karo: fdt: prevent duplicate call of fdt_fixup_ethernet()
[karo-tx-uboot.git] / board / karo / tx6 / tx6qdl.c
1 /*
2  * Copyright (C) 2012-2015 Lothar WaƟmann <LW@KARO-electronics.de>
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  *
6  */
7 #include <common.h>
8 #include <errno.h>
9 #include <libfdt.h>
10 #include <fdt_support.h>
11 #include <lcd.h>
12 #include <netdev.h>
13 #include <mmc.h>
14 #include <fsl_esdhc.h>
15 #include <video_fb.h>
16 #include <ipu.h>
17 #include <mxcfb.h>
18 #include <i2c.h>
19 #include <linux/fb.h>
20 #include <asm/io.h>
21 #include <asm/gpio.h>
22 #include <asm/arch/mx6-pins.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/hab.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/crm_regs.h>
27 #include <asm/arch/sys_proto.h>
28
29 #include "../common/karo.h"
30 #include "pmic.h"
31
32 #define __data __attribute__((section(".data")))
33
34 #define TX6_FEC_RST_GPIO                IMX_GPIO_NR(7, 6)
35 #define TX6_FEC_PWR_GPIO                IMX_GPIO_NR(3, 20)
36 #define TX6_FEC_INT_GPIO                IMX_GPIO_NR(7, 1)
37 #define TX6_LED_GPIO                    IMX_GPIO_NR(2, 20)
38
39 #define TX6_LCD_PWR_GPIO                IMX_GPIO_NR(2, 31)
40 #define TX6_LCD_RST_GPIO                IMX_GPIO_NR(3, 29)
41 #define TX6_LCD_BACKLIGHT_GPIO          IMX_GPIO_NR(1, 1)
42
43 #define TX6_RESET_OUT_GPIO              IMX_GPIO_NR(7, 12)
44 #define TX6_I2C1_SCL_GPIO               IMX_GPIO_NR(3, 21)
45 #define TX6_I2C1_SDA_GPIO               IMX_GPIO_NR(3, 28)
46
47 #ifdef CONFIG_MX6_TEMPERATURE_MIN
48 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
49 #else
50 #define TEMPERATURE_MIN                 (-40)
51 #endif
52 #ifdef CONFIG_MX6_TEMPERATURE_HOT
53 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
54 #else
55 #define TEMPERATURE_HOT                 80
56 #endif
57
58 DECLARE_GLOBAL_DATA_PTR;
59
60 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
61
62 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
63 #ifdef CONFIG_SECURE_BOOT
64 char __csf_data[0] __attribute__((section(".__csf_data")));
65 #endif
66
67 static const iomux_v3_cfg_t const tx6qdl_pads[] = {
68         /* RESET_OUT */
69         MX6_PAD_GPIO_17__GPIO7_IO12,
70
71         /* UART pads */
72 #if CONFIG_MXC_UART_BASE == UART1_BASE
73         MX6_PAD_SD3_DAT7__UART1_TX_DATA,
74         MX6_PAD_SD3_DAT6__UART1_RX_DATA,
75         MX6_PAD_SD3_DAT1__UART1_RTS_B,
76         MX6_PAD_SD3_DAT0__UART1_CTS_B,
77 #endif
78 #if CONFIG_MXC_UART_BASE == UART2_BASE
79         MX6_PAD_SD4_DAT4__UART2_RX_DATA,
80         MX6_PAD_SD4_DAT7__UART2_TX_DATA,
81         MX6_PAD_SD4_DAT5__UART2_RTS_B,
82         MX6_PAD_SD4_DAT6__UART2_CTS_B,
83 #endif
84 #if CONFIG_MXC_UART_BASE == UART3_BASE
85         MX6_PAD_EIM_D24__UART3_TX_DATA,
86         MX6_PAD_EIM_D25__UART3_RX_DATA,
87         MX6_PAD_SD3_RST__UART3_RTS_B,
88         MX6_PAD_SD3_DAT3__UART3_CTS_B,
89 #endif
90         /* internal I2C */
91         MX6_PAD_EIM_D28__I2C1_SDA,
92         MX6_PAD_EIM_D21__I2C1_SCL,
93
94         /* FEC PHY GPIO functions */
95         MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION, /* PHY POWER */
96         MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION, /* PHY RESET */
97         MX6_PAD_SD3_DAT4__GPIO7_IO01, /* PHY INT */
98 };
99
100 static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = {
101         /* FEC functions */
102         MX6_PAD_ENET_MDC__ENET_MDC,
103         MX6_PAD_ENET_MDIO__ENET_MDIO,
104         MX6_PAD_GPIO_16__ENET_REF_CLK,
105         MX6_PAD_ENET_RX_ER__ENET_RX_ER,
106         MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
107         MX6_PAD_ENET_RXD1__ENET_RX_DATA1,
108         MX6_PAD_ENET_RXD0__ENET_RX_DATA0,
109         MX6_PAD_ENET_TX_EN__ENET_TX_EN,
110         MX6_PAD_ENET_TXD1__ENET_TX_DATA1,
111         MX6_PAD_ENET_TXD0__ENET_TX_DATA0,
112 };
113
114 #define TX6_I2C_GPIO_PAD_CTRL   (PAD_CTL_PUS_22K_UP |   \
115                                 PAD_CTL_SPEED_MED |     \
116                                 PAD_CTL_DSE_34ohm |     \
117                                 PAD_CTL_SRE_FAST)
118
119 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
120         /* internal I2C */
121         MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_GPIO_PAD_CTRL),
122         MX6_PAD_EIM_D21__GPIO3_IO21 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_GPIO_PAD_CTRL),
123 };
124
125 static const iomux_v3_cfg_t const tx6_i2c_pads[] = {
126         /* internal I2C */
127         MX6_PAD_EIM_D28__I2C1_SDA,
128         MX6_PAD_EIM_D21__I2C1_SCL,
129 };
130
131 static const struct gpio const tx6qdl_gpios[] = {
132         /* These two entries are used to forcefully reinitialize the I2C bus */
133         { TX6_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
134         { TX6_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
135
136         { TX6_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", },
137         { TX6_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
138         { TX6_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
139         { TX6_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
140 };
141
142 static int pmic_addr __data;
143
144 #if defined(CONFIG_SOC_MX6Q)
145 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21        0x020e00a4
146 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28        0x020e00c4
147 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21        0x020e03b8
148 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28        0x020e03d8
149 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21      0x020e0898
150 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28      0x020e089c
151 #define I2C1_SEL_INPUT_VAL                      0
152 #endif
153 #if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
154 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21        0x020e0158
155 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28        0x020e0174
156 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21        0x020e0528
157 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28        0x020e0544
158 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21      0x020e0868
159 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28      0x020e086c
160 #define I2C1_SEL_INPUT_VAL                      1
161 #endif
162
163 #define GPIO_DR 0
164 #define GPIO_DIR 4
165 #define GPIO_PSR 8
166
167 static void tx6_i2c_recover(void)
168 {
169         int i;
170         int bad = 0;
171 #define SCL_BIT         (1 << (TX6_I2C1_SCL_GPIO % 32))
172 #define SDA_BIT         (1 << (TX6_I2C1_SDA_GPIO % 32))
173
174         if ((readl(GPIO3_BASE_ADDR + GPIO_PSR) &
175                         (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
176                 return;
177
178         debug("Clearing I2C bus\n");
179         if (!(readl(GPIO3_BASE_ADDR + GPIO_PSR) & SCL_BIT)) {
180                 printf("I2C SCL stuck LOW\n");
181                 bad++;
182
183                 writel(readl(GPIO3_BASE_ADDR + GPIO_DR) | SCL_BIT,
184                         GPIO3_BASE_ADDR + GPIO_DR);
185                 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) | SCL_BIT,
186                         GPIO3_BASE_ADDR + GPIO_DIR);
187         }
188         if (!(readl(GPIO3_BASE_ADDR + GPIO_PSR) & SDA_BIT)) {
189                 printf("I2C SDA stuck LOW\n");
190                 bad++;
191
192                 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) & ~SDA_BIT,
193                         GPIO3_BASE_ADDR + GPIO_DIR);
194                 writel(readl(GPIO3_BASE_ADDR + GPIO_DR) | SCL_BIT,
195                         GPIO3_BASE_ADDR + GPIO_DR);
196                 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) | SCL_BIT,
197                         GPIO3_BASE_ADDR + GPIO_DIR);
198
199                 imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
200                                                 ARRAY_SIZE(tx6_i2c_gpio_pads));
201                 udelay(10);
202
203                 for (i = 0; i < 18; i++) {
204                         u32 reg = readl(GPIO3_BASE_ADDR + GPIO_DR) ^ SCL_BIT;
205
206                         debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
207                         writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
208                         udelay(10);
209                         if (reg & SCL_BIT &&
210                                 readl(GPIO3_BASE_ADDR + GPIO_PSR) & SDA_BIT)
211                                 break;
212                 }
213         }
214         if (bad) {
215                 u32 reg = readl(GPIO3_BASE_ADDR + GPIO_PSR);
216
217                 if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
218                         printf("I2C bus recovery succeeded\n");
219                 } else {
220                         printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
221                                 SCL_BIT | SDA_BIT);
222                 }
223         }
224         debug("Setting up I2C Pads\n");
225         imx_iomux_v3_setup_multiple_pads(tx6_i2c_pads,
226                                         ARRAY_SIZE(tx6_i2c_pads));
227 }
228
229 /* placed in section '.data' to prevent overwriting relocation info
230  * overlayed with bss
231  */
232 static u32 wrsr __data;
233
234 #define WRSR_POR                        (1 << 4)
235 #define WRSR_TOUT                       (1 << 1)
236 #define WRSR_SFTW                       (1 << 0)
237
238 static void print_reset_cause(void)
239 {
240         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
241         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
242         u32 srsr;
243         char *dlm = "";
244
245         printf("Reset cause: ");
246
247         srsr = readl(&src_regs->srsr);
248         wrsr = readw(wdt_base + 4);
249
250         if (wrsr & WRSR_POR) {
251                 printf("%sPOR", dlm);
252                 dlm = " | ";
253         }
254         if (srsr & 0x00004) {
255                 printf("%sCSU", dlm);
256                 dlm = " | ";
257         }
258         if (srsr & 0x00008) {
259                 printf("%sIPP USER", dlm);
260                 dlm = " | ";
261         }
262         if (srsr & 0x00010) {
263                 if (wrsr & WRSR_SFTW) {
264                         printf("%sSOFT", dlm);
265                         dlm = " | ";
266                 }
267                 if (wrsr & WRSR_TOUT) {
268                         printf("%sWDOG", dlm);
269                         dlm = " | ";
270                 }
271         }
272         if (srsr & 0x00020) {
273                 printf("%sJTAG HIGH-Z", dlm);
274                 dlm = " | ";
275         }
276         if (srsr & 0x00040) {
277                 printf("%sJTAG SW", dlm);
278                 dlm = " | ";
279         }
280         if (srsr & 0x10000) {
281                 printf("%sWARM BOOT", dlm);
282                 dlm = " | ";
283         }
284         if (dlm[0] == '\0')
285                 printf("unknown");
286
287         printf("\n");
288 }
289
290 static const char __data *tx6_mod_suffix;
291
292 #ifdef CONFIG_IMX6_THERMAL
293 #include <thermal.h>
294 #include <imx_thermal.h>
295 #include <fuse.h>
296
297 static void print_temperature(void)
298 {
299         struct udevice *thermal_dev;
300         int cpu_tmp, minc, maxc, ret;
301         char const *grade_str;
302         static u32 __data thermal_calib;
303
304         puts("Temperature: ");
305         switch (get_cpu_temp_grade(&minc, &maxc)) {
306         case TEMP_AUTOMOTIVE:
307                 grade_str = "Automotive";
308                 break;
309         case TEMP_INDUSTRIAL:
310                 grade_str = "Industrial";
311                 break;
312         case TEMP_EXTCOMMERCIAL:
313                 grade_str = "Extended Commercial";
314                 break;
315         default:
316                 grade_str = "Commercial";
317         }
318         printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
319         ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
320         if (ret == 0) {
321                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
322
323                 if (ret == 0)
324                         printf(" at %dC", cpu_tmp);
325                 else
326                         puts(" - failed to read sensor data");
327         } else {
328                 puts(" - no sensor device found");
329         }
330
331         if (fuse_read(1, 6, &thermal_calib) == 0) {
332                 printf(" - calibration data 0x%08x\n", thermal_calib);
333         } else {
334                 puts(" - Failed to read thermal calib fuse\n");
335         }
336 }
337 #else
338 static inline void print_temperature(void)
339 {
340 }
341 #endif
342
343 int checkboard(void)
344 {
345         u32 cpurev = get_cpu_rev();
346         char *cpu_str = "?";
347
348         switch ((cpurev >> 12) & 0xff) {
349         case MXC_CPU_MX6SL:
350                 cpu_str = "SL";
351                 tx6_mod_suffix = "?";
352                 break;
353         case MXC_CPU_MX6DL:
354                 cpu_str = "DL";
355                 tx6_mod_suffix = "U";
356                 break;
357         case MXC_CPU_MX6SOLO:
358                 cpu_str = "SOLO";
359                 tx6_mod_suffix = "S";
360                 break;
361         case MXC_CPU_MX6Q:
362                 cpu_str = "Q";
363                 tx6_mod_suffix = "Q";
364                 break;
365         }
366
367         printf("CPU:         Freescale i.MX6%s rev%d.%d at %d MHz\n",
368                 cpu_str,
369                 (cpurev & 0x000F0) >> 4,
370                 (cpurev & 0x0000F) >> 0,
371                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
372
373         print_temperature();
374         print_reset_cause();
375 #ifdef CONFIG_MX6_TEMPERATURE_HOT
376         check_cpu_temperature(1);
377 #endif
378         tx6_i2c_recover();
379         return 0;
380 }
381
382 /* serial port not initialized at this point */
383 int board_early_init_f(void)
384 {
385         return 0;
386 }
387
388 #ifndef CONFIG_MX6_TEMPERATURE_HOT
389 static bool tx6_temp_check_enabled = true;
390 #else
391 #define tx6_temp_check_enabled  0
392 #endif
393
394 #ifdef CONFIG_TX6_NAND
395 #define TX6_FLASH_SZ    (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
396 #else
397 #ifdef CONFIG_MMC_BOOT_SIZE
398 #define TX6_FLASH_SZ    (CONFIG_MMC_BOOT_SIZE / 4096 + 2)
399 #else
400 #define TX6_FLASH_SZ    2
401 #endif
402 #endif /* CONFIG_TX6_NAND */
403
404 #define TX6_DDR_SZ      (ffs(CONFIG_SYS_SDRAM_BUS_WIDTH / 16) - 1)
405
406 static char tx6_mem_table[] = {
407         '4', /* 256MiB SDRAM 16bit; 128MiB NAND */
408         '1', /* 512MiB SDRAM 32bit; 128MiB NAND */
409         '0', /* 1GiB SDRAM 64bit; 128MiB NAND */
410         '?', /* 256MiB SDRAM 16bit; 256MiB NAND */
411         '?', /* 512MiB SDRAM 32bit; 256MiB NAND */
412         '2', /* 1GiB SDRAM 64bit; 256MiB NAND */
413         '?', /* 256MiB SDRAM 16bit; 4GiB eMMC */
414         '5', /* 512MiB SDRAM 32bit; 4GiB eMMC */
415         '3', /* 1GiB SDRAM 64bit; 4GiB eMMC */
416         '?', /* 256MiB SDRAM 16bit; 8GiB eMMC */
417         '?', /* 512MiB SDRAM 32bit; 8GiB eMMC */
418         '0', /* 1GiB SDRAM 64bit; 8GiB eMMC */
419 };
420
421 static struct {
422         uchar addr;
423         uchar rev;
424 } tx6_mod_revs[] = {
425         { 0x3c, 1, },
426         { 0x32, 2, },
427         { 0x33, 3, },
428 };
429
430 static inline char tx6_mem_suffix(void)
431 {
432         size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
433
434         debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
435                 TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
436
437         if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
438                 return '?';
439
440         return tx6_mem_table[mem_idx];
441 };
442
443 static int tx6_get_mod_rev(unsigned int pmic_id)
444 {
445         if (pmic_id < ARRAY_SIZE(tx6_mod_revs))
446                 return tx6_mod_revs[pmic_id].rev;
447
448         return 0;
449 }
450
451 static int tx6_pmic_probe(void)
452 {
453         int i;
454
455         debug("%s@%d: \n", __func__, __LINE__);
456
457 //      i2c_init_all();
458
459         for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) {
460                 u8 i2c_addr = tx6_mod_revs[i].addr;
461                 int ret = i2c_probe(i2c_addr);
462
463                 if (ret == 0) {
464                         debug("I2C probe succeeded for addr 0x%02x\n", i2c_addr);
465                         return i;
466                 }
467                 debug("I2C probe returned %d for addr 0x%02x\n", ret, i2c_addr);
468         }
469         return -EINVAL;
470 }
471
472 int board_init(void)
473 {
474         int ret;
475         u32 cpurev = get_cpu_rev();
476         int cpu_variant = (cpurev >> 12) & 0xff;
477         int pmic_id;
478
479         debug("%s@%d: \n", __func__, __LINE__);
480
481         pmic_id = tx6_pmic_probe();
482         if (pmic_id >= 0)
483                 pmic_addr = tx6_mod_revs[pmic_id].addr;
484
485         printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
486                 tx6_mod_suffix,
487                 cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
488                 is_lvds(), tx6_get_mod_rev(pmic_id),
489                 tx6_mem_suffix());
490
491         get_hab_status();
492
493         ret = gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
494         if (ret < 0) {
495                 printf("Failed to request tx6qdl_gpios: %d\n", ret);
496         }
497         imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
498
499         /* Address of boot parameters */
500         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
501         gd->bd->bi_arch_number = -1;
502
503         if (ctrlc() || (wrsr & WRSR_TOUT)) {
504                 if (wrsr & WRSR_TOUT)
505                         printf("WDOG RESET detected; Skipping PMIC setup\n");
506                 else
507                         printf("<CTRL-C> detected; safeboot enabled\n");
508 #ifndef CONFIG_MX6_TEMPERATURE_HOT
509                 tx6_temp_check_enabled = false;
510 #endif
511                 return 0;
512         }
513
514         ret = tx6_pmic_init(pmic_addr);
515         if (ret) {
516                 printf("Failed to setup PMIC voltages: %d\n", ret);
517                 hang();
518         }
519         return 0;
520 }
521
522 int dram_init(void)
523 {
524         debug("%s@%d: \n", __func__, __LINE__);
525
526         /* dram_init must store complete ramsize in gd->ram_size */
527         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
528                                 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
529         return 0;
530 }
531
532 void dram_init_banksize(void)
533 {
534         debug("%s@%d: \n", __func__, __LINE__);
535
536         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
537         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
538                         PHYS_SDRAM_1_SIZE);
539 #if CONFIG_NR_DRAM_BANKS > 1
540         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
541         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
542                         PHYS_SDRAM_2_SIZE);
543 #endif
544 }
545
546 #ifdef  CONFIG_FSL_ESDHC
547 #define SD_PAD_CTRL (PAD_CTL_PUS_47K_UP |               \
548         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |         \
549         PAD_CTL_SRE_FAST)
550
551 static const iomux_v3_cfg_t mmc0_pads[] = {
552         MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
553         MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
554         MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
555         MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
556         MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
557         MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
558         /* SD1 CD */
559         MX6_PAD_SD3_CMD__GPIO7_IO02,
560 };
561
562 static const iomux_v3_cfg_t mmc1_pads[] = {
563         MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
564         MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
565         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
566         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
567         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
568         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
569         /* SD2 CD */
570         MX6_PAD_SD3_CLK__GPIO7_IO03,
571 };
572
573 #ifdef CONFIG_TX6_EMMC
574 static const iomux_v3_cfg_t mmc3_pads[] = {
575         MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
576         MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
577         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
578         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
579         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
580         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
581         /* eMMC RESET */
582         MX6_PAD_NANDF_ALE__SD4_RESET | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
583                                                 PAD_CTL_DSE_40ohm),
584 };
585 #endif
586
587 static struct tx6_esdhc_cfg {
588         const iomux_v3_cfg_t *pads;
589         int num_pads;
590         enum mxc_clock clkid;
591         struct fsl_esdhc_cfg cfg;
592         int cd_gpio;
593 } tx6qdl_esdhc_cfg[] = {
594 #ifdef CONFIG_TX6_EMMC
595         {
596                 .pads = mmc3_pads,
597                 .num_pads = ARRAY_SIZE(mmc3_pads),
598                 .clkid = MXC_ESDHC4_CLK,
599                 .cfg = {
600                         .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
601                         .max_bus_width = 4,
602                 },
603                 .cd_gpio = -EINVAL,
604         },
605 #endif
606         {
607                 .pads = mmc0_pads,
608                 .num_pads = ARRAY_SIZE(mmc0_pads),
609                 .clkid = MXC_ESDHC_CLK,
610                 .cfg = {
611                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
612                         .max_bus_width = 4,
613                 },
614                 .cd_gpio = IMX_GPIO_NR(7, 2),
615         },
616         {
617                 .pads = mmc1_pads,
618                 .num_pads = ARRAY_SIZE(mmc1_pads),
619                 .clkid = MXC_ESDHC2_CLK,
620                 .cfg = {
621                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
622                         .max_bus_width = 4,
623                 },
624                 .cd_gpio = IMX_GPIO_NR(7, 3),
625         },
626 };
627
628 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
629 {
630         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
631 }
632
633 int board_mmc_getcd(struct mmc *mmc)
634 {
635         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
636
637         if (cfg->cd_gpio < 0)
638                 return 1;
639
640         debug("SD card %d is %spresent (GPIO %d)\n",
641                 cfg - tx6qdl_esdhc_cfg,
642                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
643                 cfg->cd_gpio);
644         return !gpio_get_value(cfg->cd_gpio);
645 }
646
647 int board_mmc_init(bd_t *bis)
648 {
649         int i;
650
651         debug("%s@%d: \n", __func__, __LINE__);
652
653         for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
654                 struct mmc *mmc;
655                 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
656                 int ret;
657
658                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
659                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
660
661                 if (cfg->cd_gpio >= 0) {
662                         ret = gpio_request_one(cfg->cd_gpio,
663                                         GPIOFLAG_INPUT, "MMC CD");
664                         if (ret) {
665                                 printf("Error %d requesting GPIO%d_%d\n",
666                                         ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
667                                 continue;
668                         }
669                 }
670
671                 debug("%s: Initializing MMC slot %d\n", __func__, i);
672                 fsl_esdhc_initialize(bis, &cfg->cfg);
673
674                 mmc = find_mmc_device(i);
675                 if (mmc == NULL)
676                         continue;
677                 if (board_mmc_getcd(mmc))
678                         mmc_init(mmc);
679         }
680         return 0;
681 }
682 #endif /* CONFIG_CMD_MMC */
683
684 #ifdef CONFIG_FEC_MXC
685
686 #ifndef ETH_ALEN
687 #define ETH_ALEN 6
688 #endif
689
690 int board_eth_init(bd_t *bis)
691 {
692         int ret;
693
694         debug("%s@%d: \n", __func__, __LINE__);
695
696         /* delay at least 21ms for the PHY internal POR signal to deassert */
697         udelay(22000);
698
699         imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads,
700                                         ARRAY_SIZE(tx6qdl_fec_pads));
701
702         /* Deassert RESET to the external phy */
703         gpio_set_value(TX6_FEC_RST_GPIO, 1);
704
705         ret = cpu_eth_init(bis);
706         if (ret)
707                 printf("cpu_eth_init() failed: %d\n", ret);
708
709         return ret;
710 }
711
712 static void tx6_init_mac(void)
713 {
714         u8 mac[ETH_ALEN];
715
716         imx_get_mac_from_fuse(0, mac);
717         if (!is_valid_ethaddr(mac)) {
718                 printf("No valid MAC address programmed\n");
719                 return;
720         }
721
722         printf("MAC addr from fuse: %pM\n", mac);
723         eth_setenv_enetaddr("ethaddr", mac);
724 }
725 #else
726 static inline void tx6_init_mac(void)
727 {
728 }
729 #endif /* CONFIG_FEC_MXC */
730
731 enum {
732         LED_STATE_INIT = -1,
733         LED_STATE_OFF,
734         LED_STATE_ON,
735 };
736
737 static inline int calc_blink_rate(void)
738 {
739         if (!tx6_temp_check_enabled)
740                 return CONFIG_SYS_HZ;
741
742         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
743                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
744                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
745 }
746
747 void show_activity(int arg)
748 {
749         static int led_state = LED_STATE_INIT;
750         static int blink_rate;
751         static ulong last;
752
753         if (led_state == LED_STATE_INIT) {
754                 last = get_timer(0);
755                 gpio_set_value(TX6_LED_GPIO, 1);
756                 led_state = LED_STATE_ON;
757                 blink_rate = calc_blink_rate();
758         } else {
759                 if (get_timer(last) > blink_rate) {
760                         blink_rate = calc_blink_rate();
761                         last = get_timer_masked();
762                         if (led_state == LED_STATE_ON) {
763                                 gpio_set_value(TX6_LED_GPIO, 0);
764                         } else {
765                                 gpio_set_value(TX6_LED_GPIO, 1);
766                         }
767                         led_state = 1 - led_state;
768                 }
769         }
770 }
771
772 static const iomux_v3_cfg_t stk5_pads[] = {
773         /* SW controlled LED on STK5 baseboard */
774         MX6_PAD_EIM_A18__GPIO2_IO20,
775
776         /* I2C bus on DIMM pins 40/41 */
777         MX6_PAD_GPIO_6__I2C3_SDA,
778         MX6_PAD_GPIO_3__I2C3_SCL,
779
780         /* TSC200x PEN IRQ */
781         MX6_PAD_EIM_D26__GPIO3_IO26,
782
783         /* EDT-FT5x06 Polytouch panel */
784         MX6_PAD_NANDF_CS2__GPIO6_IO15, /* IRQ */
785         MX6_PAD_EIM_A16__GPIO2_IO22, /* RESET */
786         MX6_PAD_EIM_A17__GPIO2_IO21, /* WAKE */
787
788         /* USBH1 */
789         MX6_PAD_EIM_D31__GPIO3_IO31, /* VBUSEN */
790         MX6_PAD_EIM_D30__GPIO3_IO30, /* OC */
791         /* USBOTG */
792         MX6_PAD_EIM_D23__GPIO3_IO23, /* USBOTG ID */
793         MX6_PAD_GPIO_7__GPIO1_IO07, /* VBUSEN */
794         MX6_PAD_GPIO_8__GPIO1_IO08, /* OC */
795 };
796
797 static const struct gpio stk5_gpios[] = {
798         { TX6_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
799
800         { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
801         { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
802         { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
803         { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
804         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
805 };
806
807 #ifdef CONFIG_LCD
808 static u16 tx6_cmap[256];
809 vidinfo_t panel_info = {
810         /* set to max. size supported by SoC */
811         .vl_col = 1920,
812         .vl_row = 1080,
813
814         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
815         .cmap = tx6_cmap,
816 };
817
818 static struct fb_videomode tx6_fb_modes[] = {
819 #ifndef CONFIG_SYS_LVDS_IF
820         {
821                 /* Standard VGA timing */
822                 .name           = "VGA",
823                 .refresh        = 60,
824                 .xres           = 640,
825                 .yres           = 480,
826                 .pixclock       = KHZ2PICOS(25175),
827                 .left_margin    = 48,
828                 .hsync_len      = 96,
829                 .right_margin   = 16,
830                 .upper_margin   = 31,
831                 .vsync_len      = 2,
832                 .lower_margin   = 12,
833                 .sync           = FB_SYNC_CLK_LAT_FALL,
834         },
835         {
836                 /* Emerging ETV570 640 x 480 display. Syncs low active,
837                  * DE high active, 115.2 mm x 86.4 mm display area
838                  * VGA compatible timing
839                  */
840                 .name           = "ETV570",
841                 .refresh        = 60,
842                 .xres           = 640,
843                 .yres           = 480,
844                 .pixclock       = KHZ2PICOS(25175),
845                 .left_margin    = 114,
846                 .hsync_len      = 30,
847                 .right_margin   = 16,
848                 .upper_margin   = 32,
849                 .vsync_len      = 3,
850                 .lower_margin   = 10,
851                 .sync           = FB_SYNC_CLK_LAT_FALL,
852         },
853         {
854                 /* Emerging ET0350G0DH6 320 x 240 display.
855                  * 70.08 mm x 52.56 mm display area.
856                  */
857                 .name           = "ET0350",
858                 .refresh        = 60,
859                 .xres           = 320,
860                 .yres           = 240,
861                 .pixclock       = KHZ2PICOS(6500),
862                 .left_margin    = 68 - 34,
863                 .hsync_len      = 34,
864                 .right_margin   = 20,
865                 .upper_margin   = 18 - 3,
866                 .vsync_len      = 3,
867                 .lower_margin   = 4,
868                 .sync           = FB_SYNC_CLK_LAT_FALL,
869         },
870         {
871                 /* Emerging ET0430G0DH6 480 x 272 display.
872                  * 95.04 mm x 53.856 mm display area.
873                  */
874                 .name           = "ET0430",
875                 .refresh        = 60,
876                 .xres           = 480,
877                 .yres           = 272,
878                 .pixclock       = KHZ2PICOS(9000),
879                 .left_margin    = 2,
880                 .hsync_len      = 41,
881                 .right_margin   = 2,
882                 .upper_margin   = 2,
883                 .vsync_len      = 10,
884                 .lower_margin   = 2,
885         },
886         {
887                 /* Emerging ET0500G0DH6 800 x 480 display.
888                  * 109.6 mm x 66.4 mm display area.
889                  */
890                 .name           = "ET0500",
891                 .refresh        = 60,
892                 .xres           = 800,
893                 .yres           = 480,
894                 .pixclock       = KHZ2PICOS(33260),
895                 .left_margin    = 216 - 128,
896                 .hsync_len      = 128,
897                 .right_margin   = 1056 - 800 - 216,
898                 .upper_margin   = 35 - 2,
899                 .vsync_len      = 2,
900                 .lower_margin   = 525 - 480 - 35,
901                 .sync           = FB_SYNC_CLK_LAT_FALL,
902         },
903         {
904                 /* Emerging ETQ570G0DH6 320 x 240 display.
905                  * 115.2 mm x 86.4 mm display area.
906                  */
907                 .name           = "ETQ570",
908                 .refresh        = 60,
909                 .xres           = 320,
910                 .yres           = 240,
911                 .pixclock       = KHZ2PICOS(6400),
912                 .left_margin    = 38,
913                 .hsync_len      = 30,
914                 .right_margin   = 30,
915                 .upper_margin   = 16, /* 15 according to datasheet */
916                 .vsync_len      = 3, /* TVP -> 1>x>5 */
917                 .lower_margin   = 4, /* 4.5 according to datasheet */
918                 .sync           = FB_SYNC_CLK_LAT_FALL,
919         },
920         {
921                 /* Emerging ET0700G0DH6 800 x 480 display.
922                  * 152.4 mm x 91.44 mm display area.
923                  */
924                 .name           = "ET0700",
925                 .refresh        = 60,
926                 .xres           = 800,
927                 .yres           = 480,
928                 .pixclock       = KHZ2PICOS(33260),
929                 .left_margin    = 216 - 128,
930                 .hsync_len      = 128,
931                 .right_margin   = 1056 - 800 - 216,
932                 .upper_margin   = 35 - 2,
933                 .vsync_len      = 2,
934                 .lower_margin   = 525 - 480 - 35,
935                 .sync           = FB_SYNC_CLK_LAT_FALL,
936         },
937         {
938                 /* Emerging ET070001DM6 800 x 480 display.
939                  * 152.4 mm x 91.44 mm display area.
940                  */
941                 .name           = "ET070001DM6",
942                 .refresh        = 60,
943                 .xres           = 800,
944                 .yres           = 480,
945                 .pixclock       = KHZ2PICOS(33260),
946                 .left_margin    = 216 - 128,
947                 .hsync_len      = 128,
948                 .right_margin   = 1056 - 800 - 216,
949                 .upper_margin   = 35 - 2,
950                 .vsync_len      = 2,
951                 .lower_margin   = 525 - 480 - 35,
952                 .sync           = 0,
953         },
954 #else
955         {
956                 /* HannStar HSD100PXN1
957                  * 202.7m mm x 152.06 mm display area.
958                  */
959                 .name           = "HSD100PXN1",
960                 .refresh        = 60,
961                 .xres           = 1024,
962                 .yres           = 768,
963                 .pixclock       = KHZ2PICOS(65000),
964                 .left_margin    = 0,
965                 .hsync_len      = 0,
966                 .right_margin   = 320,
967                 .upper_margin   = 0,
968                 .vsync_len      = 0,
969                 .lower_margin   = 38,
970                 .sync           = FB_SYNC_CLK_LAT_FALL,
971         },
972 #endif
973         {
974                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
975                 .refresh        = 60,
976                 .left_margin    = 48,
977                 .hsync_len      = 96,
978                 .right_margin   = 16,
979                 .upper_margin   = 31,
980                 .vsync_len      = 2,
981                 .lower_margin   = 12,
982                 .sync           = FB_SYNC_CLK_LAT_FALL,
983         },
984 };
985
986 static int lcd_enabled = 1;
987 static int lcd_bl_polarity;
988
989 static int lcd_backlight_polarity(void)
990 {
991         return lcd_bl_polarity;
992 }
993
994 void lcd_enable(void)
995 {
996         /* HACK ALERT:
997          * global variable from common/lcd.c
998          * Set to 0 here to prevent messages from going to LCD
999          * rather than serial console
1000          */
1001         lcd_is_enabled = 0;
1002
1003         if (lcd_enabled) {
1004                 karo_load_splashimage(1);
1005
1006                 debug("Switching LCD on\n");
1007                 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
1008                 udelay(100);
1009                 gpio_set_value(TX6_LCD_RST_GPIO, 1);
1010                 udelay(300000);
1011                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
1012                         lcd_backlight_polarity());
1013         }
1014 }
1015
1016 void lcd_disable(void)
1017 {
1018         if (lcd_enabled) {
1019                 printf("Disabling LCD\n");
1020                 ipuv3_fb_shutdown();
1021         }
1022 }
1023
1024 void lcd_panel_disable(void)
1025 {
1026         if (lcd_enabled) {
1027                 debug("Switching LCD off\n");
1028                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
1029                         !lcd_backlight_polarity());
1030                 gpio_set_value(TX6_LCD_RST_GPIO, 0);
1031                 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
1032         }
1033 }
1034
1035 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
1036         /* LCD RESET */
1037         MX6_PAD_EIM_D29__GPIO3_IO29,
1038         /* LCD POWER_ENABLE */
1039         MX6_PAD_EIM_EB3__GPIO2_IO31,
1040         /* LCD Backlight (PWM) */
1041         MX6_PAD_GPIO_1__GPIO1_IO01,
1042
1043 #ifndef CONFIG_SYS_LVDS_IF
1044         /* Display */
1045         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
1046         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
1047         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
1048         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
1049         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
1050         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
1051         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
1052         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
1053         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
1054         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
1055         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
1056         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
1057         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
1058         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
1059         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
1060         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
1061         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
1062         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
1063         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
1064         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
1065         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
1066         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
1067         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
1068         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
1069         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSYNC */
1070         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSYNC */
1071         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
1072         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
1073 #endif
1074 };
1075
1076 static const struct gpio stk5_lcd_gpios[] = {
1077         { TX6_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1078         { TX6_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1079         { TX6_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1080 };
1081
1082 void lcd_ctrl_init(void *lcdbase)
1083 {
1084         int color_depth = 24;
1085         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1086         const char *vm;
1087         unsigned long val;
1088         int refresh = 60;
1089         struct fb_videomode *p = &tx6_fb_modes[0];
1090         struct fb_videomode fb_mode;
1091         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1092         int pix_fmt;
1093         int lcd_bus_width;
1094         unsigned long di_clk_rate = 65000000;
1095
1096         if (!lcd_enabled) {
1097                 debug("LCD disabled\n");
1098                 return;
1099         }
1100
1101         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1102                 debug("Disabling LCD\n");
1103                 lcd_enabled = 0;
1104                 setenv("splashimage", NULL);
1105                 return;
1106         }
1107
1108         karo_fdt_move_fdt();
1109         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1110
1111         if (video_mode == NULL) {
1112                 debug("Disabling LCD\n");
1113                 lcd_enabled = 0;
1114                 return;
1115         }
1116         vm = video_mode;
1117         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1118                 p = &fb_mode;
1119                 debug("Using video mode from FDT\n");
1120                 vm += strlen(vm);
1121                 if (fb_mode.xres > panel_info.vl_col ||
1122                         fb_mode.yres > panel_info.vl_row) {
1123                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1124                                 fb_mode.xres, fb_mode.yres,
1125                                 panel_info.vl_col, panel_info.vl_row);
1126                         lcd_enabled = 0;
1127                         return;
1128                 }
1129         }
1130         if (p->name != NULL)
1131                 debug("Trying compiled-in video modes\n");
1132         while (p->name != NULL) {
1133                 if (strcmp(p->name, vm) == 0) {
1134                         debug("Using video mode: '%s'\n", p->name);
1135                         vm += strlen(vm);
1136                         break;
1137                 }
1138                 p++;
1139         }
1140         if (*vm != '\0')
1141                 debug("Trying to decode video_mode: '%s'\n", vm);
1142         while (*vm != '\0') {
1143                 if (*vm >= '0' && *vm <= '9') {
1144                         char *end;
1145
1146                         val = simple_strtoul(vm, &end, 0);
1147                         if (end > vm) {
1148                                 if (!xres_set) {
1149                                         if (val > panel_info.vl_col)
1150                                                 val = panel_info.vl_col;
1151                                         p->xres = val;
1152                                         panel_info.vl_col = val;
1153                                         xres_set = 1;
1154                                 } else if (!yres_set) {
1155                                         if (val > panel_info.vl_row)
1156                                                 val = panel_info.vl_row;
1157                                         p->yres = val;
1158                                         panel_info.vl_row = val;
1159                                         yres_set = 1;
1160                                 } else if (!bpp_set) {
1161                                         switch (val) {
1162                                         case 32:
1163                                         case 24:
1164                                                 if (is_lvds())
1165                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
1166                                                 /* fallthru */
1167                                         case 16:
1168                                         case 8:
1169                                                 color_depth = val;
1170                                                 break;
1171
1172                                         case 18:
1173                                                 if (is_lvds()) {
1174                                                         color_depth = val;
1175                                                         break;
1176                                                 }
1177                                                 /* fallthru */
1178                                         default:
1179                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1180                                                         end - vm, vm, color_depth);
1181                                         }
1182                                         bpp_set = 1;
1183                                 } else if (!refresh_set) {
1184                                         refresh = val;
1185                                         refresh_set = 1;
1186                                 }
1187                         }
1188                         vm = end;
1189                 }
1190                 switch (*vm) {
1191                 case '@':
1192                         bpp_set = 1;
1193                         /* fallthru */
1194                 case '-':
1195                         yres_set = 1;
1196                         /* fallthru */
1197                 case 'x':
1198                         xres_set = 1;
1199                         /* fallthru */
1200                 case 'M':
1201                 case 'R':
1202                         vm++;
1203                         break;
1204
1205                 default:
1206                         if (*vm != '\0')
1207                                 vm++;
1208                 }
1209         }
1210         if (p->xres == 0 || p->yres == 0) {
1211                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1212                 lcd_enabled = 0;
1213                 printf("Supported video modes are:");
1214                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1215                         printf(" %s", p->name);
1216                 }
1217                 printf("\n");
1218                 return;
1219         }
1220         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1221                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1222                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1223                 lcd_enabled = 0;
1224                 return;
1225         }
1226         panel_info.vl_col = p->xres;
1227         panel_info.vl_row = p->yres;
1228
1229         switch (color_depth) {
1230         case 8:
1231                 panel_info.vl_bpix = LCD_COLOR8;
1232                 break;
1233         case 16:
1234                 panel_info.vl_bpix = LCD_COLOR16;
1235                 break;
1236         default:
1237                 panel_info.vl_bpix = LCD_COLOR32;
1238         }
1239
1240         p->pixclock = KHZ2PICOS(refresh *
1241                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1242                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1243                                 1000);
1244         debug("Pixel clock set to %lu.%03lu MHz\n",
1245                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1246
1247         if (p != &fb_mode) {
1248                 int ret;
1249
1250                 debug("Creating new display-timing node from '%s'\n",
1251                         video_mode);
1252                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1253                 if (ret)
1254                         printf("Failed to create new display-timing node from '%s': %d\n",
1255                                 video_mode, ret);
1256         }
1257
1258         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1259         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1260                                         ARRAY_SIZE(stk5_lcd_pads));
1261
1262         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1263         switch (lcd_bus_width) {
1264         case 24:
1265                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1266                 break;
1267
1268         case 18:
1269                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1270                 break;
1271
1272         case 16:
1273                 if (!is_lvds()) {
1274                         pix_fmt = IPU_PIX_FMT_RGB565;
1275                         break;
1276                 }
1277                 /* fallthru */
1278         default:
1279                 lcd_enabled = 0;
1280                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1281                         lcd_bus_width);
1282                 return;
1283         }
1284         if (is_lvds()) {
1285                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1286                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1287                 uint32_t gpr2;
1288                 uint32_t gpr3;
1289
1290                 if (lvds_chan_mask == 0) {
1291                         printf("No LVDS channel active\n");
1292                         lcd_enabled = 0;
1293                         return;
1294                 }
1295
1296                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1297                 if (lcd_bus_width == 24)
1298                         gpr2 |= (1 << 5) | (1 << 7);
1299                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1300                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1301                 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1302                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1303
1304                 gpr3 = readl(IOMUXC_BASE_ADDR + 0xc);
1305                 gpr3 &= ~((3 << 8) | (3 << 6));
1306                 writel(gpr3, IOMUXC_BASE_ADDR + 0xc);
1307         }
1308         if (karo_load_splashimage(0) == 0) {
1309                 int ret;
1310
1311                 debug("Initializing LCD controller\n");
1312                 ret = ipuv3_fb_init(p, 0, pix_fmt,
1313                                 is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
1314                                 di_clk_rate, -1);
1315                 if (ret) {
1316                         printf("Failed to initialize FB driver: %d\n", ret);
1317                         lcd_enabled = 0;
1318                 }
1319         } else {
1320                 debug("Skipping initialization of LCD controller\n");
1321         }
1322 }
1323 #else
1324 #define lcd_enabled 0
1325 #endif /* CONFIG_LCD */
1326
1327 static void stk5_board_init(void)
1328 {
1329         int ret;
1330
1331         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1332         if (ret < 0) {
1333                 printf("Failed to request stk5_gpios: %d\n", ret);
1334                 return;
1335         }
1336         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1337 }
1338
1339 static void stk5v3_board_init(void)
1340 {
1341         stk5_board_init();
1342 }
1343
1344 static void stk5v5_board_init(void)
1345 {
1346         int ret;
1347
1348         stk5_board_init();
1349
1350         ret = gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH,
1351                         "Flexcan Transceiver");
1352         if (ret) {
1353                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1354                 return;
1355         }
1356
1357         imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21);
1358 }
1359
1360 static void tx6qdl_set_cpu_clock(void)
1361 {
1362         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1363
1364         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1365                 return;
1366
1367         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1368                 printf("%s detected; skipping cpu clock change\n",
1369                         (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1370                 return;
1371         }
1372         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1373                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1374                 printf("CPU clock set to %lu.%03lu MHz\n",
1375                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1376         } else {
1377                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1378         }
1379 }
1380
1381 int board_late_init(void)
1382 {
1383         int ret = 0;
1384         const char *baseboard;
1385 #if 1
1386         /* override secure_boot fuse */
1387         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1388         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1389
1390         writel(0x12, &fuse->cfg5);
1391 #endif
1392
1393         debug("%s@%d: \n", __func__, __LINE__);
1394
1395         env_cleanup();
1396
1397         if (tx6_temp_check_enabled)
1398                 check_cpu_temperature(1);
1399
1400         tx6qdl_set_cpu_clock();
1401
1402         if (had_ctrlc())
1403                 setenv_ulong("safeboot", 1);
1404         else if (wrsr & WRSR_TOUT)
1405                 setenv_ulong("wdreset", 1);
1406         else
1407                 karo_fdt_move_fdt();
1408
1409         baseboard = getenv("baseboard");
1410         if (!baseboard)
1411                 goto exit;
1412
1413         printf("Baseboard: %s\n", baseboard);
1414
1415         if (strncmp(baseboard, "stk5", 4) == 0) {
1416                 if ((strlen(baseboard) == 4) ||
1417                         strcmp(baseboard, "stk5-v3") == 0) {
1418                         stk5v3_board_init();
1419                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1420                         const char *otg_mode = getenv("otg_mode");
1421
1422                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1423                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1424                                         otg_mode, baseboard);
1425                                 setenv("otg_mode", "none");
1426                         }
1427                         stk5v5_board_init();
1428                 } else {
1429                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1430                                 baseboard + 4);
1431                 }
1432         } else {
1433                 printf("WARNING: Unsupported baseboard: '%s'\n",
1434                         baseboard);
1435                 ret = -EINVAL;
1436         }
1437
1438 exit:
1439         tx6_init_mac();
1440
1441         gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1442         clear_ctrlc();
1443         return ret;
1444 }
1445
1446 #ifdef CONFIG_SERIAL_TAG
1447 void get_board_serial(struct tag_serialnr *serialnr)
1448 {
1449         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1450         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1451
1452         serialnr->low = readl(&fuse->cfg0);
1453         serialnr->high = readl(&fuse->cfg1);
1454 }
1455 #endif
1456
1457 #if defined(CONFIG_OF_BOARD_SETUP)
1458 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1459 #include <jffs2/jffs2.h>
1460 #include <mtd_node.h>
1461 static struct node_info nodes[] = {
1462         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1463 };
1464 #else
1465 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1466 #endif
1467
1468 static const char *tx6_touchpanels[] = {
1469         "ti,tsc2007",
1470         "edt,edt-ft5x06",
1471         "eeti,egalax_ts",
1472 };
1473
1474 int ft_board_setup(void *blob, bd_t *bd)
1475 {
1476         const char *baseboard = getenv("baseboard");
1477         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1478         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1479         int ret;
1480
1481         ret = fdt_increase_size(blob, 4096);
1482         if (ret) {
1483                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1484                 return ret;
1485         }
1486         if (stk5_v5)
1487                 karo_fdt_enable_node(blob, "stk5led", 0);
1488
1489         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1490
1491         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1492                                 ARRAY_SIZE(tx6_touchpanels));
1493         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1494         karo_fdt_fixup_flexcan(blob, stk5_v5);
1495
1496         karo_fdt_update_fb_mode(blob, video_mode);
1497
1498         return 0;
1499 }
1500 #endif /* CONFIG_OF_BOARD_SETUP */