5d2317dde43072ad72a692b91942587452499495
[karo-tx-uboot.git] / board / karo / tx6 / tx6qdl.c
1 /*
2  * Copyright (C) 2012,2013 Lothar WaƟmann <LW@KARO-electronics.de>
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License
9  * version 2 as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17
18 #include <common.h>
19 #include <errno.h>
20 #include <libfdt.h>
21 #include <fdt_support.h>
22 #include <lcd.h>
23 #include <netdev.h>
24 #include <mmc.h>
25 #include <fsl_esdhc.h>
26 #include <video_fb.h>
27 #include <ipu.h>
28 #include <mxcfb.h>
29 #include <i2c.h>
30 #include <linux/fb.h>
31 #include <asm/io.h>
32 #include <asm/gpio.h>
33 #include <asm/arch/mx6-pins.h>
34 #include <asm/arch/clock.h>
35 #include <asm/arch/imx-regs.h>
36 #include <asm/arch/crm_regs.h>
37 #include <asm/arch/sys_proto.h>
38
39 #include "../common/karo.h"
40 #include "pmic.h"
41
42 #define TX6_FEC_RST_GPIO                IMX_GPIO_NR(7, 6)
43 #define TX6_FEC_PWR_GPIO                IMX_GPIO_NR(3, 20)
44 #define TX6_FEC_INT_GPIO                IMX_GPIO_NR(7, 1)
45 #define TX6_LED_GPIO                    IMX_GPIO_NR(2, 20)
46
47 #define TX6_LCD_PWR_GPIO                IMX_GPIO_NR(2, 31)
48 #define TX6_LCD_RST_GPIO                IMX_GPIO_NR(3, 29)
49 #define TX6_LCD_BACKLIGHT_GPIO          IMX_GPIO_NR(1, 1)
50
51 #define TX6_RESET_OUT_GPIO              IMX_GPIO_NR(7, 12)
52
53 #define TEMPERATURE_MIN                 -40
54 #define TEMPERATURE_HOT                 80
55 #define TEMPERATURE_MAX                 125
56
57 DECLARE_GLOBAL_DATA_PTR;
58
59 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
60
61 static const iomux_v3_cfg_t tx6qdl_pads[] = {
62 #ifndef CONFIG_NO_NAND
63         /* NAND flash pads */
64         MX6_PAD_NANDF_CLE__RAWNAND_CLE,
65         MX6_PAD_NANDF_ALE__RAWNAND_ALE,
66         MX6_PAD_NANDF_WP_B__RAWNAND_RESETN,
67         MX6_PAD_NANDF_RB0__RAWNAND_READY0,
68         MX6_PAD_NANDF_CS0__RAWNAND_CE0N,
69         MX6_PAD_SD4_CMD__RAWNAND_RDN,
70         MX6_PAD_SD4_CLK__RAWNAND_WRN,
71         MX6_PAD_NANDF_D0__RAWNAND_D0,
72         MX6_PAD_NANDF_D1__RAWNAND_D1,
73         MX6_PAD_NANDF_D2__RAWNAND_D2,
74         MX6_PAD_NANDF_D3__RAWNAND_D3,
75         MX6_PAD_NANDF_D4__RAWNAND_D4,
76         MX6_PAD_NANDF_D5__RAWNAND_D5,
77         MX6_PAD_NANDF_D6__RAWNAND_D6,
78         MX6_PAD_NANDF_D7__RAWNAND_D7,
79 #endif
80         /* RESET_OUT */
81         MX6_PAD_GPIO_17__GPIO_7_12,
82
83         /* UART pads */
84 #if CONFIG_MXC_UART_BASE == UART1_BASE
85         MX6_PAD_SD3_DAT7__UART1_TXD,
86         MX6_PAD_SD3_DAT6__UART1_RXD,
87         MX6_PAD_SD3_DAT1__UART1_RTS,
88         MX6_PAD_SD3_DAT0__UART1_CTS,
89 #endif
90 #if CONFIG_MXC_UART_BASE == UART2_BASE
91         MX6_PAD_SD4_DAT4__UART2_RXD,
92         MX6_PAD_SD4_DAT7__UART2_TXD,
93         MX6_PAD_SD4_DAT5__UART2_RTS,
94         MX6_PAD_SD4_DAT6__UART2_CTS,
95 #endif
96 #if CONFIG_MXC_UART_BASE == UART3_BASE
97         MX6_PAD_EIM_D24__UART3_TXD,
98         MX6_PAD_EIM_D25__UART3_RXD,
99         MX6_PAD_SD3_RST__UART3_RTS,
100         MX6_PAD_SD3_DAT3__UART3_CTS,
101 #endif
102         /* internal I2C */
103         MX6_PAD_EIM_D28__I2C1_SDA,
104         MX6_PAD_EIM_D21__I2C1_SCL,
105
106         /* FEC PHY GPIO functions */
107         MX6_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */
108         MX6_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */
109         MX6_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */
110 };
111
112 static const iomux_v3_cfg_t tx6qdl_fec_pads[] = {
113         /* FEC functions */
114         MX6_PAD_ENET_MDC__ENET_MDC,
115         MX6_PAD_ENET_MDIO__ENET_MDIO,
116         MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
117         MX6_PAD_ENET_RX_ER__ENET_RX_ER,
118         MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
119         MX6_PAD_ENET_RXD1__ENET_RDATA_1,
120         MX6_PAD_ENET_RXD0__ENET_RDATA_0,
121         MX6_PAD_ENET_TX_EN__ENET_TX_EN,
122         MX6_PAD_ENET_TXD1__ENET_TDATA_1,
123         MX6_PAD_ENET_TXD0__ENET_TDATA_0,
124 };
125
126 static const struct gpio tx6qdl_gpios[] = {
127         { TX6_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
128         { TX6_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
129         { TX6_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
130         { TX6_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
131 };
132
133 /*
134  * Functions
135  */
136 /* placed in section '.data' to prevent overwriting relocation info
137  * overlayed with bss
138  */
139 static u32 wrsr __attribute__((section(".data")));
140
141 #define WRSR_POR                        (1 << 4)
142 #define WRSR_TOUT                       (1 << 1)
143 #define WRSR_SFTW                       (1 << 0)
144
145 static void print_reset_cause(void)
146 {
147         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
148         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
149         u32 srsr;
150         char *dlm = "";
151
152         printf("Reset cause: ");
153
154         srsr = readl(&src_regs->srsr);
155         wrsr = readw(wdt_base + 4);
156
157         if (wrsr & WRSR_POR) {
158                 printf("%sPOR", dlm);
159                 dlm = " | ";
160         }
161         if (srsr & 0x00004) {
162                 printf("%sCSU", dlm);
163                 dlm = " | ";
164         }
165         if (srsr & 0x00008) {
166                 printf("%sIPP USER", dlm);
167                 dlm = " | ";
168         }
169         if (srsr & 0x00010) {
170                 if (wrsr & WRSR_SFTW) {
171                         printf("%sSOFT", dlm);
172                         dlm = " | ";
173                 }
174                 if (wrsr & WRSR_TOUT) {
175                         printf("%sWDOG", dlm);
176                         dlm = " | ";
177                 }
178         }
179         if (srsr & 0x00020) {
180                 printf("%sJTAG HIGH-Z", dlm);
181                 dlm = " | ";
182         }
183         if (srsr & 0x00040) {
184                 printf("%sJTAG SW", dlm);
185                 dlm = " | ";
186         }
187         if (srsr & 0x10000) {
188                 printf("%sWARM BOOT", dlm);
189                 dlm = " | ";
190         }
191         if (dlm[0] == '\0')
192                 printf("unknown");
193
194         printf("\n");
195 }
196
197 int read_cpu_temperature(void);
198 int check_cpu_temperature(int boot);
199
200 static const char *tx6_mod_suffix;
201
202 static void tx6qdl_print_cpuinfo(void)
203 {
204         u32 cpurev = get_cpu_rev();
205         char *cpu_str = "?";
206
207         switch ((cpurev >> 12) & 0xff) {
208         case MXC_CPU_MX6SL:
209                 cpu_str = "SL";
210                 tx6_mod_suffix = "?";
211                 break;
212         case MXC_CPU_MX6DL:
213                 cpu_str = "DL";
214                 tx6_mod_suffix = "U";
215                 break;
216         case MXC_CPU_MX6SOLO:
217                 cpu_str = "SOLO";
218                 tx6_mod_suffix = "S";
219                 break;
220         case MXC_CPU_MX6Q:
221                 cpu_str = "Q";
222                 tx6_mod_suffix = "Q";
223                 break;
224         }
225
226         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
227                 cpu_str,
228                 (cpurev & 0x000F0) >> 4,
229                 (cpurev & 0x0000F) >> 0,
230                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
231
232         print_reset_cause();
233         check_cpu_temperature(1);
234 }
235
236 int board_early_init_f(void)
237 {
238         gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
239         imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
240
241         return 0;
242 }
243
244 int board_init(void)
245 {
246         int ret;
247
248         /* Address of boot parameters */
249         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
250         gd->bd->bi_arch_number = -1;
251
252         if (ctrlc()) {
253                 printf("CTRL-C detected; Skipping PMIC setup\n");
254                 return 1;
255         }
256
257         ret = setup_pmic_voltages();
258         if (ret) {
259                 printf("Failed to setup PMIC voltages\n");
260                 hang();
261         }
262         return 0;
263 }
264
265 int dram_init(void)
266 {
267         /* dram_init must store complete ramsize in gd->ram_size */
268         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
269                                 PHYS_SDRAM_1_SIZE);
270         return 0;
271 }
272
273 void dram_init_banksize(void)
274 {
275         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
276         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
277                         PHYS_SDRAM_1_SIZE);
278 #if CONFIG_NR_DRAM_BANKS > 1
279         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
280         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
281                         PHYS_SDRAM_2_SIZE);
282 #endif
283 }
284
285 #ifdef  CONFIG_CMD_MMC
286 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
287         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
288         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
289
290 static const iomux_v3_cfg_t mmc0_pads[] = {
291         MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
292         MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
293         MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
294         MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
295         MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
296         MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
297         /* SD1 CD */
298         MX6_PAD_SD3_CMD__GPIO_7_2,
299 };
300
301 static const iomux_v3_cfg_t mmc1_pads[] = {
302         MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
303         MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
304         MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
305         MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
306         MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
307         MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
308         /* SD2 CD */
309         MX6_PAD_SD3_CLK__GPIO_7_3,
310 };
311
312 #ifdef CONFIG_MMC_BOOT_SIZE
313 static const iomux_v3_cfg_t mmc3_pads[] = {
314         MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
315         MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
316         MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
317         MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
318         MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
319         MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
320         /* eMMC RESET */
321         MX6_PAD_NANDF_ALE__USDHC4_RST,
322 };
323 #endif
324
325 static struct tx6_esdhc_cfg {
326         const iomux_v3_cfg_t *pads;
327         int num_pads;
328         enum mxc_clock clkid;
329         struct fsl_esdhc_cfg cfg;
330         int cd_gpio;
331 } tx6qdl_esdhc_cfg[] = {
332 #ifdef CONFIG_MMC_BOOT_SIZE
333         {
334                 .pads = mmc3_pads,
335                 .num_pads = ARRAY_SIZE(mmc3_pads),
336                 .clkid = MXC_ESDHC4_CLK,
337                 .cfg = {
338                         .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
339                         .max_bus_width = 4,
340                 },
341                 .cd_gpio = -EINVAL,
342         },
343 #endif
344         {
345                 .pads = mmc0_pads,
346                 .num_pads = ARRAY_SIZE(mmc0_pads),
347                 .clkid = MXC_ESDHC_CLK,
348                 .cfg = {
349                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
350                         .max_bus_width = 4,
351                 },
352                 .cd_gpio = IMX_GPIO_NR(7, 2),
353         },
354         {
355                 .pads = mmc1_pads,
356                 .num_pads = ARRAY_SIZE(mmc1_pads),
357                 .clkid = MXC_ESDHC2_CLK,
358                 .cfg = {
359                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
360                         .max_bus_width = 4,
361                 },
362                 .cd_gpio = IMX_GPIO_NR(7, 3),
363         },
364 };
365
366 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
367 {
368         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
369 }
370
371 int board_mmc_getcd(struct mmc *mmc)
372 {
373         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
374
375         if (cfg->cd_gpio < 0)
376                 return 1;
377
378         debug("SD card %d is %spresent\n",
379                 cfg - tx6qdl_esdhc_cfg,
380                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
381         return !gpio_get_value(cfg->cd_gpio);
382 }
383
384 int board_mmc_init(bd_t *bis)
385 {
386         int i;
387
388         for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
389                 struct mmc *mmc;
390                 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
391                 int ret;
392
393                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
394                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
395
396                 if (cfg->cd_gpio >= 0) {
397                         ret = gpio_request_one(cfg->cd_gpio,
398                                         GPIOF_INPUT, "MMC CD");
399                         if (ret) {
400                                 printf("Error %d requesting GPIO%d_%d\n",
401                                         ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
402                                 continue;
403                         }
404                 }
405
406                 debug("%s: Initializing MMC slot %d\n", __func__, i);
407                 fsl_esdhc_initialize(bis, &cfg->cfg);
408
409                 mmc = find_mmc_device(i);
410                 if (mmc == NULL)
411                         continue;
412                 if (board_mmc_getcd(mmc))
413                         mmc_init(mmc);
414         }
415         return 0;
416 }
417 #endif /* CONFIG_CMD_MMC */
418
419 #ifdef CONFIG_FEC_MXC
420
421 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
422                         PAD_CTL_SRE_FAST)
423 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
424 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
425
426 #ifndef ETH_ALEN
427 #define ETH_ALEN 6
428 #endif
429
430 int board_eth_init(bd_t *bis)
431 {
432         int ret;
433
434         /* delay at least 21ms for the PHY internal POR signal to deassert */
435         udelay(22000);
436
437         imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads, ARRAY_SIZE(tx6qdl_fec_pads));
438
439         /* Deassert RESET to the external phy */
440         gpio_set_value(TX6_FEC_RST_GPIO, 1);
441
442         ret = cpu_eth_init(bis);
443         if (ret)
444                 printf("cpu_eth_init() failed: %d\n", ret);
445
446         return ret;
447 }
448 #endif /* CONFIG_FEC_MXC */
449
450 enum {
451         LED_STATE_INIT = -1,
452         LED_STATE_OFF,
453         LED_STATE_ON,
454 };
455
456 static inline int calc_blink_rate(int tmp)
457 {
458         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
459                 (tmp - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
460                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
461 }
462
463 void show_activity(int arg)
464 {
465         static int led_state = LED_STATE_INIT;
466         static int blink_rate;
467         static ulong last;
468
469         if (led_state == LED_STATE_INIT) {
470                 last = get_timer(0);
471                 gpio_set_value(TX6_LED_GPIO, 1);
472                 led_state = LED_STATE_ON;
473                 blink_rate = calc_blink_rate(check_cpu_temperature(0));
474         } else {
475                 if (get_timer(last) > blink_rate) {
476                         blink_rate = calc_blink_rate(check_cpu_temperature(0));
477                         last = get_timer_masked();
478                         if (led_state == LED_STATE_ON) {
479                                 gpio_set_value(TX6_LED_GPIO, 0);
480                         } else {
481                                 gpio_set_value(TX6_LED_GPIO, 1);
482                         }
483                         led_state = 1 - led_state;
484                 }
485         }
486 }
487
488 static const iomux_v3_cfg_t stk5_pads[] = {
489         /* SW controlled LED on STK5 baseboard */
490         MX6_PAD_EIM_A18__GPIO_2_20,
491
492         /* I2C bus on DIMM pins 40/41 */
493         MX6_PAD_GPIO_6__I2C3_SDA,
494         MX6_PAD_GPIO_3__I2C3_SCL,
495
496         /* TSC200x PEN IRQ */
497         MX6_PAD_EIM_D26__GPIO_3_26,
498
499         /* EDT-FT5x06 Polytouch panel */
500         MX6_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */
501         MX6_PAD_EIM_A16__GPIO_2_22, /* RESET */
502         MX6_PAD_EIM_A17__GPIO_2_21, /* WAKE */
503
504         /* USBH1 */
505         MX6_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */
506         MX6_PAD_EIM_D30__GPIO_3_30, /* OC */
507         /* USBOTG */
508         MX6_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */
509         MX6_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */
510         MX6_PAD_GPIO_8__GPIO_1_8, /* OC */
511 };
512
513 static const struct gpio stk5_gpios[] = {
514         { TX6_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
515
516         { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", },
517         { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
518         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
519         { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
520         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
521 };
522
523 #ifdef CONFIG_LCD
524 static u16 tx6_cmap[256];
525 vidinfo_t panel_info = {
526         /* set to max. size supported by SoC */
527         .vl_col = 1920,
528         .vl_row = 1080,
529
530         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
531         .cmap = tx6_cmap,
532 };
533
534 static struct fb_videomode tx6_fb_modes[] = {
535 #ifndef CONFIG_SYS_LVDS_IF
536         {
537                 /* Standard VGA timing */
538                 .name           = "VGA",
539                 .refresh        = 60,
540                 .xres           = 640,
541                 .yres           = 480,
542                 .pixclock       = KHZ2PICOS(25175),
543                 .left_margin    = 48,
544                 .hsync_len      = 96,
545                 .right_margin   = 16,
546                 .upper_margin   = 31,
547                 .vsync_len      = 2,
548                 .lower_margin   = 12,
549                 .sync           = FB_SYNC_CLK_LAT_FALL,
550         },
551         {
552                 /* Emerging ETV570 640 x 480 display. Syncs low active,
553                  * DE high active, 115.2 mm x 86.4 mm display area
554                  * VGA compatible timing
555                  */
556                 .name           = "ETV570",
557                 .refresh        = 60,
558                 .xres           = 640,
559                 .yres           = 480,
560                 .pixclock       = KHZ2PICOS(25175),
561                 .left_margin    = 114,
562                 .hsync_len      = 30,
563                 .right_margin   = 16,
564                 .upper_margin   = 32,
565                 .vsync_len      = 3,
566                 .lower_margin   = 10,
567                 .sync           = FB_SYNC_CLK_LAT_FALL,
568         },
569         {
570                 /* Emerging ET0350G0DH6 320 x 240 display.
571                  * 70.08 mm x 52.56 mm display area.
572                  */
573                 .name           = "ET0350",
574                 .refresh        = 60,
575                 .xres           = 320,
576                 .yres           = 240,
577                 .pixclock       = KHZ2PICOS(6500),
578                 .left_margin    = 68 - 34,
579                 .hsync_len      = 34,
580                 .right_margin   = 20,
581                 .upper_margin   = 18 - 3,
582                 .vsync_len      = 3,
583                 .lower_margin   = 4,
584                 .sync           = FB_SYNC_CLK_LAT_FALL,
585         },
586         {
587                 /* Emerging ET0430G0DH6 480 x 272 display.
588                  * 95.04 mm x 53.856 mm display area.
589                  */
590                 .name           = "ET0430",
591                 .refresh        = 60,
592                 .xres           = 480,
593                 .yres           = 272,
594                 .pixclock       = KHZ2PICOS(9000),
595                 .left_margin    = 2,
596                 .hsync_len      = 41,
597                 .right_margin   = 2,
598                 .upper_margin   = 2,
599                 .vsync_len      = 10,
600                 .lower_margin   = 2,
601                 .sync           = FB_SYNC_CLK_LAT_FALL,
602         },
603         {
604                 /* Emerging ET0500G0DH6 800 x 480 display.
605                  * 109.6 mm x 66.4 mm display area.
606                  */
607                 .name           = "ET0500",
608                 .refresh        = 60,
609                 .xres           = 800,
610                 .yres           = 480,
611                 .pixclock       = KHZ2PICOS(33260),
612                 .left_margin    = 216 - 128,
613                 .hsync_len      = 128,
614                 .right_margin   = 1056 - 800 - 216,
615                 .upper_margin   = 35 - 2,
616                 .vsync_len      = 2,
617                 .lower_margin   = 525 - 480 - 35,
618                 .sync           = FB_SYNC_CLK_LAT_FALL,
619         },
620         {
621                 /* Emerging ETQ570G0DH6 320 x 240 display.
622                  * 115.2 mm x 86.4 mm display area.
623                  */
624                 .name           = "ETQ570",
625                 .refresh        = 60,
626                 .xres           = 320,
627                 .yres           = 240,
628                 .pixclock       = KHZ2PICOS(6400),
629                 .left_margin    = 38,
630                 .hsync_len      = 30,
631                 .right_margin   = 30,
632                 .upper_margin   = 16, /* 15 according to datasheet */
633                 .vsync_len      = 3, /* TVP -> 1>x>5 */
634                 .lower_margin   = 4, /* 4.5 according to datasheet */
635                 .sync           = FB_SYNC_CLK_LAT_FALL,
636         },
637         {
638                 /* Emerging ET0700G0DH6 800 x 480 display.
639                  * 152.4 mm x 91.44 mm display area.
640                  */
641                 .name           = "ET0700",
642                 .refresh        = 60,
643                 .xres           = 800,
644                 .yres           = 480,
645                 .pixclock       = KHZ2PICOS(33260),
646                 .left_margin    = 216 - 128,
647                 .hsync_len      = 128,
648                 .right_margin   = 1056 - 800 - 216,
649                 .upper_margin   = 35 - 2,
650                 .vsync_len      = 2,
651                 .lower_margin   = 525 - 480 - 35,
652                 .sync           = FB_SYNC_CLK_LAT_FALL,
653         },
654         {
655                 /* Emerging ET070001DM6 800 x 480 display.
656                  * 152.4 mm x 91.44 mm display area.
657                  */
658                 .name           = "ET070001DM6",
659                 .refresh        = 60,
660                 .xres           = 800,
661                 .yres           = 480,
662                 .pixclock       = KHZ2PICOS(33260),
663                 .left_margin    = 216 - 128,
664                 .hsync_len      = 128,
665                 .right_margin   = 1056 - 800 - 216,
666                 .upper_margin   = 35 - 2,
667                 .vsync_len      = 2,
668                 .lower_margin   = 525 - 480 - 35,
669                 .sync           = 0,
670         },
671 #else
672         {
673                 /* HannStar HSD100PXN1
674                  * 202.7m mm x 152.06 mm display area.
675                  */
676                 .name           = "HSD100PXN1",
677                 .refresh        = 60,
678                 .xres           = 1024,
679                 .yres           = 768,
680                 .pixclock       = KHZ2PICOS(65000),
681                 .left_margin    = 0,
682                 .hsync_len      = 0,
683                 .right_margin   = 320,
684                 .upper_margin   = 0,
685                 .vsync_len      = 0,
686                 .lower_margin   = 38,
687                 .sync           = FB_SYNC_CLK_LAT_FALL,
688         },
689 #endif
690         {
691                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
692                 .refresh        = 60,
693                 .left_margin    = 48,
694                 .hsync_len      = 96,
695                 .right_margin   = 16,
696                 .upper_margin   = 31,
697                 .vsync_len      = 2,
698                 .lower_margin   = 12,
699                 .sync           = FB_SYNC_CLK_LAT_FALL,
700         },
701 };
702
703 static int lcd_enabled = 1;
704 static int lcd_bl_polarity;
705
706 static int lcd_backlight_polarity(void)
707 {
708         return lcd_bl_polarity;
709 }
710
711 void lcd_enable(void)
712 {
713         /* HACK ALERT:
714          * global variable from common/lcd.c
715          * Set to 0 here to prevent messages from going to LCD
716          * rather than serial console
717          */
718         lcd_is_enabled = 0;
719
720         karo_load_splashimage(1);
721
722         if (lcd_enabled) {
723                 debug("Switching LCD on\n");
724                 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
725                 udelay(100);
726                 gpio_set_value(TX6_LCD_RST_GPIO, 1);
727                 udelay(300000);
728                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
729                         lcd_backlight_polarity());
730         }
731 }
732
733 void lcd_disable(void)
734 {
735         if (lcd_enabled) {
736                 printf("Disabling LCD\n");
737                 ipuv3_fb_shutdown();
738         }
739 }
740
741 void lcd_panel_disable(void)
742 {
743         if (lcd_enabled) {
744                 debug("Switching LCD off\n");
745                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
746                         !lcd_backlight_polarity());
747                 gpio_set_value(TX6_LCD_RST_GPIO, 0);
748                 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
749         }
750 }
751
752 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
753         /* LCD RESET */
754         MX6_PAD_EIM_D29__GPIO_3_29,
755         /* LCD POWER_ENABLE */
756         MX6_PAD_EIM_EB3__GPIO_2_31,
757         /* LCD Backlight (PWM) */
758         MX6_PAD_GPIO_1__GPIO_1_1,
759
760 #ifndef CONFIG_SYS_LVDS_IF
761         /* Display */
762         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
763         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
764         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
765         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
766         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
767         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
768         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
769         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
770         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
771         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
772         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
773         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
774         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
775         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
776         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
777         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
778         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
779         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
780         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
781         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
782         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
783         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
784         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
785         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
786         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */
787         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */
788         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
789         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
790 #endif
791 };
792
793 static const struct gpio stk5_lcd_gpios[] = {
794         { TX6_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
795         { TX6_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
796         { TX6_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
797 };
798
799 void lcd_ctrl_init(void *lcdbase)
800 {
801         int color_depth = 24;
802         const char *video_mode = karo_get_vmode(getenv("video_mode"));
803         const char *vm;
804         unsigned long val;
805         int refresh = 60;
806         struct fb_videomode *p = &tx6_fb_modes[0];
807         struct fb_videomode fb_mode;
808         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
809         int pix_fmt;
810         int lcd_bus_width;
811         unsigned long di_clk_rate = 65000000;
812
813         if (!lcd_enabled) {
814                 debug("LCD disabled\n");
815                 return;
816         }
817
818         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
819                 debug("Disabling LCD\n");
820                 lcd_enabled = 0;
821                 setenv("splashimage", NULL);
822                 return;
823         }
824
825         karo_fdt_move_fdt();
826         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
827
828         if (video_mode == NULL) {
829                 debug("Disabling LCD\n");
830                 lcd_enabled = 0;
831                 return;
832         }
833         vm = video_mode;
834         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
835                 p = &fb_mode;
836                 debug("Using video mode from FDT\n");
837                 vm += strlen(vm);
838                 if (fb_mode.xres > panel_info.vl_col ||
839                         fb_mode.yres > panel_info.vl_row) {
840                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
841                                 fb_mode.xres, fb_mode.yres,
842                                 panel_info.vl_col, panel_info.vl_row);
843                         lcd_enabled = 0;
844                         return;
845                 }
846         }
847         if (p->name != NULL)
848                 debug("Trying compiled-in video modes\n");
849         while (p->name != NULL) {
850                 if (strcmp(p->name, vm) == 0) {
851                         debug("Using video mode: '%s'\n", p->name);
852                         vm += strlen(vm);
853                         break;
854                 }
855                 p++;
856         }
857         if (*vm != '\0')
858                 debug("Trying to decode video_mode: '%s'\n", vm);
859         while (*vm != '\0') {
860                 if (*vm >= '0' && *vm <= '9') {
861                         char *end;
862
863                         val = simple_strtoul(vm, &end, 0);
864                         if (end > vm) {
865                                 if (!xres_set) {
866                                         if (val > panel_info.vl_col)
867                                                 val = panel_info.vl_col;
868                                         p->xres = val;
869                                         panel_info.vl_col = val;
870                                         xres_set = 1;
871                                 } else if (!yres_set) {
872                                         if (val > panel_info.vl_row)
873                                                 val = panel_info.vl_row;
874                                         p->yres = val;
875                                         panel_info.vl_row = val;
876                                         yres_set = 1;
877                                 } else if (!bpp_set) {
878                                         switch (val) {
879                                         case 32:
880                                         case 24:
881                                                 if (is_lvds())
882                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
883                                                 /* fallthru */
884                                         case 16:
885                                         case 8:
886                                                 color_depth = val;
887                                                 break;
888
889                                         case 18:
890                                                 if (is_lvds()) {
891                                                         color_depth = val;
892                                                         break;
893                                                 }
894                                                 /* fallthru */
895                                         default:
896                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
897                                                         end - vm, vm, color_depth);
898                                         }
899                                         bpp_set = 1;
900                                 } else if (!refresh_set) {
901                                         refresh = val;
902                                         refresh_set = 1;
903                                 }
904                         }
905                         vm = end;
906                 }
907                 switch (*vm) {
908                 case '@':
909                         bpp_set = 1;
910                         /* fallthru */
911                 case '-':
912                         yres_set = 1;
913                         /* fallthru */
914                 case 'x':
915                         xres_set = 1;
916                         /* fallthru */
917                 case 'M':
918                 case 'R':
919                         vm++;
920                         break;
921
922                 default:
923                         if (*vm != '\0')
924                                 vm++;
925                 }
926         }
927         if (p->xres == 0 || p->yres == 0) {
928                 printf("Invalid video mode: %s\n", getenv("video_mode"));
929                 lcd_enabled = 0;
930                 printf("Supported video modes are:");
931                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
932                         printf(" %s", p->name);
933                 }
934                 printf("\n");
935                 return;
936         }
937         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
938                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
939                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
940                 lcd_enabled = 0;
941                 return;
942         }
943         panel_info.vl_col = p->xres;
944         panel_info.vl_row = p->yres;
945
946         switch (color_depth) {
947         case 8:
948                 panel_info.vl_bpix = LCD_COLOR8;
949                 break;
950         case 16:
951                 panel_info.vl_bpix = LCD_COLOR16;
952                 break;
953         default:
954                 panel_info.vl_bpix = LCD_COLOR24;
955         }
956
957         p->pixclock = KHZ2PICOS(refresh *
958                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
959                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
960                                 1000);
961         debug("Pixel clock set to %lu.%03lu MHz\n",
962                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
963
964         if (p != &fb_mode) {
965                 int ret;
966
967                 debug("Creating new display-timing node from '%s'\n",
968                         video_mode);
969                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
970                 if (ret)
971                         printf("Failed to create new display-timing node from '%s': %d\n",
972                                 video_mode, ret);
973         }
974
975         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
976         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
977                                         ARRAY_SIZE(stk5_lcd_pads));
978
979         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
980         switch (lcd_bus_width) {
981         case 24:
982                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
983                 break;
984
985         case 18:
986                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
987                 break;
988
989         case 16:
990                 if (!is_lvds()) {
991                         pix_fmt = IPU_PIX_FMT_RGB565;
992                         break;
993                 }
994                 /* fallthru */
995         default:
996                 lcd_enabled = 0;
997                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
998                         lcd_bus_width);
999                 return;
1000         }
1001         if (is_lvds()) {
1002                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1003                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1004                 uint32_t gpr2;
1005
1006                 if (lvds_chan_mask == 0) {
1007                         printf("No LVDS channel active\n");
1008                         lcd_enabled = 0;
1009                         return;
1010                 }
1011
1012                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1013                 if (lcd_bus_width == 24)
1014                         gpr2 |= (1 << 5) | (1 << 7);
1015                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1016                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1017                 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1018                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1019         }
1020         if (karo_load_splashimage(0) == 0) {
1021                 int ret;
1022
1023                 debug("Initializing LCD controller\n");
1024                 ret = ipuv3_fb_init(p, 0, pix_fmt, DI_PCLK_PLL3, di_clk_rate, -1);
1025                 if (ret) {
1026                         printf("Failed to initialize FB driver: %d\n", ret);
1027                         lcd_enabled = 0;
1028                 }
1029         } else {
1030                 debug("Skipping initialization of LCD controller\n");
1031         }
1032 }
1033 #else
1034 #define lcd_enabled 0
1035 #endif /* CONFIG_LCD */
1036
1037 static void stk5_board_init(void)
1038 {
1039         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1040         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1041 }
1042
1043 static void stk5v3_board_init(void)
1044 {
1045         stk5_board_init();
1046 }
1047
1048 static void stk5v5_board_init(void)
1049 {
1050         stk5_board_init();
1051
1052         gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
1053                         "Flexcan Transceiver");
1054         imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO_4_21);
1055 }
1056
1057 static void tx6qdl_set_cpu_clock(void)
1058 {
1059         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1060
1061         if (had_ctrlc() || (wrsr & WRSR_TOUT))
1062                 return;
1063
1064         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1065                 return;
1066
1067         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1068                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1069                 printf("CPU clock set to %lu.%03lu MHz\n",
1070                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1071         } else {
1072                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1073         }
1074 }
1075
1076 static void tx6_init_mac(void)
1077 {
1078         u8 mac[ETH_ALEN];
1079
1080         imx_get_mac_from_fuse(-1, mac);
1081         if (!is_valid_ether_addr(mac)) {
1082                 printf("No valid MAC address programmed\n");
1083                 return;
1084         }
1085
1086         printf("MAC addr from fuse: %pM\n", mac);
1087         eth_setenv_enetaddr("ethaddr", mac);
1088 }
1089
1090 int board_late_init(void)
1091 {
1092         int ret = 0;
1093         const char *baseboard;
1094
1095         tx6qdl_set_cpu_clock();
1096         karo_fdt_move_fdt();
1097
1098         baseboard = getenv("baseboard");
1099         if (!baseboard)
1100                 goto exit;
1101
1102         printf("Baseboard: %s\n", baseboard);
1103
1104         if (strncmp(baseboard, "stk5", 4) == 0) {
1105                 if ((strlen(baseboard) == 4) ||
1106                         strcmp(baseboard, "stk5-v3") == 0) {
1107                         stk5v3_board_init();
1108                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1109                         const char *otg_mode = getenv("otg_mode");
1110
1111                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1112                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1113                                         otg_mode, baseboard);
1114                                 setenv("otg_mode", "none");
1115                         }
1116                         stk5v5_board_init();
1117                 } else {
1118                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1119                                 baseboard + 4);
1120                 }
1121         } else {
1122                 printf("WARNING: Unsupported baseboard: '%s'\n",
1123                         baseboard);
1124                 ret = -EINVAL;
1125         }
1126
1127 exit:
1128         tx6_init_mac();
1129
1130         gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1131         clear_ctrlc();
1132         return ret;
1133 }
1134
1135 #ifdef CONFIG_NO_NAND
1136 #ifdef CONFIG_MMC_BOOT_SIZE
1137 #define TX6_FLASH_SZ    (CONFIG_MMC_BOOT_SIZE / 1024 - 1 + 2)
1138 #else
1139 #define TX6_FLASH_SZ    3
1140 #endif
1141 #else /* CONFIG_NO_NAND */
1142 #define TX6_FLASH_SZ    (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
1143 #endif /* CONFIG_NO_NAND */
1144
1145 #ifdef CONFIG_SYS_SDRAM_BUS_WIDTH
1146 #define TX6_DDR_SZ      (ffs(CONFIG_SYS_SDRAM_BUS_WIDTH / 16) - 1)
1147 #else
1148 #define TX6_DDR_SZ      2
1149 #endif
1150
1151 #if CONFIG_TX6_REV >= 0x3
1152 static char tx6_mem_table[] = {
1153         '4', /* 256MiB SDRAM; 128MiB NAND */
1154         '1', /* 512MiB SDRAM; 128MiB NAND */
1155         '0', /* 1GiB SDRAM; 128MiB NAND */
1156         '?', /* 256MiB SDRAM; 256MiB NAND */
1157         '?', /* 512MiB SDRAM; 256MiB NAND */
1158         '2', /* 1GiB SDRAM; 256MiB NAND */
1159         '?', /* 256MiB SDRAM; 4GiB eMMC */
1160         '5', /* 512MiB SDRAM; 4GiB eMMC */
1161         '3', /* 1GiB SDRAM; 4GiB eMMC */
1162         '?', /* 256MiB SDRAM; 8GiB eMMC */
1163         '?', /* 512MiB SDRAM; 8GiB eMMC */
1164         '?', /* 1GiB SDRAM; 8GiB eMMC */
1165 };
1166
1167 static inline char tx6_mem_suffix(void)
1168 {
1169         size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
1170
1171         debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
1172                 TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
1173
1174         if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
1175                 return '?';
1176
1177         return tx6_mem_table[mem_idx];
1178 };
1179 #else /* CONFIG_TX6_REV >= 0x3 */
1180 static inline char tx6_mem_suffix(void)
1181 {
1182 #ifdef CONFIG_SYS_SDRAM_BUS_WIDTH
1183         if (CONFIG_SYS_SDRAM_BUS_WIDTH == 32)
1184                 return '1';
1185 #endif
1186 #ifdef CONFIG_SYS_NAND_BLOCKS
1187         if (CONFIG_SYS_NAND_BLOCKS == 2048)
1188                 return '2';
1189 #endif
1190         return '0';
1191 }
1192 #endif /* CONFIG_TX6_REV >= 0x3 */
1193
1194 int checkboard(void)
1195 {
1196         u32 cpurev = get_cpu_rev();
1197         int cpu_variant = (cpurev >> 12) & 0xff;
1198
1199         tx6qdl_print_cpuinfo();
1200
1201         printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
1202                 tx6_mod_suffix,
1203                 cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
1204                 is_lvds(), CONFIG_TX6_REV,
1205                 tx6_mem_suffix());
1206
1207         return 0;
1208 }
1209
1210 #ifdef CONFIG_SERIAL_TAG
1211 void get_board_serial(struct tag_serialnr *serialnr)
1212 {
1213         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1214         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1215
1216         serialnr->low = readl(&fuse->cfg0);
1217         serialnr->high = readl(&fuse->cfg1);
1218 }
1219 #endif
1220
1221 #if defined(CONFIG_OF_BOARD_SETUP)
1222 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1223 #include <jffs2/jffs2.h>
1224 #include <mtd_node.h>
1225 static struct node_info nodes[] = {
1226         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1227 };
1228 #else
1229 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1230 #endif
1231
1232 static const char *tx6_touchpanels[] = {
1233         "ti,tsc2007",
1234         "edt,edt-ft5x06",
1235         "eeti,egalax_ts",
1236 };
1237
1238 void ft_board_setup(void *blob, bd_t *bd)
1239 {
1240         const char *baseboard = getenv("baseboard");
1241         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1242         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1243         int ret;
1244
1245         ret = fdt_increase_size(blob, 4096);
1246         if (ret)
1247                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1248
1249         if (stk5_v5)
1250                 karo_fdt_enable_node(blob, "stk5led", 0);
1251
1252         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1253         fdt_fixup_ethernet(blob);
1254
1255         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1256                                 ARRAY_SIZE(tx6_touchpanels));
1257         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1258         karo_fdt_fixup_flexcan(blob, stk5_v5);
1259
1260         karo_fdt_update_fb_mode(blob, video_mode);
1261 }
1262 #endif /* CONFIG_OF_BOARD_SETUP */