karo: tx6: replace open coded interpretation of cpurev by calls to is_cpu_type()
[karo-tx-uboot.git] / board / karo / tx6 / tx6qdl.c
1 /*
2  * Copyright (C) 2012-2015 Lothar WaƟmann <LW@KARO-electronics.de>
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  *
6  */
7 #include <common.h>
8 #include <errno.h>
9 #include <libfdt.h>
10 #include <fdt_support.h>
11 #include <lcd.h>
12 #include <netdev.h>
13 #include <mmc.h>
14 #include <fsl_esdhc.h>
15 #include <video_fb.h>
16 #include <ipu.h>
17 #include <mxcfb.h>
18 #include <i2c.h>
19 #include <linux/fb.h>
20 #include <asm/io.h>
21 #include <asm/gpio.h>
22 #include <asm/arch/mx6-pins.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/hab.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/crm_regs.h>
27 #include <asm/arch/sys_proto.h>
28
29 #include "../common/karo.h"
30 #include "pmic.h"
31
32 #define __data __attribute__((section(".data")))
33
34 #define TX6_FEC_RST_GPIO                IMX_GPIO_NR(7, 6)
35 #define TX6_FEC_PWR_GPIO                IMX_GPIO_NR(3, 20)
36 #define TX6_FEC_INT_GPIO                IMX_GPIO_NR(7, 1)
37 #define TX6_LED_GPIO                    IMX_GPIO_NR(2, 20)
38
39 #define TX6_LCD_PWR_GPIO                IMX_GPIO_NR(2, 31)
40 #define TX6_LCD_RST_GPIO                IMX_GPIO_NR(3, 29)
41 #define TX6_LCD_BACKLIGHT_GPIO          IMX_GPIO_NR(1, 1)
42
43 #define TX6_RESET_OUT_GPIO              IMX_GPIO_NR(7, 12)
44 #define TX6_I2C1_SCL_GPIO               IMX_GPIO_NR(3, 21)
45 #define TX6_I2C1_SDA_GPIO               IMX_GPIO_NR(3, 28)
46
47 #ifdef CONFIG_MX6_TEMPERATURE_MIN
48 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
49 #else
50 #define TEMPERATURE_MIN                 (-40)
51 #endif
52 #ifdef CONFIG_MX6_TEMPERATURE_HOT
53 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
54 #else
55 #define TEMPERATURE_HOT                 80
56 #endif
57
58 DECLARE_GLOBAL_DATA_PTR;
59
60 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
61
62 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
63 #ifdef CONFIG_SECURE_BOOT
64 char __csf_data[0] __attribute__((section(".__csf_data")));
65 #endif
66
67 static const iomux_v3_cfg_t const tx6qdl_pads[] = {
68         /* RESET_OUT */
69         MX6_PAD_GPIO_17__GPIO7_IO12,
70
71         /* UART pads */
72 #if CONFIG_MXC_UART_BASE == UART1_BASE
73         MX6_PAD_SD3_DAT7__UART1_TX_DATA,
74         MX6_PAD_SD3_DAT6__UART1_RX_DATA,
75         MX6_PAD_SD3_DAT1__UART1_RTS_B,
76         MX6_PAD_SD3_DAT0__UART1_CTS_B,
77 #endif
78 #if CONFIG_MXC_UART_BASE == UART2_BASE
79         MX6_PAD_SD4_DAT4__UART2_RX_DATA,
80         MX6_PAD_SD4_DAT7__UART2_TX_DATA,
81         MX6_PAD_SD4_DAT5__UART2_RTS_B,
82         MX6_PAD_SD4_DAT6__UART2_CTS_B,
83 #endif
84 #if CONFIG_MXC_UART_BASE == UART3_BASE
85         MX6_PAD_EIM_D24__UART3_TX_DATA,
86         MX6_PAD_EIM_D25__UART3_RX_DATA,
87         MX6_PAD_SD3_RST__UART3_RTS_B,
88         MX6_PAD_SD3_DAT3__UART3_CTS_B,
89 #endif
90         /* internal I2C */
91         MX6_PAD_EIM_D28__I2C1_SDA,
92         MX6_PAD_EIM_D21__I2C1_SCL,
93
94         /* FEC PHY GPIO functions */
95         MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION, /* PHY POWER */
96         MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION, /* PHY RESET */
97         MX6_PAD_SD3_DAT4__GPIO7_IO01, /* PHY INT */
98 };
99
100 static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = {
101         /* FEC functions */
102         MX6_PAD_ENET_MDC__ENET_MDC,
103         MX6_PAD_ENET_MDIO__ENET_MDIO,
104         MX6_PAD_GPIO_16__ENET_REF_CLK,
105         MX6_PAD_ENET_RX_ER__ENET_RX_ER,
106         MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
107         MX6_PAD_ENET_RXD1__ENET_RX_DATA1,
108         MX6_PAD_ENET_RXD0__ENET_RX_DATA0,
109         MX6_PAD_ENET_TX_EN__ENET_TX_EN,
110         MX6_PAD_ENET_TXD1__ENET_TX_DATA1,
111         MX6_PAD_ENET_TXD0__ENET_TX_DATA0,
112 };
113
114 #define TX6_I2C_GPIO_PAD_CTRL   (PAD_CTL_PUS_22K_UP |   \
115                                 PAD_CTL_SPEED_MED |     \
116                                 PAD_CTL_DSE_34ohm |     \
117                                 PAD_CTL_SRE_FAST)
118
119 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
120         /* internal I2C */
121         MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_GPIO_PAD_CTRL),
122         MX6_PAD_EIM_D21__GPIO3_IO21 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_GPIO_PAD_CTRL),
123 };
124
125 static const iomux_v3_cfg_t const tx6_i2c_pads[] = {
126         /* internal I2C */
127         MX6_PAD_EIM_D28__I2C1_SDA,
128         MX6_PAD_EIM_D21__I2C1_SCL,
129 };
130
131 static const struct gpio const tx6qdl_gpios[] = {
132         /* These two entries are used to forcefully reinitialize the I2C bus */
133         { TX6_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
134         { TX6_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
135
136         { TX6_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", },
137         { TX6_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
138         { TX6_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
139         { TX6_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
140 };
141
142 static int pmic_addr __data;
143
144 #if defined(CONFIG_SOC_MX6Q)
145 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21        0x020e00a4
146 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28        0x020e00c4
147 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21        0x020e03b8
148 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28        0x020e03d8
149 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21      0x020e0898
150 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28      0x020e089c
151 #define I2C1_SEL_INPUT_VAL                      0
152 #endif
153 #if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
154 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21        0x020e0158
155 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28        0x020e0174
156 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21        0x020e0528
157 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28        0x020e0544
158 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21      0x020e0868
159 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28      0x020e086c
160 #define I2C1_SEL_INPUT_VAL                      1
161 #endif
162
163 #define GPIO_DR 0
164 #define GPIO_DIR 4
165 #define GPIO_PSR 8
166
167 static void tx6_i2c_recover(void)
168 {
169         int i;
170         int bad = 0;
171 #define SCL_BIT         (1 << (TX6_I2C1_SCL_GPIO % 32))
172 #define SDA_BIT         (1 << (TX6_I2C1_SDA_GPIO % 32))
173
174         if ((readl(GPIO3_BASE_ADDR + GPIO_PSR) &
175                         (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
176                 return;
177
178         debug("Clearing I2C bus\n");
179         if (!(readl(GPIO3_BASE_ADDR + GPIO_PSR) & SCL_BIT)) {
180                 printf("I2C SCL stuck LOW\n");
181                 bad++;
182
183                 writel(readl(GPIO3_BASE_ADDR + GPIO_DR) | SCL_BIT,
184                         GPIO3_BASE_ADDR + GPIO_DR);
185                 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) | SCL_BIT,
186                         GPIO3_BASE_ADDR + GPIO_DIR);
187         }
188         if (!(readl(GPIO3_BASE_ADDR + GPIO_PSR) & SDA_BIT)) {
189                 printf("I2C SDA stuck LOW\n");
190                 bad++;
191
192                 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) & ~SDA_BIT,
193                         GPIO3_BASE_ADDR + GPIO_DIR);
194                 writel(readl(GPIO3_BASE_ADDR + GPIO_DR) | SCL_BIT,
195                         GPIO3_BASE_ADDR + GPIO_DR);
196                 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) | SCL_BIT,
197                         GPIO3_BASE_ADDR + GPIO_DIR);
198
199                 imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
200                                                 ARRAY_SIZE(tx6_i2c_gpio_pads));
201                 udelay(10);
202
203                 for (i = 0; i < 18; i++) {
204                         u32 reg = readl(GPIO3_BASE_ADDR + GPIO_DR) ^ SCL_BIT;
205
206                         debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
207                         writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
208                         udelay(10);
209                         if (reg & SCL_BIT &&
210                                 readl(GPIO3_BASE_ADDR + GPIO_PSR) & SDA_BIT)
211                                 break;
212                 }
213         }
214         if (bad) {
215                 u32 reg = readl(GPIO3_BASE_ADDR + GPIO_PSR);
216
217                 if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
218                         printf("I2C bus recovery succeeded\n");
219                 } else {
220                         printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
221                                 SCL_BIT | SDA_BIT);
222                 }
223         }
224         debug("Setting up I2C Pads\n");
225         imx_iomux_v3_setup_multiple_pads(tx6_i2c_pads,
226                                         ARRAY_SIZE(tx6_i2c_pads));
227 }
228
229 /* placed in section '.data' to prevent overwriting relocation info
230  * overlayed with bss
231  */
232 static u32 wrsr __data;
233
234 #define WRSR_POR                        (1 << 4)
235 #define WRSR_TOUT                       (1 << 1)
236 #define WRSR_SFTW                       (1 << 0)
237
238 static void print_reset_cause(void)
239 {
240         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
241         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
242         u32 srsr;
243         char *dlm = "";
244
245         printf("Reset cause: ");
246
247         srsr = readl(&src_regs->srsr);
248         wrsr = readw(wdt_base + 4);
249
250         if (wrsr & WRSR_POR) {
251                 printf("%sPOR", dlm);
252                 dlm = " | ";
253         }
254         if (srsr & 0x00004) {
255                 printf("%sCSU", dlm);
256                 dlm = " | ";
257         }
258         if (srsr & 0x00008) {
259                 printf("%sIPP USER", dlm);
260                 dlm = " | ";
261         }
262         if (srsr & 0x00010) {
263                 if (wrsr & WRSR_SFTW) {
264                         printf("%sSOFT", dlm);
265                         dlm = " | ";
266                 }
267                 if (wrsr & WRSR_TOUT) {
268                         printf("%sWDOG", dlm);
269                         dlm = " | ";
270                 }
271         }
272         if (srsr & 0x00020) {
273                 printf("%sJTAG HIGH-Z", dlm);
274                 dlm = " | ";
275         }
276         if (srsr & 0x00040) {
277                 printf("%sJTAG SW", dlm);
278                 dlm = " | ";
279         }
280         if (srsr & 0x10000) {
281                 printf("%sWARM BOOT", dlm);
282                 dlm = " | ";
283         }
284         if (dlm[0] == '\0')
285                 printf("unknown");
286
287         printf("\n");
288 }
289
290 static const char __data *tx6_mod_suffix;
291
292 #ifdef CONFIG_IMX6_THERMAL
293 #include <thermal.h>
294 #include <imx_thermal.h>
295 #include <fuse.h>
296
297 static void print_temperature(void)
298 {
299         struct udevice *thermal_dev;
300         int cpu_tmp, minc, maxc, ret;
301         char const *grade_str;
302         static u32 __data thermal_calib;
303
304         puts("Temperature: ");
305         switch (get_cpu_temp_grade(&minc, &maxc)) {
306         case TEMP_AUTOMOTIVE:
307                 grade_str = "Automotive";
308                 break;
309         case TEMP_INDUSTRIAL:
310                 grade_str = "Industrial";
311                 break;
312         case TEMP_EXTCOMMERCIAL:
313                 grade_str = "Extended Commercial";
314                 break;
315         default:
316                 grade_str = "Commercial";
317         }
318         printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
319         ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
320         if (ret == 0) {
321                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
322
323                 if (ret == 0)
324                         printf(" at %dC", cpu_tmp);
325                 else
326                         puts(" - failed to read sensor data");
327         } else {
328                 puts(" - no sensor device found");
329         }
330
331         if (fuse_read(1, 6, &thermal_calib) == 0) {
332                 printf(" - calibration data 0x%08x\n", thermal_calib);
333         } else {
334                 puts(" - Failed to read thermal calib fuse\n");
335         }
336 }
337 #else
338 static inline void print_temperature(void)
339 {
340 }
341 #endif
342
343 int checkboard(void)
344 {
345         u32 cpurev = get_cpu_rev();
346         char *cpu_str = "?";
347
348         if (is_cpu_type(MXC_CPU_MX6SL)) {
349                 cpu_str = "SL";
350                 tx6_mod_suffix = "?";
351         } else if (is_cpu_type(MXC_CPU_MX6DL)) {
352                 cpu_str = "DL";
353                 tx6_mod_suffix = "U";
354         } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
355                 cpu_str = "SOLO";
356                 tx6_mod_suffix = "S";
357         } else if (is_cpu_type(MXC_CPU_MX6Q)) {
358                 cpu_str = "Q";
359                 tx6_mod_suffix = "Q";
360         }
361
362         printf("CPU:         Freescale i.MX6%s rev%d.%d at %d MHz\n",
363                 cpu_str,
364                 (cpurev & 0x000F0) >> 4,
365                 (cpurev & 0x0000F) >> 0,
366                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
367
368         print_temperature();
369         print_reset_cause();
370 #ifdef CONFIG_MX6_TEMPERATURE_HOT
371         check_cpu_temperature(1);
372 #endif
373         tx6_i2c_recover();
374         return 0;
375 }
376
377 /* serial port not initialized at this point */
378 int board_early_init_f(void)
379 {
380         return 0;
381 }
382
383 #ifndef CONFIG_MX6_TEMPERATURE_HOT
384 static bool tx6_temp_check_enabled = true;
385 #else
386 #define tx6_temp_check_enabled  0
387 #endif
388
389 #ifdef CONFIG_TX6_NAND
390 #define TX6_FLASH_SZ    (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
391 #else
392 #ifdef CONFIG_MMC_BOOT_SIZE
393 #define TX6_FLASH_SZ    (CONFIG_MMC_BOOT_SIZE / 4096 + 2)
394 #else
395 #define TX6_FLASH_SZ    2
396 #endif
397 #endif /* CONFIG_TX6_NAND */
398
399 #define TX6_DDR_SZ      (ffs(CONFIG_SYS_SDRAM_BUS_WIDTH / 16) - 1)
400
401 static char tx6_mem_table[] = {
402         '4', /* 256MiB SDRAM 16bit; 128MiB NAND */
403         '1', /* 512MiB SDRAM 32bit; 128MiB NAND */
404         '0', /* 1GiB SDRAM 64bit; 128MiB NAND */
405         '?', /* 256MiB SDRAM 16bit; 256MiB NAND */
406         '?', /* 512MiB SDRAM 32bit; 256MiB NAND */
407         '2', /* 1GiB SDRAM 64bit; 256MiB NAND */
408         '?', /* 256MiB SDRAM 16bit; 4GiB eMMC */
409         '5', /* 512MiB SDRAM 32bit; 4GiB eMMC */
410         '3', /* 1GiB SDRAM 64bit; 4GiB eMMC */
411         '?', /* 256MiB SDRAM 16bit; 8GiB eMMC */
412         '?', /* 512MiB SDRAM 32bit; 8GiB eMMC */
413         '0', /* 1GiB SDRAM 64bit; 8GiB eMMC */
414 };
415
416 static struct {
417         uchar addr;
418         uchar rev;
419 } tx6_mod_revs[] = {
420         { 0x3c, 1, },
421         { 0x32, 2, },
422         { 0x33, 3, },
423 };
424
425 static inline char tx6_mem_suffix(void)
426 {
427         size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
428
429         debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
430                 TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
431
432         if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
433                 return '?';
434
435         return tx6_mem_table[mem_idx];
436 };
437
438 static int tx6_get_mod_rev(unsigned int pmic_id)
439 {
440         if (pmic_id < ARRAY_SIZE(tx6_mod_revs))
441                 return tx6_mod_revs[pmic_id].rev;
442
443         return 0;
444 }
445
446 static int tx6_pmic_probe(void)
447 {
448         int i;
449
450         debug("%s@%d: \n", __func__, __LINE__);
451
452         for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) {
453                 u8 i2c_addr = tx6_mod_revs[i].addr;
454                 int ret = i2c_probe(i2c_addr);
455
456                 if (ret == 0) {
457                         debug("I2C probe succeeded for addr 0x%02x\n", i2c_addr);
458                         return i;
459                 }
460                 debug("I2C probe returned %d for addr 0x%02x\n", ret, i2c_addr);
461         }
462         return -EINVAL;
463 }
464
465 int board_init(void)
466 {
467         int ret;
468         int pmic_id;
469
470         debug("%s@%d: \n", __func__, __LINE__);
471
472         pmic_id = tx6_pmic_probe();
473         if (pmic_id >= 0 && pmic_id < ARRAY_SIZE(tx6_mod_revs))
474                 pmic_addr = tx6_mod_revs[pmic_id].addr;
475
476         printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
477                 tx6_mod_suffix,
478                 is_cpu_type(MXC_CPU_MX6Q) ? 1 : 8,
479                 is_lvds(), tx6_get_mod_rev(pmic_id),
480                 tx6_mem_suffix());
481
482         get_hab_status();
483
484         ret = gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
485         if (ret < 0) {
486                 printf("Failed to request tx6qdl_gpios: %d\n", ret);
487         }
488         imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
489
490         /* Address of boot parameters */
491         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
492         gd->bd->bi_arch_number = -1;
493
494         if (ctrlc() || (wrsr & WRSR_TOUT)) {
495                 if (wrsr & WRSR_TOUT)
496                         printf("WDOG RESET detected; Skipping PMIC setup\n");
497                 else
498                         printf("<CTRL-C> detected; safeboot enabled\n");
499 #ifndef CONFIG_MX6_TEMPERATURE_HOT
500                 tx6_temp_check_enabled = false;
501 #endif
502                 return 0;
503         }
504
505         ret = tx6_pmic_init(pmic_addr, NULL, 0);
506         if (ret) {
507                 printf("Failed to setup PMIC voltages: %d\n", ret);
508                 hang();
509         }
510         return 0;
511 }
512
513 int dram_init(void)
514 {
515         debug("%s@%d: \n", __func__, __LINE__);
516
517         /* dram_init must store complete ramsize in gd->ram_size */
518         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
519                                 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
520         return 0;
521 }
522
523 void dram_init_banksize(void)
524 {
525         debug("%s@%d: \n", __func__, __LINE__);
526
527         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
528         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
529                         PHYS_SDRAM_1_SIZE);
530 #if CONFIG_NR_DRAM_BANKS > 1
531         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
532         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
533                         PHYS_SDRAM_2_SIZE);
534 #endif
535 }
536
537 #ifdef  CONFIG_FSL_ESDHC
538 #define SD_PAD_CTRL (PAD_CTL_PUS_47K_UP |               \
539         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |         \
540         PAD_CTL_SRE_FAST)
541
542 static const iomux_v3_cfg_t mmc0_pads[] = {
543         MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
544         MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
545         MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
546         MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
547         MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
548         MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
549         /* SD1 CD */
550         MX6_PAD_SD3_CMD__GPIO7_IO02,
551 };
552
553 static const iomux_v3_cfg_t mmc1_pads[] = {
554         MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
555         MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
556         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
557         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
558         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
559         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
560         /* SD2 CD */
561         MX6_PAD_SD3_CLK__GPIO7_IO03,
562 };
563
564 #ifdef CONFIG_TX6_EMMC
565 static const iomux_v3_cfg_t mmc3_pads[] = {
566         MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
567         MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
568         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
569         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
570         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
571         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
572         /* eMMC RESET */
573         MX6_PAD_NANDF_ALE__SD4_RESET | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
574                                                 PAD_CTL_DSE_40ohm),
575 };
576 #endif
577
578 static struct tx6_esdhc_cfg {
579         const iomux_v3_cfg_t *pads;
580         int num_pads;
581         enum mxc_clock clkid;
582         struct fsl_esdhc_cfg cfg;
583         int cd_gpio;
584 } tx6qdl_esdhc_cfg[] = {
585 #ifdef CONFIG_TX6_EMMC
586         {
587                 .pads = mmc3_pads,
588                 .num_pads = ARRAY_SIZE(mmc3_pads),
589                 .clkid = MXC_ESDHC4_CLK,
590                 .cfg = {
591                         .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
592                         .max_bus_width = 4,
593                 },
594                 .cd_gpio = -EINVAL,
595         },
596 #endif
597         {
598                 .pads = mmc0_pads,
599                 .num_pads = ARRAY_SIZE(mmc0_pads),
600                 .clkid = MXC_ESDHC_CLK,
601                 .cfg = {
602                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
603                         .max_bus_width = 4,
604                 },
605                 .cd_gpio = IMX_GPIO_NR(7, 2),
606         },
607         {
608                 .pads = mmc1_pads,
609                 .num_pads = ARRAY_SIZE(mmc1_pads),
610                 .clkid = MXC_ESDHC2_CLK,
611                 .cfg = {
612                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
613                         .max_bus_width = 4,
614                 },
615                 .cd_gpio = IMX_GPIO_NR(7, 3),
616         },
617 };
618
619 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
620 {
621         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
622 }
623
624 int board_mmc_getcd(struct mmc *mmc)
625 {
626         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
627
628         if (cfg->cd_gpio < 0)
629                 return 1;
630
631         debug("SD card %d is %spresent (GPIO %d)\n",
632                 cfg - tx6qdl_esdhc_cfg,
633                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
634                 cfg->cd_gpio);
635         return !gpio_get_value(cfg->cd_gpio);
636 }
637
638 int board_mmc_init(bd_t *bis)
639 {
640         int i;
641
642         debug("%s@%d: \n", __func__, __LINE__);
643
644         for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
645                 struct mmc *mmc;
646                 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
647                 int ret;
648
649                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
650                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
651
652                 if (cfg->cd_gpio >= 0) {
653                         ret = gpio_request_one(cfg->cd_gpio,
654                                         GPIOFLAG_INPUT, "MMC CD");
655                         if (ret) {
656                                 printf("Error %d requesting GPIO%d_%d\n",
657                                         ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
658                                 continue;
659                         }
660                 }
661
662                 debug("%s: Initializing MMC slot %d\n", __func__, i);
663                 fsl_esdhc_initialize(bis, &cfg->cfg);
664
665                 mmc = find_mmc_device(i);
666                 if (mmc == NULL)
667                         continue;
668                 if (board_mmc_getcd(mmc))
669                         mmc_init(mmc);
670         }
671         return 0;
672 }
673 #endif /* CONFIG_CMD_MMC */
674
675 #ifdef CONFIG_FEC_MXC
676
677 #ifndef ETH_ALEN
678 #define ETH_ALEN 6
679 #endif
680
681 int board_eth_init(bd_t *bis)
682 {
683         int ret;
684
685         debug("%s@%d: \n", __func__, __LINE__);
686
687         /* delay at least 21ms for the PHY internal POR signal to deassert */
688         udelay(22000);
689
690         imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads,
691                                         ARRAY_SIZE(tx6qdl_fec_pads));
692
693         /* Deassert RESET to the external phy */
694         gpio_set_value(TX6_FEC_RST_GPIO, 1);
695
696         ret = cpu_eth_init(bis);
697         if (ret)
698                 printf("cpu_eth_init() failed: %d\n", ret);
699
700         return ret;
701 }
702
703 static void tx6_init_mac(void)
704 {
705         u8 mac[ETH_ALEN];
706
707         imx_get_mac_from_fuse(0, mac);
708         if (!is_valid_ethaddr(mac)) {
709                 printf("No valid MAC address programmed\n");
710                 return;
711         }
712
713         printf("MAC addr from fuse: %pM\n", mac);
714         eth_setenv_enetaddr("ethaddr", mac);
715 }
716 #else
717 static inline void tx6_init_mac(void)
718 {
719 }
720 #endif /* CONFIG_FEC_MXC */
721
722 enum {
723         LED_STATE_INIT = -1,
724         LED_STATE_OFF,
725         LED_STATE_ON,
726 };
727
728 static inline int calc_blink_rate(void)
729 {
730         if (!tx6_temp_check_enabled)
731                 return CONFIG_SYS_HZ;
732
733         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
734                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
735                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
736 }
737
738 void show_activity(int arg)
739 {
740         static int led_state = LED_STATE_INIT;
741         static int blink_rate;
742         static ulong last;
743
744         if (led_state == LED_STATE_INIT) {
745                 last = get_timer(0);
746                 gpio_set_value(TX6_LED_GPIO, 1);
747                 led_state = LED_STATE_ON;
748                 blink_rate = calc_blink_rate();
749         } else {
750                 if (get_timer(last) > blink_rate) {
751                         blink_rate = calc_blink_rate();
752                         last = get_timer_masked();
753                         if (led_state == LED_STATE_ON) {
754                                 gpio_set_value(TX6_LED_GPIO, 0);
755                         } else {
756                                 gpio_set_value(TX6_LED_GPIO, 1);
757                         }
758                         led_state = 1 - led_state;
759                 }
760         }
761 }
762
763 static const iomux_v3_cfg_t stk5_pads[] = {
764         /* SW controlled LED on STK5 baseboard */
765         MX6_PAD_EIM_A18__GPIO2_IO20,
766
767         /* I2C bus on DIMM pins 40/41 */
768         MX6_PAD_GPIO_6__I2C3_SDA,
769         MX6_PAD_GPIO_3__I2C3_SCL,
770
771         /* TSC200x PEN IRQ */
772         MX6_PAD_EIM_D26__GPIO3_IO26,
773
774         /* EDT-FT5x06 Polytouch panel */
775         MX6_PAD_NANDF_CS2__GPIO6_IO15, /* IRQ */
776         MX6_PAD_EIM_A16__GPIO2_IO22, /* RESET */
777         MX6_PAD_EIM_A17__GPIO2_IO21, /* WAKE */
778
779         /* USBH1 */
780         MX6_PAD_EIM_D31__GPIO3_IO31, /* VBUSEN */
781         MX6_PAD_EIM_D30__GPIO3_IO30, /* OC */
782         /* USBOTG */
783         MX6_PAD_EIM_D23__GPIO3_IO23, /* USBOTG ID */
784         MX6_PAD_GPIO_7__GPIO1_IO07, /* VBUSEN */
785         MX6_PAD_GPIO_8__GPIO1_IO08, /* OC */
786 };
787
788 static const struct gpio stk5_gpios[] = {
789         { TX6_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
790
791         { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
792         { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
793         { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
794         { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
795         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
796 };
797
798 #ifdef CONFIG_LCD
799 vidinfo_t panel_info = {
800         /* set to max. size supported by SoC */
801         .vl_col = 1920,
802         .vl_row = 1080,
803
804         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
805 };
806
807 static struct fb_videomode tx6_fb_modes[] = {
808 #ifndef CONFIG_SYS_LVDS_IF
809         {
810                 /* Standard VGA timing */
811                 .name           = "VGA",
812                 .refresh        = 60,
813                 .xres           = 640,
814                 .yres           = 480,
815                 .pixclock       = KHZ2PICOS(25175),
816                 .left_margin    = 48,
817                 .hsync_len      = 96,
818                 .right_margin   = 16,
819                 .upper_margin   = 31,
820                 .vsync_len      = 2,
821                 .lower_margin   = 12,
822                 .sync           = FB_SYNC_CLK_LAT_FALL,
823         },
824         {
825                 /* Emerging ETV570 640 x 480 display. Syncs low active,
826                  * DE high active, 115.2 mm x 86.4 mm display area
827                  * VGA compatible timing
828                  */
829                 .name           = "ETV570",
830                 .refresh        = 60,
831                 .xres           = 640,
832                 .yres           = 480,
833                 .pixclock       = KHZ2PICOS(25175),
834                 .left_margin    = 114,
835                 .hsync_len      = 30,
836                 .right_margin   = 16,
837                 .upper_margin   = 32,
838                 .vsync_len      = 3,
839                 .lower_margin   = 10,
840                 .sync           = FB_SYNC_CLK_LAT_FALL,
841         },
842         {
843                 /* Emerging ET0350G0DH6 320 x 240 display.
844                  * 70.08 mm x 52.56 mm display area.
845                  */
846                 .name           = "ET0350",
847                 .refresh        = 60,
848                 .xres           = 320,
849                 .yres           = 240,
850                 .pixclock       = KHZ2PICOS(6500),
851                 .left_margin    = 68 - 34,
852                 .hsync_len      = 34,
853                 .right_margin   = 20,
854                 .upper_margin   = 18 - 3,
855                 .vsync_len      = 3,
856                 .lower_margin   = 4,
857                 .sync           = FB_SYNC_CLK_LAT_FALL,
858         },
859         {
860                 /* Emerging ET0430G0DH6 480 x 272 display.
861                  * 95.04 mm x 53.856 mm display area.
862                  */
863                 .name           = "ET0430",
864                 .refresh        = 60,
865                 .xres           = 480,
866                 .yres           = 272,
867                 .pixclock       = KHZ2PICOS(9000),
868                 .left_margin    = 2,
869                 .hsync_len      = 41,
870                 .right_margin   = 2,
871                 .upper_margin   = 2,
872                 .vsync_len      = 10,
873                 .lower_margin   = 2,
874         },
875         {
876                 /* Emerging ET0500G0DH6 800 x 480 display.
877                  * 109.6 mm x 66.4 mm display area.
878                  */
879                 .name           = "ET0500",
880                 .refresh        = 60,
881                 .xres           = 800,
882                 .yres           = 480,
883                 .pixclock       = KHZ2PICOS(33260),
884                 .left_margin    = 216 - 128,
885                 .hsync_len      = 128,
886                 .right_margin   = 1056 - 800 - 216,
887                 .upper_margin   = 35 - 2,
888                 .vsync_len      = 2,
889                 .lower_margin   = 525 - 480 - 35,
890                 .sync           = FB_SYNC_CLK_LAT_FALL,
891         },
892         {
893                 /* Emerging ETQ570G0DH6 320 x 240 display.
894                  * 115.2 mm x 86.4 mm display area.
895                  */
896                 .name           = "ETQ570",
897                 .refresh        = 60,
898                 .xres           = 320,
899                 .yres           = 240,
900                 .pixclock       = KHZ2PICOS(6400),
901                 .left_margin    = 38,
902                 .hsync_len      = 30,
903                 .right_margin   = 30,
904                 .upper_margin   = 16, /* 15 according to datasheet */
905                 .vsync_len      = 3, /* TVP -> 1>x>5 */
906                 .lower_margin   = 4, /* 4.5 according to datasheet */
907                 .sync           = FB_SYNC_CLK_LAT_FALL,
908         },
909         {
910                 /* Emerging ET0700G0DH6 800 x 480 display.
911                  * 152.4 mm x 91.44 mm display area.
912                  */
913                 .name           = "ET0700",
914                 .refresh        = 60,
915                 .xres           = 800,
916                 .yres           = 480,
917                 .pixclock       = KHZ2PICOS(33260),
918                 .left_margin    = 216 - 128,
919                 .hsync_len      = 128,
920                 .right_margin   = 1056 - 800 - 216,
921                 .upper_margin   = 35 - 2,
922                 .vsync_len      = 2,
923                 .lower_margin   = 525 - 480 - 35,
924                 .sync           = FB_SYNC_CLK_LAT_FALL,
925         },
926         {
927                 /* Emerging ET070001DM6 800 x 480 display.
928                  * 152.4 mm x 91.44 mm display area.
929                  */
930                 .name           = "ET070001DM6",
931                 .refresh        = 60,
932                 .xres           = 800,
933                 .yres           = 480,
934                 .pixclock       = KHZ2PICOS(33260),
935                 .left_margin    = 216 - 128,
936                 .hsync_len      = 128,
937                 .right_margin   = 1056 - 800 - 216,
938                 .upper_margin   = 35 - 2,
939                 .vsync_len      = 2,
940                 .lower_margin   = 525 - 480 - 35,
941                 .sync           = 0,
942         },
943 #else
944         {
945                 /* HannStar HSD100PXN1
946                  * 202.7m mm x 152.06 mm display area.
947                  */
948                 .name           = "HSD100PXN1",
949                 .refresh        = 60,
950                 .xres           = 1024,
951                 .yres           = 768,
952                 .pixclock       = KHZ2PICOS(65000),
953                 .left_margin    = 0,
954                 .hsync_len      = 0,
955                 .right_margin   = 320,
956                 .upper_margin   = 0,
957                 .vsync_len      = 0,
958                 .lower_margin   = 38,
959                 .sync           = FB_SYNC_CLK_LAT_FALL,
960         },
961 #endif
962         {
963                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
964                 .refresh        = 60,
965                 .left_margin    = 48,
966                 .hsync_len      = 96,
967                 .right_margin   = 16,
968                 .upper_margin   = 31,
969                 .vsync_len      = 2,
970                 .lower_margin   = 12,
971                 .sync           = FB_SYNC_CLK_LAT_FALL,
972         },
973 };
974
975 static int lcd_enabled = 1;
976 static int lcd_bl_polarity;
977
978 static int lcd_backlight_polarity(void)
979 {
980         return lcd_bl_polarity;
981 }
982
983 void lcd_enable(void)
984 {
985         /* HACK ALERT:
986          * global variable from common/lcd.c
987          * Set to 0 here to prevent messages from going to LCD
988          * rather than serial console
989          */
990         lcd_is_enabled = 0;
991
992         if (lcd_enabled) {
993                 karo_load_splashimage(1);
994
995                 debug("Switching LCD on\n");
996                 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
997                 udelay(100);
998                 gpio_set_value(TX6_LCD_RST_GPIO, 1);
999                 udelay(300000);
1000                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
1001                         lcd_backlight_polarity());
1002         }
1003 }
1004
1005 void lcd_disable(void)
1006 {
1007         if (lcd_enabled) {
1008                 printf("Disabling LCD\n");
1009                 ipuv3_fb_shutdown();
1010         }
1011 }
1012
1013 void lcd_panel_disable(void)
1014 {
1015         if (lcd_enabled) {
1016                 debug("Switching LCD off\n");
1017                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
1018                         !lcd_backlight_polarity());
1019                 gpio_set_value(TX6_LCD_RST_GPIO, 0);
1020                 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
1021         }
1022 }
1023
1024 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
1025         /* LCD RESET */
1026         MX6_PAD_EIM_D29__GPIO3_IO29,
1027         /* LCD POWER_ENABLE */
1028         MX6_PAD_EIM_EB3__GPIO2_IO31,
1029         /* LCD Backlight (PWM) */
1030         MX6_PAD_GPIO_1__GPIO1_IO01,
1031
1032 #ifndef CONFIG_SYS_LVDS_IF
1033         /* Display */
1034         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
1035         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
1036         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
1037         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
1038         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
1039         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
1040         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
1041         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
1042         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
1043         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
1044         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
1045         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
1046         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
1047         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
1048         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
1049         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
1050         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
1051         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
1052         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
1053         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
1054         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
1055         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
1056         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
1057         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
1058         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSYNC */
1059         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSYNC */
1060         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
1061         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
1062 #endif
1063 };
1064
1065 static const struct gpio stk5_lcd_gpios[] = {
1066         { TX6_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1067         { TX6_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1068         { TX6_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1069 };
1070
1071 void lcd_ctrl_init(void *lcdbase)
1072 {
1073         int color_depth = 24;
1074         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1075         const char *vm;
1076         unsigned long val;
1077         int refresh = 60;
1078         struct fb_videomode *p = &tx6_fb_modes[0];
1079         struct fb_videomode fb_mode;
1080         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1081         int pix_fmt;
1082         int lcd_bus_width;
1083         unsigned long di_clk_rate = 65000000;
1084
1085         if (!lcd_enabled) {
1086                 debug("LCD disabled\n");
1087                 goto disable;
1088                 return;
1089         }
1090
1091         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1092                 debug("Disabling LCD\n");
1093                 lcd_enabled = 0;
1094                 setenv("splashimage", NULL);
1095                 goto disable;
1096                 return;
1097         }
1098
1099         karo_fdt_move_fdt();
1100         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1101
1102         if (video_mode == NULL) {
1103                 debug("Disabling LCD\n");
1104                 lcd_enabled = 0;
1105                 goto disable;
1106                 return;
1107         }
1108         vm = video_mode;
1109         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1110                 p = &fb_mode;
1111                 debug("Using video mode from FDT\n");
1112                 vm += strlen(vm);
1113                 if (fb_mode.xres > panel_info.vl_col ||
1114                         fb_mode.yres > panel_info.vl_row) {
1115                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1116                                 fb_mode.xres, fb_mode.yres,
1117                                 panel_info.vl_col, panel_info.vl_row);
1118                         lcd_enabled = 0;
1119                         goto disable;
1120                         return;
1121                 }
1122         }
1123         if (p->name != NULL)
1124                 debug("Trying compiled-in video modes\n");
1125         while (p->name != NULL) {
1126                 if (strcmp(p->name, vm) == 0) {
1127                         debug("Using video mode: '%s'\n", p->name);
1128                         vm += strlen(vm);
1129                         break;
1130                 }
1131                 p++;
1132         }
1133         if (*vm != '\0')
1134                 debug("Trying to decode video_mode: '%s'\n", vm);
1135         while (*vm != '\0') {
1136                 if (*vm >= '0' && *vm <= '9') {
1137                         char *end;
1138
1139                         val = simple_strtoul(vm, &end, 0);
1140                         if (end > vm) {
1141                                 if (!xres_set) {
1142                                         if (val > panel_info.vl_col)
1143                                                 val = panel_info.vl_col;
1144                                         p->xres = val;
1145                                         panel_info.vl_col = val;
1146                                         xres_set = 1;
1147                                 } else if (!yres_set) {
1148                                         if (val > panel_info.vl_row)
1149                                                 val = panel_info.vl_row;
1150                                         p->yres = val;
1151                                         panel_info.vl_row = val;
1152                                         yres_set = 1;
1153                                 } else if (!bpp_set) {
1154                                         switch (val) {
1155                                         case 32:
1156                                         case 24:
1157                                                 if (is_lvds())
1158                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
1159                                                 /* fallthru */
1160                                         case 16:
1161                                         case 8:
1162                                                 color_depth = val;
1163                                                 break;
1164
1165                                         case 18:
1166                                                 if (is_lvds()) {
1167                                                         color_depth = val;
1168                                                         break;
1169                                                 }
1170                                                 /* fallthru */
1171                                         default:
1172                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1173                                                         end - vm, vm, color_depth);
1174                                         }
1175                                         bpp_set = 1;
1176                                 } else if (!refresh_set) {
1177                                         refresh = val;
1178                                         refresh_set = 1;
1179                                 }
1180                         }
1181                         vm = end;
1182                 }
1183                 switch (*vm) {
1184                 case '@':
1185                         bpp_set = 1;
1186                         /* fallthru */
1187                 case '-':
1188                         yres_set = 1;
1189                         /* fallthru */
1190                 case 'x':
1191                         xres_set = 1;
1192                         /* fallthru */
1193                 case 'M':
1194                 case 'R':
1195                         vm++;
1196                         break;
1197
1198                 default:
1199                         if (*vm != '\0')
1200                                 vm++;
1201                 }
1202         }
1203         if (p->xres == 0 || p->yres == 0) {
1204                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1205                 lcd_enabled = 0;
1206                 printf("Supported video modes are:");
1207                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1208                         printf(" %s", p->name);
1209                 }
1210                 printf("\n");
1211                 goto disable;
1212                 return;
1213         }
1214         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1215                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1216                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1217                 lcd_enabled = 0;
1218                 goto disable;
1219                 return;
1220         }
1221         panel_info.vl_col = p->xres;
1222         panel_info.vl_row = p->yres;
1223
1224         switch (color_depth) {
1225         case 8:
1226                 panel_info.vl_bpix = LCD_COLOR8;
1227                 break;
1228         case 16:
1229                 panel_info.vl_bpix = LCD_COLOR16;
1230                 break;
1231         default:
1232                 panel_info.vl_bpix = LCD_COLOR32;
1233         }
1234
1235         p->pixclock = KHZ2PICOS(refresh *
1236                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1237                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1238                                 1000);
1239         debug("Pixel clock set to %lu.%03lu MHz\n",
1240                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1241
1242         if (p != &fb_mode) {
1243                 int ret;
1244
1245                 debug("Creating new display-timing node from '%s'\n",
1246                         video_mode);
1247                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1248                 if (ret)
1249                         printf("Failed to create new display-timing node from '%s': %d\n",
1250                                 video_mode, ret);
1251         }
1252
1253         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1254         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1255                                         ARRAY_SIZE(stk5_lcd_pads));
1256
1257         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1258         switch (lcd_bus_width) {
1259         case 24:
1260                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1261                 break;
1262
1263         case 18:
1264                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1265                 break;
1266
1267         case 16:
1268                 if (!is_lvds()) {
1269                         pix_fmt = IPU_PIX_FMT_RGB565;
1270                         break;
1271                 }
1272                 /* fallthru */
1273         default:
1274                 lcd_enabled = 0;
1275                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1276                         lcd_bus_width);
1277                 goto disable;
1278                 return;
1279         }
1280         if (is_lvds()) {
1281                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1282                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1283                 uint32_t gpr2;
1284                 uint32_t gpr3;
1285
1286                 if (lvds_chan_mask == 0) {
1287                         printf("No LVDS channel active\n");
1288                         lcd_enabled = 0;
1289                         goto disable;
1290                         return;
1291                 }
1292
1293                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1294                 if (lcd_bus_width == 24)
1295                         gpr2 |= (1 << 5) | (1 << 7);
1296                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1297                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1298                 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1299                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1300
1301                 gpr3 = readl(IOMUXC_BASE_ADDR + 0xc);
1302                 gpr3 &= ~((3 << 8) | (3 << 6));
1303                 writel(gpr3, IOMUXC_BASE_ADDR + 0xc);
1304         }
1305         if (karo_load_splashimage(0) == 0) {
1306                 int ret;
1307
1308                 debug("Initializing LCD controller\n");
1309                 ret = ipuv3_fb_init(p, 0, pix_fmt,
1310                                 is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
1311                                 di_clk_rate, -1);
1312                 if (ret) {
1313                         printf("Failed to initialize FB driver: %d\n", ret);
1314                         lcd_enabled = 0;
1315                 }
1316         } else {
1317                 debug("Skipping initialization of LCD controller\n");
1318         }
1319         return;
1320
1321 disable:
1322         lcd_enabled = 0;
1323         panel_info.vl_col = 0;
1324         panel_info.vl_row = 0;
1325
1326 }
1327 #else
1328 #define lcd_enabled 0
1329 #endif /* CONFIG_LCD */
1330
1331 static void stk5_board_init(void)
1332 {
1333         int ret;
1334
1335         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1336         if (ret < 0) {
1337                 printf("Failed to request stk5_gpios: %d\n", ret);
1338                 return;
1339         }
1340         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1341 }
1342
1343 static void stk5v3_board_init(void)
1344 {
1345         stk5_board_init();
1346 }
1347
1348 static void stk5v5_board_init(void)
1349 {
1350         int ret;
1351
1352         stk5_board_init();
1353
1354         ret = gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH,
1355                         "Flexcan Transceiver");
1356         if (ret) {
1357                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1358                 return;
1359         }
1360
1361         imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21);
1362 }
1363
1364 static void tx6qdl_set_cpu_clock(void)
1365 {
1366         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1367
1368         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1369                 return;
1370
1371         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1372                 printf("%s detected; skipping cpu clock change\n",
1373                         (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1374                 return;
1375         }
1376         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1377                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1378                 printf("CPU clock set to %lu.%03lu MHz\n",
1379                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1380         } else {
1381                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1382         }
1383 }
1384
1385 int board_late_init(void)
1386 {
1387         const char *baseboard;
1388
1389         debug("%s@%d: \n", __func__, __LINE__);
1390
1391         env_cleanup();
1392
1393         if (tx6_temp_check_enabled)
1394                 check_cpu_temperature(1);
1395
1396         tx6qdl_set_cpu_clock();
1397
1398         if (had_ctrlc())
1399                 setenv_ulong("safeboot", 1);
1400         else if (wrsr & WRSR_TOUT)
1401                 setenv_ulong("wdreset", 1);
1402         else
1403                 karo_fdt_move_fdt();
1404
1405         baseboard = getenv("baseboard");
1406         if (!baseboard)
1407                 goto exit;
1408
1409         printf("Baseboard: %s\n", baseboard);
1410
1411         if (strncmp(baseboard, "stk5", 4) == 0) {
1412                 if ((strlen(baseboard) == 4) ||
1413                         strcmp(baseboard, "stk5-v3") == 0) {
1414                         stk5v3_board_init();
1415                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1416                         const char *otg_mode = getenv("otg_mode");
1417
1418                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1419                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1420                                         otg_mode, baseboard);
1421                                 setenv("otg_mode", "none");
1422                         }
1423                         stk5v5_board_init();
1424                 } else {
1425                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1426                                 baseboard + 4);
1427                 }
1428         } else {
1429                 printf("WARNING: Unsupported baseboard: '%s'\n",
1430                         baseboard);
1431                 if (!had_ctrlc())
1432                         return -EINVAL;
1433         }
1434
1435 exit:
1436         tx6_init_mac();
1437
1438         gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1439         clear_ctrlc();
1440         return 0;
1441 }
1442
1443 #ifdef CONFIG_SERIAL_TAG
1444 void get_board_serial(struct tag_serialnr *serialnr)
1445 {
1446         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1447         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1448
1449         serialnr->low = readl(&fuse->cfg0);
1450         serialnr->high = readl(&fuse->cfg1);
1451 }
1452 #endif
1453
1454 #if defined(CONFIG_OF_BOARD_SETUP)
1455 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1456 #include <jffs2/jffs2.h>
1457 #include <mtd_node.h>
1458 static struct node_info nodes[] = {
1459         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1460 };
1461 #else
1462 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1463 #endif
1464
1465 static const char *tx6_touchpanels[] = {
1466         "ti,tsc2007",
1467         "edt,edt-ft5x06",
1468         "eeti,egalax_ts",
1469 };
1470
1471 int ft_board_setup(void *blob, bd_t *bd)
1472 {
1473         const char *baseboard = getenv("baseboard");
1474         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1475         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1476         int ret;
1477
1478         ret = fdt_increase_size(blob, 4096);
1479         if (ret) {
1480                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1481                 return ret;
1482         }
1483         if (stk5_v5)
1484                 karo_fdt_enable_node(blob, "stk5led", 0);
1485
1486         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1487
1488         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1489                                 ARRAY_SIZE(tx6_touchpanels));
1490         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1491         karo_fdt_fixup_flexcan(blob, stk5_v5);
1492
1493         karo_fdt_update_fb_mode(blob, video_mode);
1494
1495         return 0;
1496 }
1497 #endif /* CONFIG_OF_BOARD_SETUP */