karo: tx6: configure all relevant PMIC registers
[karo-tx-uboot.git] / board / karo / tx6 / tx6qdl.c
1 /*
2  * Copyright (C) 2012-2015 Lothar WaƟmann <LW@KARO-electronics.de>
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  *
6  */
7 #include <common.h>
8 #include <errno.h>
9 #include <libfdt.h>
10 #include <fdt_support.h>
11 #include <lcd.h>
12 #include <netdev.h>
13 #include <mmc.h>
14 #include <fsl_esdhc.h>
15 #include <video_fb.h>
16 #include <ipu.h>
17 #include <mxcfb.h>
18 #include <i2c.h>
19 #include <linux/fb.h>
20 #include <asm/io.h>
21 #include <asm/gpio.h>
22 #include <asm/arch/mx6-pins.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/hab.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/crm_regs.h>
27 #include <asm/arch/sys_proto.h>
28
29 #include "../common/karo.h"
30 #include "pmic.h"
31
32 #define __data __attribute__((section(".data")))
33
34 #define TX6_FEC_RST_GPIO                IMX_GPIO_NR(7, 6)
35 #define TX6_FEC_PWR_GPIO                IMX_GPIO_NR(3, 20)
36 #define TX6_FEC_INT_GPIO                IMX_GPIO_NR(7, 1)
37 #define TX6_LED_GPIO                    IMX_GPIO_NR(2, 20)
38
39 #define TX6_LCD_PWR_GPIO                IMX_GPIO_NR(2, 31)
40 #define TX6_LCD_RST_GPIO                IMX_GPIO_NR(3, 29)
41 #define TX6_LCD_BACKLIGHT_GPIO          IMX_GPIO_NR(1, 1)
42
43 #define TX6_RESET_OUT_GPIO              IMX_GPIO_NR(7, 12)
44 #define TX6_I2C1_SCL_GPIO               IMX_GPIO_NR(3, 21)
45 #define TX6_I2C1_SDA_GPIO               IMX_GPIO_NR(3, 28)
46
47 #ifdef CONFIG_MX6_TEMPERATURE_MIN
48 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
49 #else
50 #define TEMPERATURE_MIN                 (-40)
51 #endif
52 #ifdef CONFIG_MX6_TEMPERATURE_HOT
53 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
54 #else
55 #define TEMPERATURE_HOT                 80
56 #endif
57
58 DECLARE_GLOBAL_DATA_PTR;
59
60 #define MUX_CFG_SION            IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
61
62 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
63 #ifdef CONFIG_SECURE_BOOT
64 char __csf_data[0] __attribute__((section(".__csf_data")));
65 #endif
66
67 #define TX6_DEFAULT_PAD_CTRL    MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |      \
68                                              PAD_CTL_SPEED_MED |        \
69                                              PAD_CTL_DSE_40ohm |        \
70                                              PAD_CTL_SRE_FAST)
71 #define TX6_FEC_PAD_CTRL        MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |      \
72                                              PAD_CTL_SPEED_MED |        \
73                                              PAD_CTL_DSE_40ohm |        \
74                                              PAD_CTL_SRE_SLOW)
75 #define TX6_GPIO_PAD_CTRL       MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |       \
76                                              PAD_CTL_SPEED_MED |        \
77                                              PAD_CTL_DSE_34ohm |        \
78                                              PAD_CTL_SRE_FAST)
79 #define TX6_I2C_PAD_CTRL        MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |       \
80                                              PAD_CTL_HYS |              \
81                                              PAD_CTL_SPEED_LOW |        \
82                                              PAD_CTL_DSE_40ohm |        \
83                                              PAD_CTL_SRE_SLOW)
84
85 static const iomux_v3_cfg_t const tx6qdl_pads[] = {
86         /* RESET_OUT */
87         MX6_PAD_GPIO_17__GPIO7_IO12 | TX6_DEFAULT_PAD_CTRL,
88
89         /* UART pads */
90 #if CONFIG_MXC_UART_BASE == UART1_BASE
91         MX6_PAD_SD3_DAT7__UART1_TX_DATA | TX6_DEFAULT_PAD_CTRL,
92         MX6_PAD_SD3_DAT6__UART1_RX_DATA | TX6_DEFAULT_PAD_CTRL,
93         MX6_PAD_SD3_DAT1__UART1_RTS_B | TX6_DEFAULT_PAD_CTRL,
94         MX6_PAD_SD3_DAT0__UART1_CTS_B | TX6_DEFAULT_PAD_CTRL,
95 #endif
96 #if CONFIG_MXC_UART_BASE == UART2_BASE
97         MX6_PAD_SD4_DAT4__UART2_RX_DATA | TX6_DEFAULT_PAD_CTRL,
98         MX6_PAD_SD4_DAT7__UART2_TX_DATA | TX6_DEFAULT_PAD_CTRL,
99         MX6_PAD_SD4_DAT5__UART2_RTS_B | TX6_DEFAULT_PAD_CTRL,
100         MX6_PAD_SD4_DAT6__UART2_CTS_B | TX6_DEFAULT_PAD_CTRL,
101 #endif
102 #if CONFIG_MXC_UART_BASE == UART3_BASE
103         MX6_PAD_EIM_D24__UART3_TX_DATA | TX6_DEFAULT_PAD_CTRL,
104         MX6_PAD_EIM_D25__UART3_RX_DATA | TX6_DEFAULT_PAD_CTRL,
105         MX6_PAD_SD3_RST__UART3_RTS_B | TX6_DEFAULT_PAD_CTRL,
106         MX6_PAD_SD3_DAT3__UART3_CTS_B | TX6_DEFAULT_PAD_CTRL,
107 #endif
108         /* internal I2C */
109         MX6_PAD_EIM_D28__I2C1_SDA | TX6_DEFAULT_PAD_CTRL,
110         MX6_PAD_EIM_D21__I2C1_SCL | TX6_DEFAULT_PAD_CTRL,
111
112         /* FEC PHY GPIO functions */
113         MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION |
114         TX6_DEFAULT_PAD_CTRL, /* PHY POWER */
115         MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION |
116         TX6_DEFAULT_PAD_CTRL, /* PHY RESET */
117         MX6_PAD_SD3_DAT4__GPIO7_IO01 | TX6_DEFAULT_PAD_CTRL, /* PHY INT */
118 };
119
120 static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = {
121         /* FEC functions */
122         MX6_PAD_ENET_MDC__ENET_MDC | TX6_FEC_PAD_CTRL,
123         MX6_PAD_ENET_MDIO__ENET_MDIO | TX6_FEC_PAD_CTRL,
124         MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
125                                                      PAD_CTL_SPEED_LOW |
126                                                      PAD_CTL_DSE_80ohm |
127                                                      PAD_CTL_SRE_SLOW),
128         MX6_PAD_ENET_RX_ER__ENET_RX_ER | TX6_FEC_PAD_CTRL,
129         MX6_PAD_ENET_CRS_DV__ENET_RX_EN | TX6_FEC_PAD_CTRL,
130         MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | TX6_FEC_PAD_CTRL,
131         MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | TX6_FEC_PAD_CTRL,
132         MX6_PAD_ENET_TX_EN__ENET_TX_EN | TX6_FEC_PAD_CTRL,
133         MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | TX6_FEC_PAD_CTRL,
134         MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | TX6_FEC_PAD_CTRL,
135 };
136
137 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
138         /* internal I2C */
139         MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_CFG_SION |
140         TX6_GPIO_PAD_CTRL,
141         MX6_PAD_EIM_D21__GPIO3_IO21 | MUX_CFG_SION |
142         TX6_GPIO_PAD_CTRL,
143 };
144
145 static const iomux_v3_cfg_t const tx6_i2c_pads[] = {
146         /* internal I2C */
147         MX6_PAD_EIM_D28__I2C1_SDA | TX6_I2C_PAD_CTRL,
148         MX6_PAD_EIM_D21__I2C1_SCL | TX6_I2C_PAD_CTRL,
149 };
150
151 static const struct gpio const tx6qdl_gpios[] = {
152         /* These two entries are used to forcefully reinitialize the I2C bus */
153         { TX6_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
154         { TX6_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
155
156         { TX6_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", },
157         { TX6_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
158         { TX6_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
159         { TX6_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
160 };
161
162 static int pmic_addr __data;
163
164 #if defined(TX6_I2C1_SCL_GPIO) && defined(TX6_I2C1_SDA_GPIO)
165 #define SCL_BANK        (TX6_I2C1_SCL_GPIO / 32)
166 #define SDA_BANK        (TX6_I2C1_SDA_GPIO / 32)
167 #define SCL_BIT         (1 << (TX6_I2C1_SCL_GPIO % 32))
168 #define SDA_BIT         (1 << (TX6_I2C1_SDA_GPIO % 32))
169
170 static void * const gpio_ports[] = {
171         (void *)GPIO1_BASE_ADDR,
172         (void *)GPIO2_BASE_ADDR,
173         (void *)GPIO3_BASE_ADDR,
174         (void *)GPIO4_BASE_ADDR,
175         (void *)GPIO5_BASE_ADDR,
176         (void *)GPIO6_BASE_ADDR,
177         (void *)GPIO7_BASE_ADDR,
178 };
179
180 static void tx6_i2c_recover(void)
181 {
182         int i;
183         int bad = 0;
184         struct gpio_regs *scl_regs = gpio_ports[SCL_BANK];
185         struct gpio_regs *sda_regs = gpio_ports[SDA_BANK];
186
187         if ((readl(&scl_regs->gpio_psr) & SCL_BIT) &&
188             (readl(&sda_regs->gpio_psr) & SDA_BIT))
189                 return;
190
191         debug("Clearing I2C bus\n");
192         if (!(readl(&scl_regs->gpio_psr) & SCL_BIT)) {
193                 printf("I2C SCL stuck LOW\n");
194                 bad++;
195
196                 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
197                 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
198
199                 imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
200                                                  ARRAY_SIZE(tx6_i2c_gpio_pads));
201         }
202         if (!(readl(&sda_regs->gpio_psr) & SDA_BIT)) {
203                 printf("I2C SDA stuck LOW\n");
204
205                 clrbits_le32(&sda_regs->gpio_dir, SDA_BIT);
206                 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
207                 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
208
209                 if (!bad++)
210                         imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
211                                                          ARRAY_SIZE(tx6_i2c_gpio_pads));
212
213                 udelay(10);
214
215                 for (i = 0; i < 18; i++) {
216                         u32 reg = readl(&scl_regs->gpio_dr) ^ SCL_BIT;
217
218                         debug("%sing SCL\n",
219                               (reg & SCL_BIT) ? "Sett" : "Clear");
220                         writel(reg, &scl_regs->gpio_dr);
221                         udelay(5);
222                         if (reg & SCL_BIT) {
223                                 if (readl(&sda_regs->gpio_psr) & SDA_BIT)
224                                         break;
225                                 if (!(readl(&scl_regs->gpio_psr) & SCL_BIT))
226                                         break;
227                                 break;
228                         }
229                 }
230         }
231         if (bad) {
232                 bool scl = !!(readl(&scl_regs->gpio_psr) & SCL_BIT);
233                 bool sda = !!(readl(&sda_regs->gpio_psr) & SDA_BIT);
234
235                 if (scl && sda) {
236                         printf("I2C bus recovery succeeded\n");
237                 } else {
238                         printf("I2C bus recovery FAILED: SCL: %d SDA: %d\n",
239                                scl, sda);
240                 }
241                 imx_iomux_v3_setup_multiple_pads(tx6_i2c_pads,
242                                                  ARRAY_SIZE(tx6_i2c_pads));
243         }
244 }
245 #endif
246
247 /* placed in section '.data' to prevent overwriting relocation info
248  * overlayed with bss
249  */
250 static u32 wrsr __data;
251
252 #define WRSR_POR                        (1 << 4)
253 #define WRSR_TOUT                       (1 << 1)
254 #define WRSR_SFTW                       (1 << 0)
255
256 static void print_reset_cause(void)
257 {
258         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
259         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
260         u32 srsr;
261         char *dlm = "";
262
263         printf("Reset cause: ");
264
265         srsr = readl(&src_regs->srsr);
266         wrsr = readw(wdt_base + 4);
267
268         if (wrsr & WRSR_POR) {
269                 printf("%sPOR", dlm);
270                 dlm = " | ";
271         }
272         if (srsr & 0x00004) {
273                 printf("%sCSU", dlm);
274                 dlm = " | ";
275         }
276         if (srsr & 0x00008) {
277                 printf("%sIPP USER", dlm);
278                 dlm = " | ";
279         }
280         if (srsr & 0x00010) {
281                 if (wrsr & WRSR_SFTW) {
282                         printf("%sSOFT", dlm);
283                         dlm = " | ";
284                 }
285                 if (wrsr & WRSR_TOUT) {
286                         printf("%sWDOG", dlm);
287                         dlm = " | ";
288                 }
289         }
290         if (srsr & 0x00020) {
291                 printf("%sJTAG HIGH-Z", dlm);
292                 dlm = " | ";
293         }
294         if (srsr & 0x00040) {
295                 printf("%sJTAG SW", dlm);
296                 dlm = " | ";
297         }
298         if (srsr & 0x10000) {
299                 printf("%sWARM BOOT", dlm);
300                 dlm = " | ";
301         }
302         if (dlm[0] == '\0')
303                 printf("unknown");
304
305         printf("\n");
306 }
307
308 static const char __data *tx6_mod_suffix;
309
310 #ifdef CONFIG_IMX6_THERMAL
311 #include <thermal.h>
312 #include <imx_thermal.h>
313 #include <fuse.h>
314
315 static void print_temperature(void)
316 {
317         struct udevice *thermal_dev;
318         int cpu_tmp, minc, maxc, ret;
319         char const *grade_str;
320         static u32 __data thermal_calib;
321
322         puts("Temperature: ");
323         switch (get_cpu_temp_grade(&minc, &maxc)) {
324         case TEMP_AUTOMOTIVE:
325                 grade_str = "Automotive";
326                 break;
327         case TEMP_INDUSTRIAL:
328                 grade_str = "Industrial";
329                 break;
330         case TEMP_EXTCOMMERCIAL:
331                 grade_str = "Extended Commercial";
332                 break;
333         default:
334                 grade_str = "Commercial";
335         }
336         printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
337         ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
338         if (ret == 0) {
339                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
340
341                 if (ret == 0)
342                         printf(" at %dC", cpu_tmp);
343                 else
344                         puts(" - failed to read sensor data");
345         } else {
346                 puts(" - no sensor device found");
347         }
348
349         if (fuse_read(1, 6, &thermal_calib) == 0) {
350                 printf(" - calibration data 0x%08x\n", thermal_calib);
351         } else {
352                 puts(" - Failed to read thermal calib fuse\n");
353         }
354 }
355 #else
356 static inline void print_temperature(void)
357 {
358 }
359 #endif
360
361 int checkboard(void)
362 {
363         u32 cpurev = get_cpu_rev();
364         char *cpu_str = "?";
365
366         if (is_cpu_type(MXC_CPU_MX6SL)) {
367                 cpu_str = "SL";
368                 tx6_mod_suffix = "?";
369         } else if (is_cpu_type(MXC_CPU_MX6DL)) {
370                 cpu_str = "DL";
371                 tx6_mod_suffix = "U";
372         } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
373                 cpu_str = "SOLO";
374                 tx6_mod_suffix = "S";
375         } else if (is_cpu_type(MXC_CPU_MX6Q)) {
376                 cpu_str = "Q";
377                 tx6_mod_suffix = "Q";
378         } else if (is_cpu_type(MXC_CPU_MX6QP)) {
379                 cpu_str = "QP";
380                 tx6_mod_suffix = "QP";
381         }
382
383         printf("CPU:         Freescale i.MX6%s rev%d.%d at %d MHz\n",
384                cpu_str,
385                (cpurev & 0x000F0) >> 4,
386                (cpurev & 0x0000F) >> 0,
387                mxc_get_clock(MXC_ARM_CLK) / 1000000);
388
389         print_temperature();
390         print_reset_cause();
391 #ifdef CONFIG_MX6_TEMPERATURE_HOT
392         check_cpu_temperature(1);
393 #endif
394         tx6_i2c_recover();
395         return 0;
396 }
397
398 /* serial port not initialized at this point */
399 int board_early_init_f(void)
400 {
401         return 0;
402 }
403
404 #ifndef CONFIG_MX6_TEMPERATURE_HOT
405 static bool tx6_temp_check_enabled = true;
406 #else
407 #define tx6_temp_check_enabled  0
408 #endif
409
410 #ifdef CONFIG_TX6_NAND
411 #define TX6_FLASH_SZ    (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
412 #else
413 #ifdef CONFIG_MMC_BOOT_SIZE
414 #define TX6_FLASH_SZ    (CONFIG_MMC_BOOT_SIZE / 4096 + 2)
415 #else
416 #define TX6_FLASH_SZ    2
417 #endif
418 #endif /* CONFIG_TX6_NAND */
419
420 #define TX6_DDR_SZ      (ffs(CONFIG_SYS_SDRAM_BUS_WIDTH / 16) - 1)
421
422 static char tx6_mem_table[] = {
423         '4', /* TX6S-8034 256MiB SDRAM 16bit; 128MiB NAND */
424         '1', /* TX6U-8011 512MiB SDRAM 32bit; 128MiB NAND */
425         '0', /* TX6Q-1030/TX6U-8030 1GiB SDRAM 64bit; 128MiB NAND */
426         '?', /* N/A 256MiB SDRAM 16bit; 256MiB NAND */
427         '?', /* N/A 512MiB SDRAM 32bit; 256MiB NAND */
428         '2', /* TX6U-8012 1GiB SDRAM 64bit; 256MiB NAND */
429         '?', /* N/A 256MiB SDRAM 16bit; 4GiB eMMC */
430         '5', /* TX6S-8035 512MiB SDRAM 32bit; 4GiB eMMC */
431         '3', /* TX6U-8033 1GiB SDRAM 64bit; 4GiB eMMC */
432         '?', /* N/A 256MiB SDRAM 16bit; 8GiB eMMC */
433         '?', /* N/A 512MiB SDRAM 32bit; 8GiB eMMC */
434         '6', /* TX6Q-1036 1GiB SDRAM 64bit; 8GiB eMMC */
435 };
436
437 #ifdef CONFIG_RN5T567
438 /* PMIC settings */
439 #define VDD_RTC_VAL             rn5t_mV_to_regval_rtc(3000)
440 #define VDD_CORE_VAL            rn5t_mV_to_regval(1400)         /* DCDC1 */
441 #define VDD_CORE_VAL_LP         rn5t_mV_to_regval(900)
442 #define VDD_SOC_VAL             rn5t_mV_to_regval(1400)         /* DCDC2 */
443 #define VDD_SOC_VAL_LP          rn5t_mV_to_regval(1400)
444 #define VDD_DDR_VAL             rn5t_mV_to_regval(1350)         /* DCDC3 */
445 #define VDD_DDR_VAL_LP          rn5t_mV_to_regval(1350)
446 #define VDD_HIGH_VAL            rn5t_mV_to_regval(3000)         /* DCDC4 */
447 #define VDD_HIGH_VAL_LP         rn5t_mV_to_regval(3000)
448 #define VDD_IO_INT_VAL          rn5t_mV_to_regval2(3300)        /* LDO1 */
449 #define VDD_IO_INT_VAL_LP       rn5t_mV_to_regval2(3300)
450 #define VDD_IO_EXT_VAL          rn5t_mV_to_regval2(3300)        /* LDO2 */
451 #define VDD_IO_EXT_VAL_LP       rn5t_mV_to_regval2(3300)
452
453 static struct pmic_regs rn5t567_regs[] = {
454         { RN5T567_NOETIMSET, 0x5, },
455         { RN5T567_DC1DAC, VDD_CORE_VAL, },
456         { RN5T567_DC2DAC, VDD_SOC_VAL, },
457         { RN5T567_DC3DAC, VDD_DDR_VAL, },
458         { RN5T567_DC4DAC, VDD_HIGH_VAL, },
459         { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
460         { RN5T567_DC2DAC_SLP, VDD_SOC_VAL_LP, },
461         { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
462         { RN5T567_DC4DAC_SLP, VDD_HIGH_VAL_LP, },
463         { RN5T567_DC1CTL, DCnCTL_EN | DCnMODE_SLP(MODE_PSM), },
464         { RN5T567_DC2CTL, DCnCTL_EN | DCnMODE_SLP(MODE_PSM), },
465         { RN5T567_DC3CTL, DCnCTL_EN | DCnMODE_SLP(MODE_PSM), },
466         { RN5T567_DC4CTL, DCnCTL_EN | DCnMODE_SLP(MODE_PSM), },
467         { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
468         { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
469         { RN5T567_LDO1DAC, VDD_IO_INT_VAL, },
470         { RN5T567_LDO2DAC, VDD_IO_EXT_VAL, },
471         { RN5T567_LDOEN1, 0x03, ~0x1f, },
472         { RN5T567_LDOEN2, 0x10, ~0x30, },
473         { RN5T567_LDODIS, 0x1c, ~0x1f, },
474         { RN5T567_INTPOL, 0, },
475         { RN5T567_INTEN, 0x3, },
476         { RN5T567_DCIREN, 0xf, },
477         { RN5T567_EN_GPIR, 0, },
478 };
479 #endif
480
481 static struct {
482         uchar addr;
483         uchar rev;
484         struct pmic_regs *regs;
485         size_t num_regs;
486 } tx6_mod_revs[] = {
487 #ifdef CONFIG_LTC3676
488         { 0x3c, 1, NULL, 0, },
489 #endif
490 #ifdef CONFIG_RN5T567
491         { 0x33, 3, rn5t567_regs, ARRAY_SIZE(rn5t567_regs), },
492 #endif
493 };
494
495 static inline char tx6_mem_suffix(void)
496 {
497         size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
498
499         debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
500               TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
501
502         if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
503                 return '?';
504         if (CONFIG_SYS_SDRAM_CHIP_SIZE > 512)
505                 return '7';
506         if (mem_idx == 8)
507                 return is_cpu_type(MXC_CPU_MX6Q) ? '6' : '3';
508         return tx6_mem_table[mem_idx];
509 };
510
511 static int tx6_get_mod_rev(unsigned int pmic_id)
512 {
513         if (pmic_id < ARRAY_SIZE(tx6_mod_revs))
514                 return tx6_mod_revs[pmic_id].rev;
515
516         return 0;
517 }
518
519 static int tx6_pmic_probe(void)
520 {
521         int i;
522
523         debug("%s@%d: \n", __func__, __LINE__);
524
525         for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) {
526                 u8 i2c_addr = tx6_mod_revs[i].addr;
527                 int ret = i2c_probe(i2c_addr);
528
529                 if (ret == 0) {
530                         debug("I2C probe succeeded for addr 0x%02x\n",
531                               i2c_addr);
532                         return i;
533                 }
534                 debug("I2C probe returned %d for addr 0x%02x\n", ret, i2c_addr);
535         }
536         return -EINVAL;
537 }
538
539 static int tx6_mipi(void)
540 {
541         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
542         struct fuse_bank4_regs *fuse = (void *)ocotp->bank[4].fuse_regs;
543         u32 gp1 = readl(&fuse->gp1);
544
545         debug("Fuse gp1 @ %p = %08x\n", &fuse->gp1, gp1);
546         return gp1 & 1;
547 }
548
549 int board_init(void)
550 {
551         int ret;
552         int pmic_id;
553
554         debug("%s@%d: \n", __func__, __LINE__);
555
556         pmic_id = tx6_pmic_probe();
557         if (pmic_id >= 0 && pmic_id < ARRAY_SIZE(tx6_mod_revs))
558                 pmic_addr = tx6_mod_revs[pmic_id].addr;
559
560         printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
561                tx6_mod_suffix,
562                is_cpu_type(MXC_CPU_MX6Q) ? 1 : 8,
563                tx6_mipi() ? 2 : is_lvds(), tx6_get_mod_rev(pmic_id),
564                tx6_mem_suffix());
565
566         get_hab_status();
567
568         ret = gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
569         if (ret < 0) {
570                 printf("Failed to request tx6qdl_gpios: %d\n", ret);
571         }
572         imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
573
574         /* Address of boot parameters */
575         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
576         gd->bd->bi_arch_number = -1;
577
578         if (ctrlc() || (wrsr & WRSR_TOUT)) {
579                 if (wrsr & WRSR_TOUT)
580                         printf("WDOG RESET detected; Skipping PMIC setup\n");
581                 else
582                         printf("<CTRL-C> detected; safeboot enabled\n");
583 #ifndef CONFIG_MX6_TEMPERATURE_HOT
584                 tx6_temp_check_enabled = false;
585 #endif
586                 return 0;
587         }
588
589         ret = tx6_pmic_init(pmic_addr, tx6_mod_revs[pmic_id].regs,
590                             tx6_mod_revs[pmic_id].num_regs);
591         if (ret) {
592                 printf("Failed to setup PMIC voltages: %d\n", ret);
593                 hang();
594         }
595         return 0;
596 }
597
598 int dram_init(void)
599 {
600         debug("%s@%d: \n", __func__, __LINE__);
601
602         /* dram_init must store complete ramsize in gd->ram_size */
603         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
604                                     PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
605         return 0;
606 }
607
608 void dram_init_banksize(void)
609 {
610         debug("%s@%d: chip_size=%u (%u bit bus width)\n", __func__, __LINE__,
611               CONFIG_SYS_SDRAM_CHIP_SIZE, CONFIG_SYS_SDRAM_BUS_WIDTH);
612         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
613         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
614                                                PHYS_SDRAM_1_SIZE);
615 #if CONFIG_NR_DRAM_BANKS > 1
616         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
617         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
618                                                PHYS_SDRAM_2_SIZE);
619 #endif
620 }
621
622 #ifdef  CONFIG_FSL_ESDHC
623 #define SD_PAD_CTRL             MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |       \
624                                              PAD_CTL_SPEED_MED |        \
625                                              PAD_CTL_DSE_40ohm |        \
626                                              PAD_CTL_SRE_FAST)
627
628 static const iomux_v3_cfg_t mmc0_pads[] = {
629         MX6_PAD_SD1_CMD__SD1_CMD | SD_PAD_CTRL,
630         MX6_PAD_SD1_CLK__SD1_CLK | SD_PAD_CTRL,
631         MX6_PAD_SD1_DAT0__SD1_DATA0 | SD_PAD_CTRL,
632         MX6_PAD_SD1_DAT1__SD1_DATA1 | SD_PAD_CTRL,
633         MX6_PAD_SD1_DAT2__SD1_DATA2 | SD_PAD_CTRL,
634         MX6_PAD_SD1_DAT3__SD1_DATA3 | SD_PAD_CTRL,
635         /* SD1 CD */
636         MX6_PAD_SD3_CMD__GPIO7_IO02 | TX6_GPIO_PAD_CTRL,
637 };
638
639 static const iomux_v3_cfg_t mmc1_pads[] = {
640         MX6_PAD_SD2_CMD__SD2_CMD | SD_PAD_CTRL,
641         MX6_PAD_SD2_CLK__SD2_CLK | SD_PAD_CTRL,
642         MX6_PAD_SD2_DAT0__SD2_DATA0 | SD_PAD_CTRL,
643         MX6_PAD_SD2_DAT1__SD2_DATA1 | SD_PAD_CTRL,
644         MX6_PAD_SD2_DAT2__SD2_DATA2 | SD_PAD_CTRL,
645         MX6_PAD_SD2_DAT3__SD2_DATA3 | SD_PAD_CTRL,
646         /* SD2 CD */
647         MX6_PAD_SD3_CLK__GPIO7_IO03 | TX6_GPIO_PAD_CTRL,
648 };
649
650 #ifdef CONFIG_TX6_EMMC
651 static const iomux_v3_cfg_t mmc3_pads[] = {
652         MX6_PAD_SD4_CMD__SD4_CMD | SD_PAD_CTRL,
653         MX6_PAD_SD4_CLK__SD4_CLK | SD_PAD_CTRL,
654         MX6_PAD_SD4_DAT0__SD4_DATA0 | SD_PAD_CTRL,
655         MX6_PAD_SD4_DAT1__SD4_DATA1 | SD_PAD_CTRL,
656         MX6_PAD_SD4_DAT2__SD4_DATA2 | SD_PAD_CTRL,
657         MX6_PAD_SD4_DAT3__SD4_DATA3 | SD_PAD_CTRL,
658         /* eMMC RESET */
659         MX6_PAD_NANDF_ALE__SD4_RESET | SD_PAD_CTRL,
660 };
661 #endif
662
663 static struct tx6_esdhc_cfg {
664         const iomux_v3_cfg_t *pads;
665         int num_pads;
666         enum mxc_clock clkid;
667         struct fsl_esdhc_cfg cfg;
668         int cd_gpio;
669 } tx6qdl_esdhc_cfg[] = {
670 #ifdef CONFIG_TX6_EMMC
671         {
672                 .pads = mmc3_pads,
673                 .num_pads = ARRAY_SIZE(mmc3_pads),
674                 .clkid = MXC_ESDHC4_CLK,
675                 .cfg = {
676                         .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
677                         .max_bus_width = 4,
678                 },
679                 .cd_gpio = -EINVAL,
680         },
681 #endif
682         {
683                 .pads = mmc0_pads,
684                 .num_pads = ARRAY_SIZE(mmc0_pads),
685                 .clkid = MXC_ESDHC_CLK,
686                 .cfg = {
687                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
688                         .max_bus_width = 4,
689                 },
690                 .cd_gpio = IMX_GPIO_NR(7, 2),
691         },
692         {
693                 .pads = mmc1_pads,
694                 .num_pads = ARRAY_SIZE(mmc1_pads),
695                 .clkid = MXC_ESDHC2_CLK,
696                 .cfg = {
697                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
698                         .max_bus_width = 4,
699                 },
700                 .cd_gpio = IMX_GPIO_NR(7, 3),
701         },
702 };
703
704 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
705 {
706         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
707 }
708
709 int board_mmc_getcd(struct mmc *mmc)
710 {
711         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
712
713         if (cfg->cd_gpio < 0)
714                 return 1;
715
716         debug("SD card %d is %spresent (GPIO %d)\n",
717               cfg - tx6qdl_esdhc_cfg,
718               gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
719               cfg->cd_gpio);
720         return !gpio_get_value(cfg->cd_gpio);
721 }
722
723 int board_mmc_init(bd_t *bis)
724 {
725         int i;
726
727         debug("%s@%d: \n", __func__, __LINE__);
728
729         for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
730                 struct mmc *mmc;
731                 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
732                 int ret;
733
734                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
735                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
736
737                 if (cfg->cd_gpio >= 0) {
738                         ret = gpio_request_one(cfg->cd_gpio,
739                                                GPIOFLAG_INPUT, "MMC CD");
740                         if (ret) {
741                                 printf("Error %d requesting GPIO%d_%d\n",
742                                        ret, cfg->cd_gpio / 32,
743                                        cfg->cd_gpio % 32);
744                                 continue;
745                         }
746                 }
747
748                 debug("%s: Initializing MMC slot %d\n", __func__, i);
749                 fsl_esdhc_initialize(bis, &cfg->cfg);
750
751                 mmc = find_mmc_device(i);
752                 if (mmc == NULL)
753                         continue;
754                 if (board_mmc_getcd(mmc))
755                         mmc_init(mmc);
756         }
757         return 0;
758 }
759 #endif /* CONFIG_CMD_MMC */
760
761 #ifdef CONFIG_FEC_MXC
762
763 #ifndef ETH_ALEN
764 #define ETH_ALEN 6
765 #endif
766
767 int board_eth_init(bd_t *bis)
768 {
769         int ret;
770
771         debug("%s@%d: \n", __func__, __LINE__);
772
773         /* delay at least 21ms for the PHY internal POR signal to deassert */
774         udelay(22000);
775
776         imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads,
777                                          ARRAY_SIZE(tx6qdl_fec_pads));
778
779         /* Deassert RESET to the external phy */
780         gpio_set_value(TX6_FEC_RST_GPIO, 1);
781
782         ret = cpu_eth_init(bis);
783         if (ret)
784                 printf("cpu_eth_init() failed: %d\n", ret);
785
786         return ret;
787 }
788
789 static void tx6_init_mac(void)
790 {
791         u8 mac[ETH_ALEN];
792
793         imx_get_mac_from_fuse(0, mac);
794         if (!is_valid_ethaddr(mac)) {
795                 printf("No valid MAC address programmed\n");
796                 return;
797         }
798
799         printf("MAC addr from fuse: %pM\n", mac);
800         eth_setenv_enetaddr("ethaddr", mac);
801 }
802 #else
803 static inline void tx6_init_mac(void)
804 {
805 }
806 #endif /* CONFIG_FEC_MXC */
807
808 enum {
809         LED_STATE_INIT = -1,
810         LED_STATE_OFF,
811         LED_STATE_ON,
812 };
813
814 static inline int calc_blink_rate(void)
815 {
816         if (!tx6_temp_check_enabled)
817                 return CONFIG_SYS_HZ;
818
819         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
820                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
821                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
822 }
823
824 void show_activity(int arg)
825 {
826         static int led_state = LED_STATE_INIT;
827         static int blink_rate;
828         static ulong last;
829
830         if (led_state == LED_STATE_INIT) {
831                 last = get_timer(0);
832                 gpio_set_value(TX6_LED_GPIO, 1);
833                 led_state = LED_STATE_ON;
834                 blink_rate = calc_blink_rate();
835         } else {
836                 if (get_timer(last) > blink_rate) {
837                         blink_rate = calc_blink_rate();
838                         last = get_timer_masked();
839                         if (led_state == LED_STATE_ON) {
840                                 gpio_set_value(TX6_LED_GPIO, 0);
841                         } else {
842                                 gpio_set_value(TX6_LED_GPIO, 1);
843                         }
844                         led_state = 1 - led_state;
845                 }
846         }
847 }
848
849 static const iomux_v3_cfg_t stk5_pads[] = {
850         /* SW controlled LED on STK5 baseboard */
851         MX6_PAD_EIM_A18__GPIO2_IO20 | TX6_GPIO_PAD_CTRL,
852
853         /* I2C bus on DIMM pins 40/41 */
854         MX6_PAD_GPIO_6__I2C3_SDA | TX6_I2C_PAD_CTRL,
855         MX6_PAD_GPIO_3__I2C3_SCL | TX6_I2C_PAD_CTRL,
856
857         /* TSC200x PEN IRQ */
858         MX6_PAD_EIM_D26__GPIO3_IO26 | TX6_GPIO_PAD_CTRL,
859
860         /* EDT-FT5x06 Polytouch panel */
861         MX6_PAD_NANDF_CS2__GPIO6_IO15 | TX6_GPIO_PAD_CTRL, /* IRQ */
862         MX6_PAD_EIM_A16__GPIO2_IO22 | TX6_GPIO_PAD_CTRL, /* RESET */
863         MX6_PAD_EIM_A17__GPIO2_IO21 | TX6_GPIO_PAD_CTRL, /* WAKE */
864
865         /* USBH1 */
866         MX6_PAD_EIM_D31__GPIO3_IO31 | TX6_GPIO_PAD_CTRL, /* VBUSEN */
867         MX6_PAD_EIM_D30__GPIO3_IO30 | TX6_GPIO_PAD_CTRL, /* OC */
868         /* USBOTG */
869         MX6_PAD_EIM_D23__GPIO3_IO23 | TX6_GPIO_PAD_CTRL, /* USBOTG ID */
870         MX6_PAD_GPIO_7__GPIO1_IO07 | TX6_GPIO_PAD_CTRL, /* VBUSEN */
871         MX6_PAD_GPIO_8__GPIO1_IO08 | TX6_GPIO_PAD_CTRL, /* OC */
872 };
873
874 static const struct gpio stk5_gpios[] = {
875         { TX6_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
876
877         { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
878         { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
879         { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
880         { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
881         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
882 };
883
884 #ifdef CONFIG_LCD
885 vidinfo_t panel_info = {
886         /* set to max. size supported by SoC */
887         .vl_col = 1920,
888         .vl_row = 1080,
889
890         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
891 };
892
893 static struct fb_videomode tx6_fb_modes[] = {
894         {
895                 /* Standard VGA timing */
896                 .name           = "VGA",
897                 .refresh        = 60,
898                 .xres           = 640,
899                 .yres           = 480,
900                 .pixclock       = KHZ2PICOS(25175),
901                 .left_margin    = 48,
902                 .hsync_len      = 96,
903                 .right_margin   = 16,
904                 .upper_margin   = 31,
905                 .vsync_len      = 2,
906                 .lower_margin   = 12,
907                 .sync           = FB_SYNC_CLK_LAT_FALL,
908         },
909         {
910                 /* Emerging ETV570 640 x 480 display. Syncs low active,
911                  * DE high active, 115.2 mm x 86.4 mm display area
912                  * VGA compatible timing
913                  */
914                 .name           = "ETV570",
915                 .refresh        = 60,
916                 .xres           = 640,
917                 .yres           = 480,
918                 .pixclock       = KHZ2PICOS(25175),
919                 .left_margin    = 114,
920                 .hsync_len      = 30,
921                 .right_margin   = 16,
922                 .upper_margin   = 32,
923                 .vsync_len      = 3,
924                 .lower_margin   = 10,
925                 .sync           = FB_SYNC_CLK_LAT_FALL,
926         },
927         {
928                 /* Emerging ETM0700G0DH6 800 x 480 display.
929                  * 152.4 mm x 91.44 mm display area.
930                  */
931                 .name           = "ET0700",
932                 .refresh        = 60,
933                 .xres           = 800,
934                 .yres           = 480,
935                 .pixclock       = KHZ2PICOS(33260),
936                 .left_margin    = 88,
937                 .hsync_len      = 128,
938                 .right_margin   = 40,
939                 .upper_margin   = 33,
940                 .vsync_len      = 2,
941                 .lower_margin   = 10,
942                 .sync           = FB_SYNC_CLK_LAT_FALL,
943         },
944 #ifndef CONFIG_SYS_LVDS_IF
945         {
946                 /* Emerging ET0350G0DH6 320 x 240 display.
947                  * 70.08 mm x 52.56 mm display area.
948                  */
949                 .name           = "ET0350",
950                 .refresh        = 60,
951                 .xres           = 320,
952                 .yres           = 240,
953                 .pixclock       = KHZ2PICOS(6500),
954                 .left_margin    = 34,
955                 .hsync_len      = 34,
956                 .right_margin   = 20,
957                 .upper_margin   = 15,
958                 .vsync_len      = 3,
959                 .lower_margin   = 4,
960                 .sync           = FB_SYNC_CLK_LAT_FALL,
961         },
962         {
963                 /* Emerging ET0430G0DH6 480 x 272 display.
964                  * 95.04 mm x 53.856 mm display area.
965                  */
966                 .name           = "ET0430",
967                 .refresh        = 60,
968                 .xres           = 480,
969                 .yres           = 272,
970                 .pixclock       = KHZ2PICOS(9000),
971                 .left_margin    = 2,
972                 .hsync_len      = 41,
973                 .right_margin   = 2,
974                 .upper_margin   = 2,
975                 .vsync_len      = 10,
976                 .lower_margin   = 2,
977         },
978         {
979                 /* Emerging ET0500G0DH6 800 x 480 display.
980                  * 109.6 mm x 66.4 mm display area.
981                  */
982                 .name           = "ET0500",
983                 .refresh        = 60,
984                 .xres           = 800,
985                 .yres           = 480,
986                 .pixclock       = KHZ2PICOS(33260),
987                 .left_margin    = 88,
988                 .hsync_len      = 128,
989                 .right_margin   = 40,
990                 .upper_margin   = 33,
991                 .vsync_len      = 2,
992                 .lower_margin   = 10,
993                 .sync           = FB_SYNC_CLK_LAT_FALL,
994         },
995         {
996                 /* Emerging ETQ570G0DH6 320 x 240 display.
997                  * 115.2 mm x 86.4 mm display area.
998                  */
999                 .name           = "ETQ570",
1000                 .refresh        = 60,
1001                 .xres           = 320,
1002                 .yres           = 240,
1003                 .pixclock       = KHZ2PICOS(6400),
1004                 .left_margin    = 38,
1005                 .hsync_len      = 30,
1006                 .right_margin   = 30,
1007                 .upper_margin   = 16, /* 15 according to datasheet */
1008                 .vsync_len      = 3, /* TVP -> 1>x>5 */
1009                 .lower_margin   = 4, /* 4.5 according to datasheet */
1010                 .sync           = FB_SYNC_CLK_LAT_FALL,
1011         },
1012 #else
1013         {
1014                 /* HannStar HSD100PXN1
1015                  * 202.7m mm x 152.06 mm display area.
1016                  */
1017                 .name           = "HSD100PXN1",
1018                 .refresh        = 60,
1019                 .xres           = 1024,
1020                 .yres           = 768,
1021                 .pixclock       = KHZ2PICOS(65000),
1022                 .left_margin    = 0,
1023                 .hsync_len      = 0,
1024                 .right_margin   = 320,
1025                 .upper_margin   = 0,
1026                 .vsync_len      = 0,
1027                 .lower_margin   = 38,
1028                 .sync           = FB_SYNC_CLK_LAT_FALL,
1029         },
1030 #endif
1031         {
1032                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
1033                 .refresh        = 60,
1034                 .left_margin    = 48,
1035                 .hsync_len      = 96,
1036                 .right_margin   = 16,
1037                 .upper_margin   = 31,
1038                 .vsync_len      = 2,
1039                 .lower_margin   = 12,
1040                 .sync           = FB_SYNC_CLK_LAT_FALL,
1041         },
1042 };
1043
1044 static int lcd_enabled = 1;
1045 static int lcd_bl_polarity;
1046
1047 static int lcd_backlight_polarity(void)
1048 {
1049         return lcd_bl_polarity;
1050 }
1051
1052 void lcd_enable(void)
1053 {
1054         /* HACK ALERT:
1055          * global variable from common/lcd.c
1056          * Set to 0 here to prevent messages from going to LCD
1057          * rather than serial console
1058          */
1059         lcd_is_enabled = 0;
1060
1061         if (lcd_enabled) {
1062                 karo_load_splashimage(1);
1063
1064                 debug("Switching LCD on\n");
1065                 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
1066                 udelay(100);
1067                 gpio_set_value(TX6_LCD_RST_GPIO, 1);
1068                 udelay(300000);
1069                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
1070                                lcd_backlight_polarity());
1071         }
1072 }
1073
1074 void lcd_disable(void)
1075 {
1076         if (lcd_enabled) {
1077                 printf("Disabling LCD\n");
1078                 ipuv3_fb_shutdown();
1079         }
1080 }
1081
1082 void lcd_panel_disable(void)
1083 {
1084         if (lcd_enabled) {
1085                 debug("Switching LCD off\n");
1086                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
1087                                !lcd_backlight_polarity());
1088                 gpio_set_value(TX6_LCD_RST_GPIO, 0);
1089                 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
1090         }
1091 }
1092
1093 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
1094         /* LCD RESET */
1095         MX6_PAD_EIM_D29__GPIO3_IO29 | TX6_GPIO_PAD_CTRL,
1096         /* LCD POWER_ENABLE */
1097         MX6_PAD_EIM_EB3__GPIO2_IO31 | TX6_GPIO_PAD_CTRL,
1098         /* LCD Backlight (PWM) */
1099         MX6_PAD_GPIO_1__GPIO1_IO01 | TX6_GPIO_PAD_CTRL,
1100
1101 #ifndef CONFIG_SYS_LVDS_IF
1102         /* Display */
1103         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | TX6_GPIO_PAD_CTRL,
1104         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | TX6_GPIO_PAD_CTRL,
1105         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | TX6_GPIO_PAD_CTRL,
1106         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | TX6_GPIO_PAD_CTRL,
1107         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | TX6_GPIO_PAD_CTRL,
1108         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | TX6_GPIO_PAD_CTRL,
1109         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | TX6_GPIO_PAD_CTRL,
1110         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | TX6_GPIO_PAD_CTRL,
1111         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | TX6_GPIO_PAD_CTRL,
1112         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | TX6_GPIO_PAD_CTRL,
1113         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | TX6_GPIO_PAD_CTRL,
1114         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | TX6_GPIO_PAD_CTRL,
1115         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | TX6_GPIO_PAD_CTRL,
1116         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | TX6_GPIO_PAD_CTRL,
1117         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | TX6_GPIO_PAD_CTRL,
1118         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | TX6_GPIO_PAD_CTRL,
1119         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | TX6_GPIO_PAD_CTRL,
1120         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | TX6_GPIO_PAD_CTRL,
1121         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | TX6_GPIO_PAD_CTRL,
1122         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | TX6_GPIO_PAD_CTRL,
1123         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | TX6_GPIO_PAD_CTRL,
1124         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | TX6_GPIO_PAD_CTRL,
1125         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | TX6_GPIO_PAD_CTRL,
1126         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | TX6_GPIO_PAD_CTRL,
1127         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | TX6_GPIO_PAD_CTRL, /* HSYNC */
1128         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | TX6_GPIO_PAD_CTRL, /* VSYNC */
1129         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | TX6_GPIO_PAD_CTRL, /* OE_ACD */
1130         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | TX6_GPIO_PAD_CTRL, /* LSCLK */
1131 #endif
1132 };
1133
1134 static const struct gpio stk5_lcd_gpios[] = {
1135         { TX6_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1136         { TX6_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1137         { TX6_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1138 };
1139
1140 void lcd_ctrl_init(void *lcdbase)
1141 {
1142         int color_depth = 24;
1143         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1144         const char *vm;
1145         unsigned long val;
1146         int refresh = 60;
1147         struct fb_videomode *p = &tx6_fb_modes[0];
1148         struct fb_videomode fb_mode;
1149         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1150         int pix_fmt;
1151         int lcd_bus_width;
1152         unsigned long di_clk_rate = 65000000;
1153
1154         if (!lcd_enabled) {
1155                 debug("LCD disabled\n");
1156                 goto disable;
1157         }
1158
1159         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1160                 debug("Disabling LCD\n");
1161                 lcd_enabled = 0;
1162                 setenv("splashimage", NULL);
1163                 goto disable;
1164         }
1165
1166         karo_fdt_move_fdt();
1167         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1168
1169         if (video_mode == NULL) {
1170                 debug("Disabling LCD\n");
1171                 lcd_enabled = 0;
1172                 goto disable;
1173         }
1174         vm = video_mode;
1175         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1176                 p = &fb_mode;
1177                 debug("Using video mode from FDT\n");
1178                 vm += strlen(vm);
1179                 if (fb_mode.xres > panel_info.vl_col ||
1180                     fb_mode.yres > panel_info.vl_row) {
1181                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1182                                fb_mode.xres, fb_mode.yres,
1183                                panel_info.vl_col, panel_info.vl_row);
1184                         lcd_enabled = 0;
1185                         goto disable;
1186                 }
1187         }
1188         if (p->name != NULL)
1189                 debug("Trying compiled-in video modes\n");
1190         while (p->name != NULL) {
1191                 if (strcmp(p->name, vm) == 0) {
1192                         debug("Using video mode: '%s'\n", p->name);
1193                         vm += strlen(vm);
1194                         break;
1195                 }
1196                 p++;
1197         }
1198         if (*vm != '\0')
1199                 debug("Trying to decode video_mode: '%s'\n", vm);
1200         while (*vm != '\0') {
1201                 if (*vm >= '0' && *vm <= '9') {
1202                         char *end;
1203
1204                         val = simple_strtoul(vm, &end, 0);
1205                         if (end > vm) {
1206                                 if (!xres_set) {
1207                                         if (val > panel_info.vl_col)
1208                                                 val = panel_info.vl_col;
1209                                         p->xres = val;
1210                                         panel_info.vl_col = val;
1211                                         xres_set = 1;
1212                                 } else if (!yres_set) {
1213                                         if (val > panel_info.vl_row)
1214                                                 val = panel_info.vl_row;
1215                                         p->yres = val;
1216                                         panel_info.vl_row = val;
1217                                         yres_set = 1;
1218                                 } else if (!bpp_set) {
1219                                         switch (val) {
1220                                         case 32:
1221                                         case 24:
1222                                                 if (is_lvds())
1223                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
1224                                                 /* fallthru */
1225                                         case 16:
1226                                         case 8:
1227                                                 color_depth = val;
1228                                                 break;
1229
1230                                         case 18:
1231                                                 if (is_lvds()) {
1232                                                         color_depth = val;
1233                                                         break;
1234                                                 }
1235                                                 /* fallthru */
1236                                         default:
1237                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1238                                                        end - vm, vm,
1239                                                        color_depth);
1240                                         }
1241                                         bpp_set = 1;
1242                                 } else if (!refresh_set) {
1243                                         refresh = val;
1244                                         refresh_set = 1;
1245                                 }
1246                         }
1247                         vm = end;
1248                 }
1249                 switch (*vm) {
1250                 case '@':
1251                         bpp_set = 1;
1252                         /* fallthru */
1253                 case '-':
1254                         yres_set = 1;
1255                         /* fallthru */
1256                 case 'x':
1257                         xres_set = 1;
1258                         /* fallthru */
1259                 case 'M':
1260                 case 'R':
1261                         vm++;
1262                         break;
1263
1264                 default:
1265                         if (*vm != '\0')
1266                                 vm++;
1267                 }
1268         }
1269         if (p->xres == 0 || p->yres == 0) {
1270                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1271                 lcd_enabled = 0;
1272                 printf("Supported video modes are:");
1273                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1274                         printf(" %s", p->name);
1275                 }
1276                 printf("\n");
1277                 goto disable;
1278         }
1279         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1280                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1281                        p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1282                 lcd_enabled = 0;
1283                 goto disable;
1284         }
1285         panel_info.vl_col = p->xres;
1286         panel_info.vl_row = p->yres;
1287
1288         switch (color_depth) {
1289         case 8:
1290                 panel_info.vl_bpix = LCD_COLOR8;
1291                 break;
1292         case 16:
1293                 panel_info.vl_bpix = LCD_COLOR16;
1294                 break;
1295         default:
1296                 panel_info.vl_bpix = LCD_COLOR32;
1297         }
1298
1299         if (refresh_set || p->pixclock == 0)
1300                 p->pixclock = KHZ2PICOS(refresh *
1301                                         (p->xres + p->left_margin +
1302                                          p->right_margin + p->hsync_len) *
1303                                         (p->yres + p->upper_margin +
1304                                          p->lower_margin + p->vsync_len) /
1305                                         1000);
1306         debug("Pixel clock set to %lu.%03lu MHz\n",
1307               PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1308
1309         if (p != &fb_mode) {
1310                 int ret;
1311
1312                 debug("Creating new display-timing node from '%s'\n",
1313                       video_mode);
1314                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1315                 if (ret)
1316                         printf("Failed to create new display-timing node from '%s': %d\n",
1317                                video_mode, ret);
1318         }
1319
1320         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1321         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1322                                          ARRAY_SIZE(stk5_lcd_pads));
1323
1324         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1325         switch (lcd_bus_width) {
1326         case 24:
1327                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1328                 break;
1329
1330         case 18:
1331                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1332                 break;
1333
1334         case 16:
1335                 if (!is_lvds()) {
1336                         pix_fmt = IPU_PIX_FMT_RGB565;
1337                         break;
1338                 }
1339                 /* fallthru */
1340         default:
1341                 lcd_enabled = 0;
1342                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1343                        lcd_bus_width);
1344                 goto disable;
1345         }
1346         if (is_lvds()) {
1347                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1348                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1349                 uint32_t gpr2;
1350                 uint32_t gpr3;
1351
1352                 if (lvds_chan_mask == 0) {
1353                         printf("No LVDS channel active\n");
1354                         lcd_enabled = 0;
1355                         goto disable;
1356                 }
1357
1358                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1359                 if (lcd_bus_width == 24)
1360                         gpr2 |= (1 << 5) | (1 << 7);
1361                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1362                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1363                 debug("writing %08x to GPR2[%08x]\n", gpr2,
1364                       IOMUXC_BASE_ADDR + 8);
1365                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1366
1367                 gpr3 = readl(IOMUXC_BASE_ADDR + 0xc);
1368                 gpr3 &= ~((3 << 8) | (3 << 6));
1369                 writel(gpr3, IOMUXC_BASE_ADDR + 0xc);
1370         }
1371         if (karo_load_splashimage(0) == 0) {
1372                 int ret;
1373
1374                 debug("Initializing LCD controller\n");
1375                 ret = ipuv3_fb_init(p, 0, pix_fmt,
1376                                     is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
1377                                     di_clk_rate, -1);
1378                 if (ret) {
1379                         printf("Failed to initialize FB driver: %d\n", ret);
1380                         lcd_enabled = 0;
1381                 }
1382         } else {
1383                 debug("Skipping initialization of LCD controller\n");
1384         }
1385         return;
1386
1387  disable:
1388         lcd_enabled = 0;
1389         panel_info.vl_col = 0;
1390         panel_info.vl_row = 0;
1391 }
1392 #else
1393 #define lcd_enabled 0
1394 #endif /* CONFIG_LCD */
1395
1396 static void stk5_board_init(void)
1397 {
1398         int ret;
1399
1400         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1401         if (ret < 0) {
1402                 printf("Failed to request stk5_gpios: %d\n", ret);
1403                 return;
1404         }
1405         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1406 }
1407
1408 static void stk5v3_board_init(void)
1409 {
1410         stk5_board_init();
1411 }
1412
1413 static void stk5v5_board_init(void)
1414 {
1415         int ret;
1416
1417         stk5_board_init();
1418
1419         ret = gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH,
1420                                "Flexcan Transceiver");
1421         if (ret) {
1422                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1423                 return;
1424         }
1425
1426         imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21 |
1427                                TX6_GPIO_PAD_CTRL);
1428 }
1429
1430 static void tx6qdl_set_cpu_clock(void)
1431 {
1432         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1433
1434         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1435                 return;
1436
1437         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1438                 printf("%s detected; skipping cpu clock change\n",
1439                        (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1440                 return;
1441         }
1442         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1443                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1444                 printf("CPU clock set to %lu.%03lu MHz\n",
1445                        cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1446         } else {
1447                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1448         }
1449 }
1450
1451 int board_late_init(void)
1452 {
1453         const char *baseboard;
1454
1455         debug("%s@%d: \n", __func__, __LINE__);
1456
1457         env_cleanup();
1458
1459         if (tx6_temp_check_enabled)
1460                 check_cpu_temperature(1);
1461
1462         tx6qdl_set_cpu_clock();
1463
1464         if (had_ctrlc())
1465                 setenv_ulong("safeboot", 1);
1466         else if (wrsr & WRSR_TOUT)
1467                 setenv_ulong("wdreset", 1);
1468         else
1469                 karo_fdt_move_fdt();
1470
1471         baseboard = getenv("baseboard");
1472         if (!baseboard)
1473                 goto exit;
1474
1475         printf("Baseboard: %s\n", baseboard);
1476
1477         if (strncmp(baseboard, "stk5", 4) == 0) {
1478                 if ((strlen(baseboard) == 4) ||
1479                     strcmp(baseboard, "stk5-v3") == 0) {
1480                         stk5v3_board_init();
1481                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1482                         const char *otg_mode = getenv("otg_mode");
1483
1484                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1485                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1486                                        otg_mode, baseboard);
1487                                 setenv("otg_mode", "none");
1488                         }
1489                         stk5v5_board_init();
1490                 } else {
1491                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1492                                baseboard + 4);
1493                 }
1494         } else {
1495                 printf("WARNING: Unsupported baseboard: '%s'\n",
1496                        baseboard);
1497                 if (!had_ctrlc())
1498                         return -EINVAL;
1499         }
1500
1501 exit:
1502         tx6_init_mac();
1503
1504         gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1505         clear_ctrlc();
1506         return 0;
1507 }
1508
1509 #ifdef CONFIG_SERIAL_TAG
1510 void get_board_serial(struct tag_serialnr *serialnr)
1511 {
1512         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1513         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1514
1515         serialnr->low = readl(&fuse->cfg0);
1516         serialnr->high = readl(&fuse->cfg1);
1517 }
1518 #endif
1519
1520 #if defined(CONFIG_OF_BOARD_SETUP)
1521 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1522 #include <jffs2/jffs2.h>
1523 #include <mtd_node.h>
1524 static struct node_info nodes[] = {
1525         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1526 };
1527 #else
1528 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1529 #endif
1530
1531 static const char *tx6_touchpanels[] = {
1532         "ti,tsc2007",
1533         "edt,edt-ft5x06",
1534         "eeti,egalax_ts",
1535 };
1536
1537 int ft_board_setup(void *blob, bd_t *bd)
1538 {
1539         const char *baseboard = getenv("baseboard");
1540         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1541         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1542         int ret;
1543
1544         ret = fdt_increase_size(blob, 4096);
1545         if (ret) {
1546                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1547                 return ret;
1548         }
1549         if (stk5_v5)
1550                 karo_fdt_enable_node(blob, "stk5led", 0);
1551
1552         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1553
1554         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1555                                   ARRAY_SIZE(tx6_touchpanels));
1556         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1557         karo_fdt_fixup_flexcan(blob, stk5_v5);
1558
1559 #ifdef CONFIG_SYS_LVDS_IF
1560         karo_fdt_update_fb_mode(blob, video_mode, "/lvds0-panel");
1561         karo_fdt_update_fb_mode(blob, video_mode, "/lvds1-panel");
1562 #else
1563         karo_fdt_update_fb_mode(blob, video_mode, "/lcd-panel");
1564 #endif
1565         return 0;
1566 }
1567 #endif /* CONFIG_OF_BOARD_SETUP */