karo: tx6: Unify code for TX6 module revisions
[karo-tx-uboot.git] / board / karo / tx6 / tx6qdl.c
1 /*
2  * Copyright (C) 2012,2013 Lothar WaƟmann <LW@KARO-electronics.de>
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License
9  * version 2 as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17
18 #include <common.h>
19 #include <errno.h>
20 #include <libfdt.h>
21 #include <fdt_support.h>
22 #include <lcd.h>
23 #include <netdev.h>
24 #include <mmc.h>
25 #include <fsl_esdhc.h>
26 #include <video_fb.h>
27 #include <ipu.h>
28 #include <mxcfb.h>
29 #include <i2c.h>
30 #include <linux/fb.h>
31 #include <asm/io.h>
32 #include <asm/gpio.h>
33 #include <asm/arch/mx6-pins.h>
34 #include <asm/arch/clock.h>
35 #include <asm/arch/imx-regs.h>
36 #include <asm/arch/crm_regs.h>
37 #include <asm/arch/sys_proto.h>
38
39 #include "../common/karo.h"
40 #include "pmic.h"
41
42 #define TX6_FEC_RST_GPIO                IMX_GPIO_NR(7, 6)
43 #define TX6_FEC_PWR_GPIO                IMX_GPIO_NR(3, 20)
44 #define TX6_FEC_INT_GPIO                IMX_GPIO_NR(7, 1)
45 #define TX6_LED_GPIO                    IMX_GPIO_NR(2, 20)
46
47 #define TX6_LCD_PWR_GPIO                IMX_GPIO_NR(2, 31)
48 #define TX6_LCD_RST_GPIO                IMX_GPIO_NR(3, 29)
49 #define TX6_LCD_BACKLIGHT_GPIO          IMX_GPIO_NR(1, 1)
50
51 #define TX6_RESET_OUT_GPIO              IMX_GPIO_NR(7, 12)
52
53 #define TEMPERATURE_MIN                 -40
54 #define TEMPERATURE_HOT                 80
55 #define TEMPERATURE_MAX                 125
56
57 DECLARE_GLOBAL_DATA_PTR;
58
59 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
60
61 static const iomux_v3_cfg_t tx6qdl_pads[] = {
62 #ifdef CONFIG_TX6_V2
63         /* NAND flash pads */
64         MX6_PAD_NANDF_CLE__RAWNAND_CLE,
65         MX6_PAD_NANDF_ALE__RAWNAND_ALE,
66         MX6_PAD_NANDF_WP_B__RAWNAND_RESETN,
67         MX6_PAD_NANDF_RB0__RAWNAND_READY0,
68         MX6_PAD_NANDF_CS0__RAWNAND_CE0N,
69         MX6_PAD_SD4_CMD__RAWNAND_RDN,
70         MX6_PAD_SD4_CLK__RAWNAND_WRN,
71         MX6_PAD_NANDF_D0__RAWNAND_D0,
72         MX6_PAD_NANDF_D1__RAWNAND_D1,
73         MX6_PAD_NANDF_D2__RAWNAND_D2,
74         MX6_PAD_NANDF_D3__RAWNAND_D3,
75         MX6_PAD_NANDF_D4__RAWNAND_D4,
76         MX6_PAD_NANDF_D5__RAWNAND_D5,
77         MX6_PAD_NANDF_D6__RAWNAND_D6,
78         MX6_PAD_NANDF_D7__RAWNAND_D7,
79 #endif
80         /* RESET_OUT */
81         MX6_PAD_GPIO_17__GPIO_7_12,
82
83         /* UART pads */
84 #if CONFIG_MXC_UART_BASE == UART1_BASE
85         MX6_PAD_SD3_DAT7__UART1_TXD,
86         MX6_PAD_SD3_DAT6__UART1_RXD,
87         MX6_PAD_SD3_DAT1__UART1_RTS,
88         MX6_PAD_SD3_DAT0__UART1_CTS,
89 #endif
90 #if CONFIG_MXC_UART_BASE == UART2_BASE
91         MX6_PAD_SD4_DAT4__UART2_RXD,
92         MX6_PAD_SD4_DAT7__UART2_TXD,
93         MX6_PAD_SD4_DAT5__UART2_RTS,
94         MX6_PAD_SD4_DAT6__UART2_CTS,
95 #endif
96 #if CONFIG_MXC_UART_BASE == UART3_BASE
97         MX6_PAD_EIM_D24__UART3_TXD,
98         MX6_PAD_EIM_D25__UART3_RXD,
99         MX6_PAD_SD3_RST__UART3_RTS,
100         MX6_PAD_SD3_DAT3__UART3_CTS,
101 #endif
102         /* internal I2C */
103         MX6_PAD_EIM_D28__I2C1_SDA,
104         MX6_PAD_EIM_D21__I2C1_SCL,
105
106         /* FEC PHY GPIO functions */
107         MX6_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */
108         MX6_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */
109         MX6_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */
110 };
111
112 static const iomux_v3_cfg_t tx6qdl_fec_pads[] = {
113         /* FEC functions */
114         MX6_PAD_ENET_MDC__ENET_MDC,
115         MX6_PAD_ENET_MDIO__ENET_MDIO,
116         MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
117         MX6_PAD_ENET_RX_ER__ENET_RX_ER,
118         MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
119         MX6_PAD_ENET_RXD1__ENET_RDATA_1,
120         MX6_PAD_ENET_RXD0__ENET_RDATA_0,
121         MX6_PAD_ENET_TX_EN__ENET_TX_EN,
122         MX6_PAD_ENET_TXD1__ENET_TDATA_1,
123         MX6_PAD_ENET_TXD0__ENET_TDATA_0,
124 };
125
126 static const struct gpio tx6qdl_gpios[] = {
127         { TX6_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
128         { TX6_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
129         { TX6_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
130         { TX6_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
131 };
132
133 /*
134  * Functions
135  */
136 /* placed in section '.data' to prevent overwriting relocation info
137  * overlayed with bss
138  */
139 static u32 wrsr __attribute__((section(".data")));
140
141 #define WRSR_POR                        (1 << 4)
142 #define WRSR_TOUT                       (1 << 1)
143 #define WRSR_SFTW                       (1 << 0)
144
145 static void print_reset_cause(void)
146 {
147         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
148         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
149         u32 srsr;
150         char *dlm = "";
151
152         printf("Reset cause: ");
153
154         srsr = readl(&src_regs->srsr);
155         wrsr = readw(wdt_base + 4);
156
157         if (wrsr & WRSR_POR) {
158                 printf("%sPOR", dlm);
159                 dlm = " | ";
160         }
161         if (srsr & 0x00004) {
162                 printf("%sCSU", dlm);
163                 dlm = " | ";
164         }
165         if (srsr & 0x00008) {
166                 printf("%sIPP USER", dlm);
167                 dlm = " | ";
168         }
169         if (srsr & 0x00010) {
170                 if (wrsr & WRSR_SFTW) {
171                         printf("%sSOFT", dlm);
172                         dlm = " | ";
173                 }
174                 if (wrsr & WRSR_TOUT) {
175                         printf("%sWDOG", dlm);
176                         dlm = " | ";
177                 }
178         }
179         if (srsr & 0x00020) {
180                 printf("%sJTAG HIGH-Z", dlm);
181                 dlm = " | ";
182         }
183         if (srsr & 0x00040) {
184                 printf("%sJTAG SW", dlm);
185                 dlm = " | ";
186         }
187         if (srsr & 0x10000) {
188                 printf("%sWARM BOOT", dlm);
189                 dlm = " | ";
190         }
191         if (dlm[0] == '\0')
192                 printf("unknown");
193
194         printf("\n");
195 }
196
197 int read_cpu_temperature(void);
198 int check_cpu_temperature(int boot);
199
200 static void tx6qdl_print_cpuinfo(void)
201 {
202         u32 cpurev = get_cpu_rev();
203         char *cpu_str = "?";
204
205         switch ((cpurev >> 12) & 0xff) {
206         case MXC_CPU_MX6SL:
207                 cpu_str = "SL";
208                 break;
209         case MXC_CPU_MX6DL:
210                 cpu_str = "DL";
211                 break;
212         case MXC_CPU_MX6SOLO:
213                 cpu_str = "SOLO";
214                 break;
215         case MXC_CPU_MX6Q:
216                 cpu_str = "Q";
217                 break;
218         }
219
220         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
221                 cpu_str,
222                 (cpurev & 0x000F0) >> 4,
223                 (cpurev & 0x0000F) >> 0,
224                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
225
226         print_reset_cause();
227         check_cpu_temperature(1);
228 }
229
230 int board_early_init_f(void)
231 {
232         gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
233         imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
234
235         return 0;
236 }
237
238 int board_init(void)
239 {
240         int ret;
241
242         /* Address of boot parameters */
243         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
244         gd->bd->bi_arch_number = -1;
245
246         if (ctrlc()) {
247                 printf("CTRL-C detected; Skipping PMIC setup\n");
248                 return 1;
249         }
250
251         ret = setup_pmic_voltages();
252         if (ret) {
253                 printf("Failed to setup PMIC voltages\n");
254                 hang();
255         }
256         return 0;
257 }
258
259 int dram_init(void)
260 {
261         /* dram_init must store complete ramsize in gd->ram_size */
262         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
263                                 PHYS_SDRAM_1_SIZE);
264         return 0;
265 }
266
267 void dram_init_banksize(void)
268 {
269         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
270         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
271                         PHYS_SDRAM_1_SIZE);
272 #if CONFIG_NR_DRAM_BANKS > 1
273         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
274         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
275                         PHYS_SDRAM_2_SIZE);
276 #endif
277 }
278
279 #ifdef  CONFIG_CMD_MMC
280 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
281         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
282         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
283
284 static const iomux_v3_cfg_t mmc0_pads[] = {
285         MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
286         MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
287         MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
288         MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
289         MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
290         MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
291         /* SD1 CD */
292         MX6_PAD_SD3_CMD__GPIO_7_2,
293 };
294
295 static const iomux_v3_cfg_t mmc1_pads[] = {
296         MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
297         MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
298         MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
299         MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
300         MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
301         MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
302         /* SD2 CD */
303         MX6_PAD_SD3_CLK__GPIO_7_3,
304 };
305
306 #ifdef CONFIG_MMC_BOOT_SIZE
307 static const iomux_v3_cfg_t mmc3_pads[] = {
308         MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
309         MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
310         MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
311         MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
312         MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
313         MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
314         /* eMMC RESET */
315         MX6_PAD_NANDF_ALE__USDHC4_RST,
316 };
317 #endif
318
319 static struct tx6_esdhc_cfg {
320         const iomux_v3_cfg_t *pads;
321         int num_pads;
322         enum mxc_clock clkid;
323         struct fsl_esdhc_cfg cfg;
324         int cd_gpio;
325 } tx6qdl_esdhc_cfg[] = {
326 #ifdef CONFIG_MMC_BOOT_SIZE
327         {
328                 .pads = mmc3_pads,
329                 .num_pads = ARRAY_SIZE(mmc3_pads),
330                 .clkid = MXC_ESDHC4_CLK,
331                 .cfg = {
332                         .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
333                         .max_bus_width = 4,
334                 },
335                 .cd_gpio = -EINVAL,
336         },
337 #endif
338         {
339                 .pads = mmc0_pads,
340                 .num_pads = ARRAY_SIZE(mmc0_pads),
341                 .clkid = MXC_ESDHC_CLK,
342                 .cfg = {
343                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
344                         .max_bus_width = 4,
345                 },
346                 .cd_gpio = IMX_GPIO_NR(7, 2),
347         },
348         {
349                 .pads = mmc1_pads,
350                 .num_pads = ARRAY_SIZE(mmc1_pads),
351                 .clkid = MXC_ESDHC2_CLK,
352                 .cfg = {
353                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
354                         .max_bus_width = 4,
355                 },
356                 .cd_gpio = IMX_GPIO_NR(7, 3),
357         },
358 };
359
360 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
361 {
362         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
363 }
364
365 int board_mmc_getcd(struct mmc *mmc)
366 {
367         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
368
369         if (cfg->cd_gpio < 0)
370                 return 1;
371
372         debug("SD card %d is %spresent\n",
373                 cfg - tx6qdl_esdhc_cfg,
374                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
375         return !gpio_get_value(cfg->cd_gpio);
376 }
377
378 int board_mmc_init(bd_t *bis)
379 {
380         int i;
381
382         for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
383                 struct mmc *mmc;
384                 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
385                 int ret;
386
387                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
388                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
389
390                 if (cfg->cd_gpio >= 0) {
391                         ret = gpio_request_one(cfg->cd_gpio,
392                                         GPIOF_INPUT, "MMC CD");
393                         if (ret) {
394                                 printf("Error %d requesting GPIO%d_%d\n",
395                                         ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
396                                 continue;
397                         }
398                 }
399
400                 debug("%s: Initializing MMC slot %d\n", __func__, i);
401                 fsl_esdhc_initialize(bis, &cfg->cfg);
402
403                 mmc = find_mmc_device(i);
404                 if (mmc == NULL)
405                         continue;
406                 if (board_mmc_getcd(mmc))
407                         mmc_init(mmc);
408         }
409         return 0;
410 }
411 #endif /* CONFIG_CMD_MMC */
412
413 #ifdef CONFIG_FEC_MXC
414
415 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
416                         PAD_CTL_SRE_FAST)
417 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
418 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
419
420 #ifndef ETH_ALEN
421 #define ETH_ALEN 6
422 #endif
423
424 int board_eth_init(bd_t *bis)
425 {
426         int ret;
427
428         /* delay at least 21ms for the PHY internal POR signal to deassert */
429         udelay(22000);
430
431         imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads, ARRAY_SIZE(tx6qdl_fec_pads));
432
433         /* Deassert RESET to the external phy */
434         gpio_set_value(TX6_FEC_RST_GPIO, 1);
435
436         ret = cpu_eth_init(bis);
437         if (ret)
438                 printf("cpu_eth_init() failed: %d\n", ret);
439
440         return ret;
441 }
442 #endif /* CONFIG_FEC_MXC */
443
444 enum {
445         LED_STATE_INIT = -1,
446         LED_STATE_OFF,
447         LED_STATE_ON,
448 };
449
450 static inline int calc_blink_rate(int tmp)
451 {
452         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
453                 (tmp - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
454                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
455 }
456
457 void show_activity(int arg)
458 {
459         static int led_state = LED_STATE_INIT;
460         static int blink_rate;
461         static ulong last;
462
463         if (led_state == LED_STATE_INIT) {
464                 last = get_timer(0);
465                 gpio_set_value(TX6_LED_GPIO, 1);
466                 led_state = LED_STATE_ON;
467                 blink_rate = calc_blink_rate(check_cpu_temperature(0));
468         } else {
469                 if (get_timer(last) > blink_rate) {
470                         blink_rate = calc_blink_rate(check_cpu_temperature(0));
471                         last = get_timer_masked();
472                         if (led_state == LED_STATE_ON) {
473                                 gpio_set_value(TX6_LED_GPIO, 0);
474                         } else {
475                                 gpio_set_value(TX6_LED_GPIO, 1);
476                         }
477                         led_state = 1 - led_state;
478                 }
479         }
480 }
481
482 static const iomux_v3_cfg_t stk5_pads[] = {
483         /* SW controlled LED on STK5 baseboard */
484         MX6_PAD_EIM_A18__GPIO_2_20,
485
486         /* I2C bus on DIMM pins 40/41 */
487         MX6_PAD_GPIO_6__I2C3_SDA,
488         MX6_PAD_GPIO_3__I2C3_SCL,
489
490         /* TSC200x PEN IRQ */
491         MX6_PAD_EIM_D26__GPIO_3_26,
492
493         /* EDT-FT5x06 Polytouch panel */
494         MX6_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */
495         MX6_PAD_EIM_A16__GPIO_2_22, /* RESET */
496         MX6_PAD_EIM_A17__GPIO_2_21, /* WAKE */
497
498         /* USBH1 */
499         MX6_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */
500         MX6_PAD_EIM_D30__GPIO_3_30, /* OC */
501         /* USBOTG */
502         MX6_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */
503         MX6_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */
504         MX6_PAD_GPIO_8__GPIO_1_8, /* OC */
505 };
506
507 static const struct gpio stk5_gpios[] = {
508         { TX6_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
509
510         { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", },
511         { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
512         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
513         { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
514         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
515 };
516
517 #ifdef CONFIG_LCD
518 static u16 tx6_cmap[256];
519 vidinfo_t panel_info = {
520         /* set to max. size supported by SoC */
521         .vl_col = 1920,
522         .vl_row = 1080,
523
524         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
525         .cmap = tx6_cmap,
526 };
527
528 static struct fb_videomode tx6_fb_modes[] = {
529 #ifndef CONFIG_SYS_LVDS_IF
530         {
531                 /* Standard VGA timing */
532                 .name           = "VGA",
533                 .refresh        = 60,
534                 .xres           = 640,
535                 .yres           = 480,
536                 .pixclock       = KHZ2PICOS(25175),
537                 .left_margin    = 48,
538                 .hsync_len      = 96,
539                 .right_margin   = 16,
540                 .upper_margin   = 31,
541                 .vsync_len      = 2,
542                 .lower_margin   = 12,
543                 .sync           = FB_SYNC_CLK_LAT_FALL,
544         },
545         {
546                 /* Emerging ETV570 640 x 480 display. Syncs low active,
547                  * DE high active, 115.2 mm x 86.4 mm display area
548                  * VGA compatible timing
549                  */
550                 .name           = "ETV570",
551                 .refresh        = 60,
552                 .xres           = 640,
553                 .yres           = 480,
554                 .pixclock       = KHZ2PICOS(25175),
555                 .left_margin    = 114,
556                 .hsync_len      = 30,
557                 .right_margin   = 16,
558                 .upper_margin   = 32,
559                 .vsync_len      = 3,
560                 .lower_margin   = 10,
561                 .sync           = FB_SYNC_CLK_LAT_FALL,
562         },
563         {
564                 /* Emerging ET0350G0DH6 320 x 240 display.
565                  * 70.08 mm x 52.56 mm display area.
566                  */
567                 .name           = "ET0350",
568                 .refresh        = 60,
569                 .xres           = 320,
570                 .yres           = 240,
571                 .pixclock       = KHZ2PICOS(6500),
572                 .left_margin    = 68 - 34,
573                 .hsync_len      = 34,
574                 .right_margin   = 20,
575                 .upper_margin   = 18 - 3,
576                 .vsync_len      = 3,
577                 .lower_margin   = 4,
578                 .sync           = FB_SYNC_CLK_LAT_FALL,
579         },
580         {
581                 /* Emerging ET0430G0DH6 480 x 272 display.
582                  * 95.04 mm x 53.856 mm display area.
583                  */
584                 .name           = "ET0430",
585                 .refresh        = 60,
586                 .xres           = 480,
587                 .yres           = 272,
588                 .pixclock       = KHZ2PICOS(9000),
589                 .left_margin    = 2,
590                 .hsync_len      = 41,
591                 .right_margin   = 2,
592                 .upper_margin   = 2,
593                 .vsync_len      = 10,
594                 .lower_margin   = 2,
595                 .sync           = FB_SYNC_CLK_LAT_FALL,
596         },
597         {
598                 /* Emerging ET0500G0DH6 800 x 480 display.
599                  * 109.6 mm x 66.4 mm display area.
600                  */
601                 .name           = "ET0500",
602                 .refresh        = 60,
603                 .xres           = 800,
604                 .yres           = 480,
605                 .pixclock       = KHZ2PICOS(33260),
606                 .left_margin    = 216 - 128,
607                 .hsync_len      = 128,
608                 .right_margin   = 1056 - 800 - 216,
609                 .upper_margin   = 35 - 2,
610                 .vsync_len      = 2,
611                 .lower_margin   = 525 - 480 - 35,
612                 .sync           = FB_SYNC_CLK_LAT_FALL,
613         },
614         {
615                 /* Emerging ETQ570G0DH6 320 x 240 display.
616                  * 115.2 mm x 86.4 mm display area.
617                  */
618                 .name           = "ETQ570",
619                 .refresh        = 60,
620                 .xres           = 320,
621                 .yres           = 240,
622                 .pixclock       = KHZ2PICOS(6400),
623                 .left_margin    = 38,
624                 .hsync_len      = 30,
625                 .right_margin   = 30,
626                 .upper_margin   = 16, /* 15 according to datasheet */
627                 .vsync_len      = 3, /* TVP -> 1>x>5 */
628                 .lower_margin   = 4, /* 4.5 according to datasheet */
629                 .sync           = FB_SYNC_CLK_LAT_FALL,
630         },
631         {
632                 /* Emerging ET0700G0DH6 800 x 480 display.
633                  * 152.4 mm x 91.44 mm display area.
634                  */
635                 .name           = "ET0700",
636                 .refresh        = 60,
637                 .xres           = 800,
638                 .yres           = 480,
639                 .pixclock       = KHZ2PICOS(33260),
640                 .left_margin    = 216 - 128,
641                 .hsync_len      = 128,
642                 .right_margin   = 1056 - 800 - 216,
643                 .upper_margin   = 35 - 2,
644                 .vsync_len      = 2,
645                 .lower_margin   = 525 - 480 - 35,
646                 .sync           = FB_SYNC_CLK_LAT_FALL,
647         },
648         {
649                 /* Emerging ET070001DM6 800 x 480 display.
650                  * 152.4 mm x 91.44 mm display area.
651                  */
652                 .name           = "ET070001DM6",
653                 .refresh        = 60,
654                 .xres           = 800,
655                 .yres           = 480,
656                 .pixclock       = KHZ2PICOS(33260),
657                 .left_margin    = 216 - 128,
658                 .hsync_len      = 128,
659                 .right_margin   = 1056 - 800 - 216,
660                 .upper_margin   = 35 - 2,
661                 .vsync_len      = 2,
662                 .lower_margin   = 525 - 480 - 35,
663                 .sync           = 0,
664         },
665 #else
666         {
667                 /* HannStar HSD100PXN1
668                  * 202.7m mm x 152.06 mm display area.
669                  */
670                 .name           = "HSD100PXN1",
671                 .refresh        = 60,
672                 .xres           = 1024,
673                 .yres           = 768,
674                 .pixclock       = KHZ2PICOS(65000),
675                 .left_margin    = 0,
676                 .hsync_len      = 0,
677                 .right_margin   = 320,
678                 .upper_margin   = 0,
679                 .vsync_len      = 0,
680                 .lower_margin   = 38,
681                 .sync           = FB_SYNC_CLK_LAT_FALL,
682         },
683 #endif
684         {
685                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
686                 .refresh        = 60,
687                 .left_margin    = 48,
688                 .hsync_len      = 96,
689                 .right_margin   = 16,
690                 .upper_margin   = 31,
691                 .vsync_len      = 2,
692                 .lower_margin   = 12,
693                 .sync           = FB_SYNC_CLK_LAT_FALL,
694         },
695 };
696
697 static int lcd_enabled = 1;
698 static int lcd_bl_polarity;
699
700 static int lcd_backlight_polarity(void)
701 {
702         return lcd_bl_polarity;
703 }
704
705 void lcd_enable(void)
706 {
707         /* HACK ALERT:
708          * global variable from common/lcd.c
709          * Set to 0 here to prevent messages from going to LCD
710          * rather than serial console
711          */
712         lcd_is_enabled = 0;
713
714         karo_load_splashimage(1);
715
716         if (lcd_enabled) {
717                 debug("Switching LCD on\n");
718                 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
719                 udelay(100);
720                 gpio_set_value(TX6_LCD_RST_GPIO, 1);
721                 udelay(300000);
722                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
723                         lcd_backlight_polarity());
724         }
725 }
726
727 void lcd_disable(void)
728 {
729         if (lcd_enabled) {
730                 printf("Disabling LCD\n");
731                 ipuv3_fb_shutdown();
732         }
733 }
734
735 void lcd_panel_disable(void)
736 {
737         if (lcd_enabled) {
738                 debug("Switching LCD off\n");
739                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
740                         !lcd_backlight_polarity());
741                 gpio_set_value(TX6_LCD_RST_GPIO, 0);
742                 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
743         }
744 }
745
746 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
747         /* LCD RESET */
748         MX6_PAD_EIM_D29__GPIO_3_29,
749         /* LCD POWER_ENABLE */
750         MX6_PAD_EIM_EB3__GPIO_2_31,
751         /* LCD Backlight (PWM) */
752         MX6_PAD_GPIO_1__GPIO_1_1,
753
754 #ifndef CONFIG_SYS_LVDS_IF
755         /* Display */
756         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
757         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
758         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
759         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
760         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
761         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
762         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
763         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
764         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
765         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
766         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
767         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
768         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
769         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
770         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
771         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
772         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
773         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
774         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
775         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
776         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
777         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
778         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
779         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
780         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */
781         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */
782         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
783         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
784 #endif
785 };
786
787 static const struct gpio stk5_lcd_gpios[] = {
788         { TX6_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
789         { TX6_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
790         { TX6_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
791 };
792
793 void lcd_ctrl_init(void *lcdbase)
794 {
795         int color_depth = 24;
796         const char *video_mode = karo_get_vmode(getenv("video_mode"));
797         const char *vm;
798         unsigned long val;
799         int refresh = 60;
800         struct fb_videomode *p = &tx6_fb_modes[0];
801         struct fb_videomode fb_mode;
802         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
803         int pix_fmt;
804         int lcd_bus_width;
805         unsigned long di_clk_rate = 65000000;
806
807         if (!lcd_enabled) {
808                 debug("LCD disabled\n");
809                 return;
810         }
811
812         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
813                 debug("Disabling LCD\n");
814                 lcd_enabled = 0;
815                 setenv("splashimage", NULL);
816                 return;
817         }
818
819         karo_fdt_move_fdt();
820         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
821
822         if (video_mode == NULL) {
823                 debug("Disabling LCD\n");
824                 lcd_enabled = 0;
825                 return;
826         }
827         vm = video_mode;
828         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
829                 p = &fb_mode;
830                 debug("Using video mode from FDT\n");
831                 vm += strlen(vm);
832                 if (fb_mode.xres > panel_info.vl_col ||
833                         fb_mode.yres > panel_info.vl_row) {
834                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
835                                 fb_mode.xres, fb_mode.yres,
836                                 panel_info.vl_col, panel_info.vl_row);
837                         lcd_enabled = 0;
838                         return;
839                 }
840         }
841         if (p->name != NULL)
842                 debug("Trying compiled-in video modes\n");
843         while (p->name != NULL) {
844                 if (strcmp(p->name, vm) == 0) {
845                         debug("Using video mode: '%s'\n", p->name);
846                         vm += strlen(vm);
847                         break;
848                 }
849                 p++;
850         }
851         if (*vm != '\0')
852                 debug("Trying to decode video_mode: '%s'\n", vm);
853         while (*vm != '\0') {
854                 if (*vm >= '0' && *vm <= '9') {
855                         char *end;
856
857                         val = simple_strtoul(vm, &end, 0);
858                         if (end > vm) {
859                                 if (!xres_set) {
860                                         if (val > panel_info.vl_col)
861                                                 val = panel_info.vl_col;
862                                         p->xres = val;
863                                         panel_info.vl_col = val;
864                                         xres_set = 1;
865                                 } else if (!yres_set) {
866                                         if (val > panel_info.vl_row)
867                                                 val = panel_info.vl_row;
868                                         p->yres = val;
869                                         panel_info.vl_row = val;
870                                         yres_set = 1;
871                                 } else if (!bpp_set) {
872                                         switch (val) {
873                                         case 32:
874                                         case 24:
875                                                 if (is_lvds())
876                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
877                                                 /* fallthru */
878                                         case 16:
879                                         case 8:
880                                                 color_depth = val;
881                                                 break;
882
883                                         case 18:
884                                                 if (is_lvds()) {
885                                                         color_depth = val;
886                                                         break;
887                                                 }
888                                                 /* fallthru */
889                                         default:
890                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
891                                                         end - vm, vm, color_depth);
892                                         }
893                                         bpp_set = 1;
894                                 } else if (!refresh_set) {
895                                         refresh = val;
896                                         refresh_set = 1;
897                                 }
898                         }
899                         vm = end;
900                 }
901                 switch (*vm) {
902                 case '@':
903                         bpp_set = 1;
904                         /* fallthru */
905                 case '-':
906                         yres_set = 1;
907                         /* fallthru */
908                 case 'x':
909                         xres_set = 1;
910                         /* fallthru */
911                 case 'M':
912                 case 'R':
913                         vm++;
914                         break;
915
916                 default:
917                         if (*vm != '\0')
918                                 vm++;
919                 }
920         }
921         if (p->xres == 0 || p->yres == 0) {
922                 printf("Invalid video mode: %s\n", getenv("video_mode"));
923                 lcd_enabled = 0;
924                 printf("Supported video modes are:");
925                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
926                         printf(" %s", p->name);
927                 }
928                 printf("\n");
929                 return;
930         }
931         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
932                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
933                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
934                 lcd_enabled = 0;
935                 return;
936         }
937         panel_info.vl_col = p->xres;
938         panel_info.vl_row = p->yres;
939
940         switch (color_depth) {
941         case 8:
942                 panel_info.vl_bpix = LCD_COLOR8;
943                 break;
944         case 16:
945                 panel_info.vl_bpix = LCD_COLOR16;
946                 break;
947         default:
948                 panel_info.vl_bpix = LCD_COLOR24;
949         }
950
951         p->pixclock = KHZ2PICOS(refresh *
952                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
953                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
954                                 1000);
955         debug("Pixel clock set to %lu.%03lu MHz\n",
956                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
957
958         if (p != &fb_mode) {
959                 int ret;
960
961                 debug("Creating new display-timing node from '%s'\n",
962                         video_mode);
963                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
964                 if (ret)
965                         printf("Failed to create new display-timing node from '%s': %d\n",
966                                 video_mode, ret);
967         }
968
969         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
970         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
971                                         ARRAY_SIZE(stk5_lcd_pads));
972
973         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
974         switch (lcd_bus_width) {
975         case 24:
976                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
977                 break;
978
979         case 18:
980                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
981                 break;
982
983         case 16:
984                 if (!is_lvds()) {
985                         pix_fmt = IPU_PIX_FMT_RGB565;
986                         break;
987                 }
988                 /* fallthru */
989         default:
990                 lcd_enabled = 0;
991                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
992                         lcd_bus_width);
993                 return;
994         }
995         if (is_lvds()) {
996                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
997                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
998                 uint32_t gpr2;
999
1000                 if (lvds_chan_mask == 0) {
1001                         printf("No LVDS channel active\n");
1002                         lcd_enabled = 0;
1003                         return;
1004                 }
1005
1006                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1007                 if (lcd_bus_width == 24)
1008                         gpr2 |= (1 << 5) | (1 << 7);
1009                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1010                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1011                 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1012                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1013         }
1014         if (karo_load_splashimage(0) == 0) {
1015                 int ret;
1016
1017                 debug("Initializing LCD controller\n");
1018                 ret = ipuv3_fb_init(p, 0, pix_fmt, DI_PCLK_PLL3, di_clk_rate, -1);
1019                 if (ret) {
1020                         printf("Failed to initialize FB driver: %d\n", ret);
1021                         lcd_enabled = 0;
1022                 }
1023         } else {
1024                 debug("Skipping initialization of LCD controller\n");
1025         }
1026 }
1027 #else
1028 #define lcd_enabled 0
1029 #endif /* CONFIG_LCD */
1030
1031 static void stk5_board_init(void)
1032 {
1033         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1034         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1035 }
1036
1037 static void stk5v3_board_init(void)
1038 {
1039         stk5_board_init();
1040 }
1041
1042 static void stk5v5_board_init(void)
1043 {
1044         stk5_board_init();
1045
1046         gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
1047                         "Flexcan Transceiver");
1048         imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO_4_21);
1049 }
1050
1051 static void tx6qdl_set_cpu_clock(void)
1052 {
1053         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1054
1055         if (had_ctrlc() || (wrsr & WRSR_TOUT))
1056                 return;
1057
1058         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1059                 return;
1060
1061         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1062                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1063                 printf("CPU clock set to %lu.%03lu MHz\n",
1064                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1065         } else {
1066                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1067         }
1068 }
1069
1070 static void tx6_init_mac(void)
1071 {
1072         u8 mac[ETH_ALEN];
1073
1074         imx_get_mac_from_fuse(-1, mac);
1075         if (!is_valid_ether_addr(mac)) {
1076                 printf("No valid MAC address programmed\n");
1077                 return;
1078         }
1079
1080         printf("MAC addr from fuse: %pM\n", mac);
1081         eth_setenv_enetaddr("ethaddr", mac);
1082 }
1083
1084 int board_late_init(void)
1085 {
1086         int ret = 0;
1087         const char *baseboard;
1088
1089         tx6qdl_set_cpu_clock();
1090         karo_fdt_move_fdt();
1091
1092         baseboard = getenv("baseboard");
1093         if (!baseboard)
1094                 goto exit;
1095
1096         printf("Baseboard: %s\n", baseboard);
1097
1098         if (strncmp(baseboard, "stk5", 4) == 0) {
1099                 if ((strlen(baseboard) == 4) ||
1100                         strcmp(baseboard, "stk5-v3") == 0) {
1101                         stk5v3_board_init();
1102                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1103                         const char *otg_mode = getenv("otg_mode");
1104
1105                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1106                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1107                                         otg_mode, baseboard);
1108                                 setenv("otg_mode", "none");
1109                         }
1110                         stk5v5_board_init();
1111                 } else {
1112                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1113                                 baseboard + 4);
1114                 }
1115         } else {
1116                 printf("WARNING: Unsupported baseboard: '%s'\n",
1117                         baseboard);
1118                 ret = -EINVAL;
1119         }
1120
1121 exit:
1122         tx6_init_mac();
1123
1124         gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1125         clear_ctrlc();
1126         return ret;
1127 }
1128
1129 #ifdef CONFIG_TX6_V2
1130 #define TX6_FLASH_SZ    0
1131 #else
1132 #define TX6_FLASH_SZ    (2 * (CONFIG_SYS_NAND_BLOCKS / 1024 - 1))
1133 #endif
1134
1135 int checkboard(void)
1136 {
1137         u32 cpurev = get_cpu_rev();
1138         int cpu_variant = (cpurev >> 12) & 0xff;
1139
1140         tx6qdl_print_cpuinfo();
1141
1142         printf("Board: Ka-Ro TX6%c-%d%d1%d\n",
1143                 cpu_variant == MXC_CPU_MX6Q ? 'Q' : 'U',
1144                 cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
1145                 is_lvds(), 1 - PHYS_SDRAM_1_WIDTH / 64 +
1146                 TX6_FLASH_SZ);
1147
1148         return 0;
1149 }
1150
1151 #ifdef CONFIG_SERIAL_TAG
1152 void get_board_serial(struct tag_serialnr *serialnr)
1153 {
1154         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1155         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1156
1157         serialnr->low = readl(&fuse->cfg0);
1158         serialnr->high = readl(&fuse->cfg1);
1159 }
1160 #endif
1161
1162 #if defined(CONFIG_OF_BOARD_SETUP)
1163 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1164 #include <jffs2/jffs2.h>
1165 #include <mtd_node.h>
1166 static struct node_info nodes[] = {
1167         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1168 };
1169 #else
1170 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1171 #endif
1172
1173 static const char *tx6_touchpanels[] = {
1174         "ti,tsc2007",
1175         "edt,edt-ft5x06",
1176         "eeti,egalax_ts",
1177 };
1178
1179 void ft_board_setup(void *blob, bd_t *bd)
1180 {
1181         const char *baseboard = getenv("baseboard");
1182         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1183         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1184         int ret;
1185
1186         ret = fdt_increase_size(blob, 4096);
1187         if (ret)
1188                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1189
1190         if (stk5_v5)
1191                 karo_fdt_enable_node(blob, "stk5led", 0);
1192
1193         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1194         fdt_fixup_ethernet(blob);
1195
1196         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1197                                 ARRAY_SIZE(tx6_touchpanels));
1198         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1199         karo_fdt_fixup_flexcan(blob, stk5_v5);
1200
1201         karo_fdt_update_fb_mode(blob, video_mode);
1202 }
1203 #endif /* CONFIG_OF_BOARD_SETUP */