karo: tx6: add support for TX6-V2 (eMMC)
[karo-tx-uboot.git] / board / karo / tx6 / tx6qdl.c
1 /*
2  * Copyright (C) 2012,2013 Lothar WaƟmann <LW@KARO-electronics.de>
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License
9  * version 2 as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17
18 #include <common.h>
19 #include <errno.h>
20 #include <libfdt.h>
21 #include <fdt_support.h>
22 #include <lcd.h>
23 #include <netdev.h>
24 #include <mmc.h>
25 #include <fsl_esdhc.h>
26 #include <video_fb.h>
27 #include <ipu.h>
28 #include <mxcfb.h>
29 #include <i2c.h>
30 #include <linux/fb.h>
31 #include <asm/io.h>
32 #include <asm/gpio.h>
33 #include <asm/arch/mx6-pins.h>
34 #include <asm/arch/clock.h>
35 #include <asm/arch/imx-regs.h>
36 #include <asm/arch/crm_regs.h>
37 #include <asm/arch/sys_proto.h>
38
39 #include "../common/karo.h"
40
41 #define TX6_FEC_RST_GPIO                IMX_GPIO_NR(7, 6)
42 #define TX6_FEC_PWR_GPIO                IMX_GPIO_NR(3, 20)
43 #define TX6_FEC_INT_GPIO                IMX_GPIO_NR(7, 1)
44 #define TX6_LED_GPIO                    IMX_GPIO_NR(2, 20)
45
46 #define TX6_LCD_PWR_GPIO                IMX_GPIO_NR(2, 31)
47 #define TX6_LCD_RST_GPIO                IMX_GPIO_NR(3, 29)
48 #define TX6_LCD_BACKLIGHT_GPIO          IMX_GPIO_NR(1, 1)
49
50 #define TX6_RESET_OUT_GPIO              IMX_GPIO_NR(7, 12)
51
52 #define TEMPERATURE_MIN                 -40
53 #define TEMPERATURE_HOT                 80
54 #define TEMPERATURE_MAX                 125
55
56 DECLARE_GLOBAL_DATA_PTR;
57
58 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
59
60 static const iomux_v3_cfg_t tx6qdl_pads[] = {
61         /* NAND flash pads */
62         MX6_PAD_NANDF_CLE__RAWNAND_CLE,
63         MX6_PAD_NANDF_ALE__RAWNAND_ALE,
64         MX6_PAD_NANDF_WP_B__RAWNAND_RESETN,
65         MX6_PAD_NANDF_RB0__RAWNAND_READY0,
66         MX6_PAD_NANDF_CS0__RAWNAND_CE0N,
67         MX6_PAD_SD4_CMD__RAWNAND_RDN,
68         MX6_PAD_SD4_CLK__RAWNAND_WRN,
69         MX6_PAD_NANDF_D0__RAWNAND_D0,
70         MX6_PAD_NANDF_D1__RAWNAND_D1,
71         MX6_PAD_NANDF_D2__RAWNAND_D2,
72         MX6_PAD_NANDF_D3__RAWNAND_D3,
73         MX6_PAD_NANDF_D4__RAWNAND_D4,
74         MX6_PAD_NANDF_D5__RAWNAND_D5,
75         MX6_PAD_NANDF_D6__RAWNAND_D6,
76         MX6_PAD_NANDF_D7__RAWNAND_D7,
77
78         /* RESET_OUT */
79         MX6_PAD_GPIO_17__GPIO_7_12,
80
81         /* UART pads */
82 #if CONFIG_MXC_UART_BASE == UART1_BASE
83         MX6_PAD_SD3_DAT7__UART1_TXD,
84         MX6_PAD_SD3_DAT6__UART1_RXD,
85         MX6_PAD_SD3_DAT1__UART1_RTS,
86         MX6_PAD_SD3_DAT0__UART1_CTS,
87 #endif
88 #if CONFIG_MXC_UART_BASE == UART2_BASE
89         MX6_PAD_SD4_DAT4__UART2_RXD,
90         MX6_PAD_SD4_DAT7__UART2_TXD,
91         MX6_PAD_SD4_DAT5__UART2_RTS,
92         MX6_PAD_SD4_DAT6__UART2_CTS,
93 #endif
94 #if CONFIG_MXC_UART_BASE == UART3_BASE
95         MX6_PAD_EIM_D24__UART3_TXD,
96         MX6_PAD_EIM_D25__UART3_RXD,
97         MX6_PAD_SD3_RST__UART3_RTS,
98         MX6_PAD_SD3_DAT3__UART3_CTS,
99 #endif
100         /* internal I2C */
101         MX6_PAD_EIM_D28__I2C1_SDA,
102         MX6_PAD_EIM_D21__I2C1_SCL,
103
104         /* FEC PHY GPIO functions */
105         MX6_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */
106         MX6_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */
107         MX6_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */
108 };
109
110 static const iomux_v3_cfg_t tx6qdl_fec_pads[] = {
111         /* FEC functions */
112         MX6_PAD_ENET_MDC__ENET_MDC,
113         MX6_PAD_ENET_MDIO__ENET_MDIO,
114         MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
115         MX6_PAD_ENET_RX_ER__ENET_RX_ER,
116         MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
117         MX6_PAD_ENET_RXD1__ENET_RDATA_1,
118         MX6_PAD_ENET_RXD0__ENET_RDATA_0,
119         MX6_PAD_ENET_TX_EN__ENET_TX_EN,
120         MX6_PAD_ENET_TXD1__ENET_TDATA_1,
121         MX6_PAD_ENET_TXD0__ENET_TDATA_0,
122 };
123
124 static const struct gpio tx6qdl_gpios[] = {
125         { TX6_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
126         { TX6_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
127         { TX6_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
128         { TX6_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
129 };
130
131 /*
132  * Functions
133  */
134 /* placed in section '.data' to prevent overwriting relocation info
135  * overlayed with bss
136  */
137 static u32 wrsr __attribute__((section(".data")));
138
139 #define WRSR_POR                        (1 << 4)
140 #define WRSR_TOUT                       (1 << 1)
141 #define WRSR_SFTW                       (1 << 0)
142
143 static void print_reset_cause(void)
144 {
145         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
146         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
147         u32 srsr;
148         char *dlm = "";
149
150         printf("Reset cause: ");
151
152         srsr = readl(&src_regs->srsr);
153         wrsr = readw(wdt_base + 4);
154
155         if (wrsr & WRSR_POR) {
156                 printf("%sPOR", dlm);
157                 dlm = " | ";
158         }
159         if (srsr & 0x00004) {
160                 printf("%sCSU", dlm);
161                 dlm = " | ";
162         }
163         if (srsr & 0x00008) {
164                 printf("%sIPP USER", dlm);
165                 dlm = " | ";
166         }
167         if (srsr & 0x00010) {
168                 if (wrsr & WRSR_SFTW) {
169                         printf("%sSOFT", dlm);
170                         dlm = " | ";
171                 }
172                 if (wrsr & WRSR_TOUT) {
173                         printf("%sWDOG", dlm);
174                         dlm = " | ";
175                 }
176         }
177         if (srsr & 0x00020) {
178                 printf("%sJTAG HIGH-Z", dlm);
179                 dlm = " | ";
180         }
181         if (srsr & 0x00040) {
182                 printf("%sJTAG SW", dlm);
183                 dlm = " | ";
184         }
185         if (srsr & 0x10000) {
186                 printf("%sWARM BOOT", dlm);
187                 dlm = " | ";
188         }
189         if (dlm[0] == '\0')
190                 printf("unknown");
191
192         printf("\n");
193 }
194
195 int read_cpu_temperature(void);
196 int check_cpu_temperature(int boot);
197
198 static void tx6qdl_print_cpuinfo(void)
199 {
200         u32 cpurev = get_cpu_rev();
201         char *cpu_str = "?";
202
203         switch ((cpurev >> 12) & 0xff) {
204         case MXC_CPU_MX6SL:
205                 cpu_str = "SL";
206                 break;
207         case MXC_CPU_MX6DL:
208                 cpu_str = "DL";
209                 break;
210         case MXC_CPU_MX6SOLO:
211                 cpu_str = "SOLO";
212                 break;
213         case MXC_CPU_MX6Q:
214                 cpu_str = "Q";
215                 break;
216         }
217
218         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
219                 cpu_str,
220                 (cpurev & 0x000F0) >> 4,
221                 (cpurev & 0x0000F) >> 0,
222                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
223
224         print_reset_cause();
225         check_cpu_temperature(1);
226 }
227
228 #define LTC3676_BUCK1           0x01
229 #define LTC3676_BUCK2           0x02
230 #define LTC3676_BUCK3           0x03
231 #define LTC3676_BUCK4           0x04
232 #define LTC3676_DVB1A           0x0A
233 #define LTC3676_DVB1B           0x0B
234 #define LTC3676_DVB2A           0x0C
235 #define LTC3676_DVB2B           0x0D
236 #define LTC3676_DVB3A           0x0E
237 #define LTC3676_DVB3B           0x0F
238 #define LTC3676_DVB4A           0x10
239 #define LTC3676_DVB4B           0x11
240 #define LTC3676_MSKPG           0x13
241 #define LTC3676_CLIRQ           0x1f
242
243 #define LTC3676_BUCK_DVDT_FAST  (1 << 0)
244 #define LTC3676_BUCK_KEEP_ALIVE (1 << 1)
245 #define LTC3676_BUCK_CLK_RATE_LOW (1 << 2)
246 #define LTC3676_BUCK_PHASE_SEL  (1 << 3)
247 #define LTC3676_BUCK_ENABLE_300 (1 << 4)
248 #define LTC3676_BUCK_PULSE_SKIP (0 << 5)
249 #define LTC3676_BUCK_BURST_MODE (1 << 5)
250 #define LTC3676_BUCK_CONTINUOUS (2 << 5)
251 #define LTC3676_BUCK_ENABLE     (1 << 7)
252
253 #define LTC3676_PGOOD_MASK      (1 << 5)
254
255 #define LTC3676_MSKPG_BUCK1     (1 << 0)
256 #define LTC3676_MSKPG_BUCK2     (1 << 1)
257 #define LTC3676_MSKPG_BUCK3     (1 << 2)
258 #define LTC3676_MSKPG_BUCK4     (1 << 3)
259 #define LTC3676_MSKPG_LDO2      (1 << 5)
260 #define LTC3676_MSKPG_LDO3      (1 << 6)
261 #define LTC3676_MSKPG_LDO4      (1 << 7)
262
263 #define VDD_IO_VAL              mV_to_regval(vout_to_vref(3300 * 10, 5))
264 #define VDD_IO_VAL_LP           mV_to_regval(vout_to_vref(3100 * 10, 5))
265 #define VDD_IO_VAL_2            mV_to_regval(vout_to_vref(3300 * 10, 5_2))
266 #define VDD_IO_VAL_2_LP         mV_to_regval(vout_to_vref(3100 * 10, 5_2))
267 #define VDD_SOC_VAL             mV_to_regval(vout_to_vref(1425 * 10, 6))
268 #define VDD_SOC_VAL_LP          mV_to_regval(vout_to_vref(900 * 10, 6))
269 #define VDD_DDR_VAL             mV_to_regval(vout_to_vref(1500 * 10, 7))
270 #define VDD_CORE_VAL            mV_to_regval(vout_to_vref(1425 * 10, 8))
271 #define VDD_CORE_VAL_LP         mV_to_regval(vout_to_vref(900 * 10, 8))
272
273 /* LDO1 */
274 #define R1_1                    470
275 #define R2_1                    150
276 /* LDO4 */
277 #define R1_4                    470
278 #define R2_4                    150
279 /* Buck1 */
280 #define R1_5                    390
281 #define R2_5                    110
282 #define R1_5_2                  470
283 #define R2_5_2                  150
284 /* Buck2 */
285 #define R1_6                    150
286 #define R2_6                    180
287 /* Buck3 */
288 #define R1_7                    150
289 #define R2_7                    140
290 /* Buck4 */
291 #define R1_8                    150
292 #define R2_8                    180
293
294 /* calculate voltages in 10mV */
295 #define R1(idx)                 R1_##idx
296 #define R2(idx)                 R2_##idx
297
298 #define vout_to_vref(vout, idx) ((vout) * R2(idx) / (R1(idx) + R2(idx)))
299 #define vref_to_vout(vref, idx) DIV_ROUND_UP((vref) * (R1(idx) + R2(idx)), R2(idx))
300
301 #define mV_to_regval(mV)        DIV_ROUND(((((mV) < 4125) ? 4125 : (mV)) - 4125), 125)
302 #define regval_to_mV(v)         (((v) * 125 + 4125))
303
304 static struct ltc3673_regs {
305         u8 addr;
306         u8 val;
307         u8 mask;
308 } ltc3676_regs[] = {
309         { LTC3676_MSKPG, ~LTC3676_MSKPG_BUCK1, },
310         { LTC3676_DVB2B, VDD_SOC_VAL | LTC3676_PGOOD_MASK, ~0x3f, },
311         { LTC3676_DVB3B, VDD_DDR_VAL, ~0x3f, },
312         { LTC3676_DVB4B, VDD_CORE_VAL | LTC3676_PGOOD_MASK, ~0x3f, },
313         { LTC3676_DVB2A, VDD_SOC_VAL, ~0x3f, },
314         { LTC3676_DVB3A, VDD_DDR_VAL, ~0x3f, },
315         { LTC3676_DVB4A, VDD_CORE_VAL, ~0x3f, },
316         { LTC3676_BUCK1, LTC3676_BUCK_BURST_MODE | LTC3676_BUCK_CLK_RATE_LOW, },
317         { LTC3676_BUCK2, LTC3676_BUCK_BURST_MODE, },
318         { LTC3676_BUCK3, LTC3676_BUCK_BURST_MODE, },
319         { LTC3676_BUCK4, LTC3676_BUCK_BURST_MODE, },
320         { LTC3676_CLIRQ, 0, }, /* clear interrupt status */
321 };
322
323 static struct ltc3673_regs ltc3676_regs_1[] = {
324         { LTC3676_DVB1B, VDD_IO_VAL_LP | LTC3676_PGOOD_MASK, ~0x3f, },
325         { LTC3676_DVB1A, VDD_IO_VAL, ~0x3f, },
326 };
327
328 static struct ltc3673_regs ltc3676_regs_2[] = {
329         { LTC3676_DVB1B, VDD_IO_VAL_2_LP | LTC3676_PGOOD_MASK, ~0x3f, },
330         { LTC3676_DVB1A, VDD_IO_VAL_2, ~0x3f, },
331 };
332
333 static int tx6_rev_2(void)
334 {
335         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
336         struct fuse_bank5_regs *fuse = (void *)ocotp->bank[5].fuse_regs;
337         u32 pad_settings = readl(&fuse->pad_settings);
338
339         debug("Fuse pad_settings @ %p = %02x\n",
340                 &fuse->pad_settings, pad_settings);
341         return pad_settings & 1;
342 }
343
344 static int tx6_ltc3676_setup_regs(struct ltc3673_regs *r, size_t count)
345 {
346         int ret;
347         int i;
348
349         for (i = 0; i < count; i++, r++) {
350 #ifdef DEBUG
351                 unsigned char value;
352
353                 ret = i2c_read(CONFIG_SYS_I2C_SLAVE, r->addr, 1, &value, 1);
354                 if ((value & ~r->mask) != r->val) {
355                         printf("Changing PMIC reg %02x from %02x to %02x\n",
356                                 r->addr, value, r->val);
357                 }
358                 if (ret) {
359                         printf("%s: failed to read PMIC register %02x: %d\n",
360                                 __func__, r->addr, ret);
361                         return ret;
362                 }
363 #endif
364                 ret = i2c_write(CONFIG_SYS_I2C_SLAVE,
365                                 r->addr, 1, &r->val, 1);
366                 if (ret) {
367                         printf("%s: failed to write PMIC register %02x: %d\n",
368                                 __func__, r->addr, ret);
369                         return ret;
370                 }
371         }
372         return 0;
373 }
374
375 static int setup_pmic_voltages(void)
376 {
377         int ret;
378         unsigned char value;
379
380         ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
381         if (ret != 0) {
382                 printf("Failed to initialize I2C\n");
383                 return ret;
384         }
385
386         ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
387         if (ret) {
388                 printf("%s: i2c_read error: %d\n", __func__, ret);
389                 return ret;
390         }
391
392         ret = tx6_ltc3676_setup_regs(ltc3676_regs, ARRAY_SIZE(ltc3676_regs));
393         if (ret)
394                 return ret;
395
396         printf("VDDCORE set to %umV\n",
397                 DIV_ROUND(vref_to_vout(regval_to_mV(VDD_CORE_VAL), 8), 10));
398         printf("VDDSOC  set to %umV\n",
399                 DIV_ROUND(vref_to_vout(regval_to_mV(VDD_SOC_VAL), 6), 10));
400
401         if (tx6_rev_2()) {
402                 ret = tx6_ltc3676_setup_regs(ltc3676_regs_2,
403                                 ARRAY_SIZE(ltc3676_regs_2));
404                 printf("VDDIO   set to %umV\n",
405                         DIV_ROUND(vref_to_vout(
406                                         regval_to_mV(VDD_IO_VAL_2), 5_2), 10));
407         } else {
408                 ret = tx6_ltc3676_setup_regs(ltc3676_regs_1,
409                                 ARRAY_SIZE(ltc3676_regs_1));
410         }
411         return ret;
412 }
413
414 int board_early_init_f(void)
415 {
416         gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
417         imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
418
419         return 0;
420 }
421
422 int board_init(void)
423 {
424         int ret;
425
426         /* Address of boot parameters */
427         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
428         gd->bd->bi_arch_number = -1;
429
430         if (ctrlc()) {
431                 printf("CTRL-C detected; Skipping PMIC setup\n");
432                 return 1;
433         }
434
435         ret = setup_pmic_voltages();
436         if (ret) {
437                 printf("Failed to setup PMIC voltages\n");
438                 hang();
439         }
440         return 0;
441 }
442
443 int dram_init(void)
444 {
445         /* dram_init must store complete ramsize in gd->ram_size */
446         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
447                                 PHYS_SDRAM_1_SIZE);
448         return 0;
449 }
450
451 void dram_init_banksize(void)
452 {
453         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
454         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
455                         PHYS_SDRAM_1_SIZE);
456 #if CONFIG_NR_DRAM_BANKS > 1
457         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
458         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
459                         PHYS_SDRAM_2_SIZE);
460 #endif
461 }
462
463 #ifdef  CONFIG_CMD_MMC
464 static const iomux_v3_cfg_t mmc0_pads[] = {
465         MX6_PAD_SD1_CMD__USDHC1_CMD,
466         MX6_PAD_SD1_CLK__USDHC1_CLK,
467         MX6_PAD_SD1_DAT0__USDHC1_DAT0,
468         MX6_PAD_SD1_DAT1__USDHC1_DAT1,
469         MX6_PAD_SD1_DAT2__USDHC1_DAT2,
470         MX6_PAD_SD1_DAT3__USDHC1_DAT3,
471         /* SD1 CD */
472         MX6_PAD_SD3_CMD__GPIO_7_2,
473 };
474
475 static const iomux_v3_cfg_t mmc1_pads[] = {
476         MX6_PAD_SD2_CMD__USDHC2_CMD,
477         MX6_PAD_SD2_CLK__USDHC2_CLK,
478         MX6_PAD_SD2_DAT0__USDHC2_DAT0,
479         MX6_PAD_SD2_DAT1__USDHC2_DAT1,
480         MX6_PAD_SD2_DAT2__USDHC2_DAT2,
481         MX6_PAD_SD2_DAT3__USDHC2_DAT3,
482         /* SD2 CD */
483         MX6_PAD_SD3_CLK__GPIO_7_3,
484 };
485
486 static struct tx6_esdhc_cfg {
487         const iomux_v3_cfg_t *pads;
488         int num_pads;
489         enum mxc_clock clkid;
490         struct fsl_esdhc_cfg cfg;
491         int cd_gpio;
492 } tx6qdl_esdhc_cfg[] = {
493         {
494                 .pads = mmc0_pads,
495                 .num_pads = ARRAY_SIZE(mmc0_pads),
496                 .clkid = MXC_ESDHC_CLK,
497                 .cfg = {
498                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
499                         .max_bus_width = 4,
500                 },
501                 .cd_gpio = IMX_GPIO_NR(7, 2),
502         },
503         {
504                 .pads = mmc1_pads,
505                 .num_pads = ARRAY_SIZE(mmc1_pads),
506                 .clkid = MXC_ESDHC2_CLK,
507                 .cfg = {
508                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
509                         .max_bus_width = 4,
510                 },
511                 .cd_gpio = IMX_GPIO_NR(7, 3),
512         },
513 };
514
515 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
516 {
517         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
518 }
519
520 int board_mmc_getcd(struct mmc *mmc)
521 {
522         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
523
524         if (cfg->cd_gpio < 0)
525                 return cfg->cd_gpio;
526
527         debug("SD card %d is %spresent\n",
528                 cfg - tx6qdl_esdhc_cfg,
529                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
530         return !gpio_get_value(cfg->cd_gpio);
531 }
532
533 int board_mmc_init(bd_t *bis)
534 {
535         int i;
536
537         for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
538                 struct mmc *mmc;
539                 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
540                 int ret;
541
542                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
543                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
544
545                 ret = gpio_request_one(cfg->cd_gpio,
546                                 GPIOF_INPUT, "MMC CD");
547                 if (ret) {
548                         printf("Error %d requesting GPIO%d_%d\n",
549                                 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
550                         continue;
551                 }
552
553                 debug("%s: Initializing MMC slot %d\n", __func__, i);
554                 fsl_esdhc_initialize(bis, &cfg->cfg);
555
556                 mmc = find_mmc_device(i);
557                 if (mmc == NULL)
558                         continue;
559                 if (board_mmc_getcd(mmc) > 0)
560                         mmc_init(mmc);
561         }
562         return 0;
563 }
564 #endif /* CONFIG_CMD_MMC */
565
566 #ifdef CONFIG_FEC_MXC
567
568 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
569                         PAD_CTL_SRE_FAST)
570 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
571 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
572
573 #ifndef ETH_ALEN
574 #define ETH_ALEN 6
575 #endif
576
577 int board_eth_init(bd_t *bis)
578 {
579         int ret;
580
581         /* delay at least 21ms for the PHY internal POR signal to deassert */
582         udelay(22000);
583
584         imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads, ARRAY_SIZE(tx6qdl_fec_pads));
585
586         /* Deassert RESET to the external phy */
587         gpio_set_value(TX6_FEC_RST_GPIO, 1);
588
589         ret = cpu_eth_init(bis);
590         if (ret)
591                 printf("cpu_eth_init() failed: %d\n", ret);
592
593         return ret;
594 }
595 #endif /* CONFIG_FEC_MXC */
596
597 enum {
598         LED_STATE_INIT = -1,
599         LED_STATE_OFF,
600         LED_STATE_ON,
601 };
602
603 static inline int calc_blink_rate(int tmp)
604 {
605         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
606                 (tmp - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
607                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
608 }
609
610 void show_activity(int arg)
611 {
612         static int led_state = LED_STATE_INIT;
613         static int blink_rate;
614         static ulong last;
615
616         if (led_state == LED_STATE_INIT) {
617                 last = get_timer(0);
618                 gpio_set_value(TX6_LED_GPIO, 1);
619                 led_state = LED_STATE_ON;
620                 blink_rate = calc_blink_rate(check_cpu_temperature(0));
621         } else {
622                 if (get_timer(last) > blink_rate) {
623                         blink_rate = calc_blink_rate(check_cpu_temperature(0));
624                         last = get_timer_masked();
625                         if (led_state == LED_STATE_ON) {
626                                 gpio_set_value(TX6_LED_GPIO, 0);
627                         } else {
628                                 gpio_set_value(TX6_LED_GPIO, 1);
629                         }
630                         led_state = 1 - led_state;
631                 }
632         }
633 }
634
635 static const iomux_v3_cfg_t stk5_pads[] = {
636         /* SW controlled LED on STK5 baseboard */
637         MX6_PAD_EIM_A18__GPIO_2_20,
638
639         /* LCD data pins */
640         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
641         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
642         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
643         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
644         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
645         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
646         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
647         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
648         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
649         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
650         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
651         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
652         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
653         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
654         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
655         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
656         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
657         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
658         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
659         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
660         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
661         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
662         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
663         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
664         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */
665         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */
666         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
667         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
668
669         /* I2C bus on DIMM pins 40/41 */
670         MX6_PAD_GPIO_6__I2C3_SDA,
671         MX6_PAD_GPIO_3__I2C3_SCL,
672
673         /* TSC200x PEN IRQ */
674         MX6_PAD_EIM_D26__GPIO_3_26,
675
676         /* EDT-FT5x06 Polytouch panel */
677         MX6_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */
678         MX6_PAD_EIM_A16__GPIO_2_22, /* RESET */
679         MX6_PAD_EIM_A17__GPIO_2_21, /* WAKE */
680
681         /* USBH1 */
682         MX6_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */
683         MX6_PAD_EIM_D30__GPIO_3_30, /* OC */
684         /* USBOTG */
685         MX6_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */
686         MX6_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */
687         MX6_PAD_GPIO_8__GPIO_1_8, /* OC */
688 };
689
690 static const struct gpio stk5_gpios[] = {
691         { TX6_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
692
693         { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", },
694         { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
695         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
696         { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
697         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
698 };
699
700 #ifdef CONFIG_LCD
701 static u16 tx6_cmap[256];
702 vidinfo_t panel_info = {
703         /* set to max. size supported by SoC */
704         .vl_col = 1920,
705         .vl_row = 1080,
706
707         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
708         .cmap = tx6_cmap,
709 };
710
711 static struct fb_videomode tx6_fb_modes[] = {
712 #ifndef CONFIG_SYS_LVDS_IF
713         {
714                 /* Standard VGA timing */
715                 .name           = "VGA",
716                 .refresh        = 60,
717                 .xres           = 640,
718                 .yres           = 480,
719                 .pixclock       = KHZ2PICOS(25175),
720                 .left_margin    = 48,
721                 .hsync_len      = 96,
722                 .right_margin   = 16,
723                 .upper_margin   = 31,
724                 .vsync_len      = 2,
725                 .lower_margin   = 12,
726                 .sync           = FB_SYNC_CLK_LAT_FALL,
727         },
728         {
729                 /* Emerging ETV570 640 x 480 display. Syncs low active,
730                  * DE high active, 115.2 mm x 86.4 mm display area
731                  * VGA compatible timing
732                  */
733                 .name           = "ETV570",
734                 .refresh        = 60,
735                 .xres           = 640,
736                 .yres           = 480,
737                 .pixclock       = KHZ2PICOS(25175),
738                 .left_margin    = 114,
739                 .hsync_len      = 30,
740                 .right_margin   = 16,
741                 .upper_margin   = 32,
742                 .vsync_len      = 3,
743                 .lower_margin   = 10,
744                 .sync           = FB_SYNC_CLK_LAT_FALL,
745         },
746         {
747                 /* Emerging ET0350G0DH6 320 x 240 display.
748                  * 70.08 mm x 52.56 mm display area.
749                  */
750                 .name           = "ET0350",
751                 .refresh        = 60,
752                 .xres           = 320,
753                 .yres           = 240,
754                 .pixclock       = KHZ2PICOS(6500),
755                 .left_margin    = 68 - 34,
756                 .hsync_len      = 34,
757                 .right_margin   = 20,
758                 .upper_margin   = 18 - 3,
759                 .vsync_len      = 3,
760                 .lower_margin   = 4,
761                 .sync           = FB_SYNC_CLK_LAT_FALL,
762         },
763         {
764                 /* Emerging ET0430G0DH6 480 x 272 display.
765                  * 95.04 mm x 53.856 mm display area.
766                  */
767                 .name           = "ET0430",
768                 .refresh        = 60,
769                 .xres           = 480,
770                 .yres           = 272,
771                 .pixclock       = KHZ2PICOS(9000),
772                 .left_margin    = 2,
773                 .hsync_len      = 41,
774                 .right_margin   = 2,
775                 .upper_margin   = 2,
776                 .vsync_len      = 10,
777                 .lower_margin   = 2,
778                 .sync           = FB_SYNC_CLK_LAT_FALL,
779         },
780         {
781                 /* Emerging ET0500G0DH6 800 x 480 display.
782                  * 109.6 mm x 66.4 mm display area.
783                  */
784                 .name           = "ET0500",
785                 .refresh        = 60,
786                 .xres           = 800,
787                 .yres           = 480,
788                 .pixclock       = KHZ2PICOS(33260),
789                 .left_margin    = 216 - 128,
790                 .hsync_len      = 128,
791                 .right_margin   = 1056 - 800 - 216,
792                 .upper_margin   = 35 - 2,
793                 .vsync_len      = 2,
794                 .lower_margin   = 525 - 480 - 35,
795                 .sync           = FB_SYNC_CLK_LAT_FALL,
796         },
797         {
798                 /* Emerging ETQ570G0DH6 320 x 240 display.
799                  * 115.2 mm x 86.4 mm display area.
800                  */
801                 .name           = "ETQ570",
802                 .refresh        = 60,
803                 .xres           = 320,
804                 .yres           = 240,
805                 .pixclock       = KHZ2PICOS(6400),
806                 .left_margin    = 38,
807                 .hsync_len      = 30,
808                 .right_margin   = 30,
809                 .upper_margin   = 16, /* 15 according to datasheet */
810                 .vsync_len      = 3, /* TVP -> 1>x>5 */
811                 .lower_margin   = 4, /* 4.5 according to datasheet */
812                 .sync           = FB_SYNC_CLK_LAT_FALL,
813         },
814         {
815                 /* Emerging ET0700G0DH6 800 x 480 display.
816                  * 152.4 mm x 91.44 mm display area.
817                  */
818                 .name           = "ET0700",
819                 .refresh        = 60,
820                 .xres           = 800,
821                 .yres           = 480,
822                 .pixclock       = KHZ2PICOS(33260),
823                 .left_margin    = 216 - 128,
824                 .hsync_len      = 128,
825                 .right_margin   = 1056 - 800 - 216,
826                 .upper_margin   = 35 - 2,
827                 .vsync_len      = 2,
828                 .lower_margin   = 525 - 480 - 35,
829                 .sync           = FB_SYNC_CLK_LAT_FALL,
830         },
831         {
832                 /* Emerging ET070001DM6 800 x 480 display.
833                  * 152.4 mm x 91.44 mm display area.
834                  */
835                 .name           = "ET070001DM6",
836                 .refresh        = 60,
837                 .xres           = 800,
838                 .yres           = 480,
839                 .pixclock       = KHZ2PICOS(33260),
840                 .left_margin    = 216 - 128,
841                 .hsync_len      = 128,
842                 .right_margin   = 1056 - 800 - 216,
843                 .upper_margin   = 35 - 2,
844                 .vsync_len      = 2,
845                 .lower_margin   = 525 - 480 - 35,
846                 .sync           = 0,
847         },
848 #else
849         {
850                 /* HannStar HSD100PXN1
851                  * 202.7m mm x 152.06 mm display area.
852                  */
853                 .name           = "HSD100PXN1",
854                 .refresh        = 60,
855                 .xres           = 1024,
856                 .yres           = 768,
857                 .pixclock       = KHZ2PICOS(65000),
858                 .left_margin    = 0,
859                 .hsync_len      = 0,
860                 .right_margin   = 320,
861                 .upper_margin   = 0,
862                 .vsync_len      = 0,
863                 .lower_margin   = 38,
864                 .sync           = FB_SYNC_CLK_LAT_FALL,
865         },
866 #endif
867         {
868                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
869                 .refresh        = 60,
870                 .left_margin    = 48,
871                 .hsync_len      = 96,
872                 .right_margin   = 16,
873                 .upper_margin   = 31,
874                 .vsync_len      = 2,
875                 .lower_margin   = 12,
876                 .sync           = FB_SYNC_CLK_LAT_FALL,
877         },
878 };
879
880 static int lcd_enabled = 1;
881 static int lcd_bl_polarity;
882
883 static int lcd_backlight_polarity(void)
884 {
885         return lcd_bl_polarity;
886 }
887
888 void lcd_enable(void)
889 {
890         /* HACK ALERT:
891          * global variable from common/lcd.c
892          * Set to 0 here to prevent messages from going to LCD
893          * rather than serial console
894          */
895         lcd_is_enabled = 0;
896
897         karo_load_splashimage(1);
898
899         if (lcd_enabled) {
900                 debug("Switching LCD on\n");
901                 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
902                 udelay(100);
903                 gpio_set_value(TX6_LCD_RST_GPIO, 1);
904                 udelay(300000);
905                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
906                         lcd_backlight_polarity());
907         }
908 }
909
910 void lcd_disable(void)
911 {
912         if (lcd_enabled) {
913                 printf("Disabling LCD\n");
914                 ipuv3_fb_shutdown();
915         }
916 }
917
918 void lcd_panel_disable(void)
919 {
920         if (lcd_enabled) {
921                 debug("Switching LCD off\n");
922                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
923                         !lcd_backlight_polarity());
924                 gpio_set_value(TX6_LCD_RST_GPIO, 0);
925                 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
926         }
927 }
928
929 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
930         /* LCD RESET */
931         MX6_PAD_EIM_D29__GPIO_3_29,
932         /* LCD POWER_ENABLE */
933         MX6_PAD_EIM_EB3__GPIO_2_31,
934         /* LCD Backlight (PWM) */
935         MX6_PAD_GPIO_1__GPIO_1_1,
936
937         /* Display */
938         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
939         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
940         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
941         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
942         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
943         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
944         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
945         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
946         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
947         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
948         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
949         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
950         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
951         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
952         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
953         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
954         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
955         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
956         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
957         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
958         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
959         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
960         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
961         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
962         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
963         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
964         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
965         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
966 };
967
968 static const struct gpio stk5_lcd_gpios[] = {
969         { TX6_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
970         { TX6_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
971         { TX6_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
972 };
973
974 void lcd_ctrl_init(void *lcdbase)
975 {
976         int color_depth = 24;
977         const char *video_mode = karo_get_vmode(getenv("video_mode"));
978         const char *vm;
979         unsigned long val;
980         int refresh = 60;
981         struct fb_videomode *p = &tx6_fb_modes[0];
982         struct fb_videomode fb_mode;
983         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
984         int pix_fmt;
985         int lcd_bus_width;
986         unsigned long di_clk_rate = 65000000;
987
988         if (!lcd_enabled) {
989                 debug("LCD disabled\n");
990                 return;
991         }
992
993         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
994                 debug("Disabling LCD\n");
995                 lcd_enabled = 0;
996                 setenv("splashimage", NULL);
997                 return;
998         }
999
1000         karo_fdt_move_fdt();
1001         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1002
1003         if (video_mode == NULL) {
1004                 debug("Disabling LCD\n");
1005                 lcd_enabled = 0;
1006                 return;
1007         }
1008         vm = video_mode;
1009         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1010                 p = &fb_mode;
1011                 debug("Using video mode from FDT\n");
1012                 vm += strlen(vm);
1013                 if (fb_mode.xres > panel_info.vl_col ||
1014                         fb_mode.yres > panel_info.vl_row) {
1015                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1016                                 fb_mode.xres, fb_mode.yres,
1017                                 panel_info.vl_col, panel_info.vl_row);
1018                         lcd_enabled = 0;
1019                         return;
1020                 }
1021         }
1022         if (p->name != NULL)
1023                 debug("Trying compiled-in video modes\n");
1024         while (p->name != NULL) {
1025                 if (strcmp(p->name, vm) == 0) {
1026                         debug("Using video mode: '%s'\n", p->name);
1027                         vm += strlen(vm);
1028                         break;
1029                 }
1030                 p++;
1031         }
1032         if (*vm != '\0')
1033                 debug("Trying to decode video_mode: '%s'\n", vm);
1034         while (*vm != '\0') {
1035                 if (*vm >= '0' && *vm <= '9') {
1036                         char *end;
1037
1038                         val = simple_strtoul(vm, &end, 0);
1039                         if (end > vm) {
1040                                 if (!xres_set) {
1041                                         if (val > panel_info.vl_col)
1042                                                 val = panel_info.vl_col;
1043                                         p->xres = val;
1044                                         panel_info.vl_col = val;
1045                                         xres_set = 1;
1046                                 } else if (!yres_set) {
1047                                         if (val > panel_info.vl_row)
1048                                                 val = panel_info.vl_row;
1049                                         p->yres = val;
1050                                         panel_info.vl_row = val;
1051                                         yres_set = 1;
1052                                 } else if (!bpp_set) {
1053                                         switch (val) {
1054                                         case 32:
1055                                         case 24:
1056                                                 if (is_lvds())
1057                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
1058                                                 /* fallthru */
1059                                         case 16:
1060                                         case 8:
1061                                                 color_depth = val;
1062                                                 break;
1063
1064                                         case 18:
1065                                                 if (is_lvds()) {
1066                                                         color_depth = val;
1067                                                         break;
1068                                                 }
1069                                                 /* fallthru */
1070                                         default:
1071                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1072                                                         end - vm, vm, color_depth);
1073                                         }
1074                                         bpp_set = 1;
1075                                 } else if (!refresh_set) {
1076                                         refresh = val;
1077                                         refresh_set = 1;
1078                                 }
1079                         }
1080                         vm = end;
1081                 }
1082                 switch (*vm) {
1083                 case '@':
1084                         bpp_set = 1;
1085                         /* fallthru */
1086                 case '-':
1087                         yres_set = 1;
1088                         /* fallthru */
1089                 case 'x':
1090                         xres_set = 1;
1091                         /* fallthru */
1092                 case 'M':
1093                 case 'R':
1094                         vm++;
1095                         break;
1096
1097                 default:
1098                         if (*vm != '\0')
1099                                 vm++;
1100                 }
1101         }
1102         if (p->xres == 0 || p->yres == 0) {
1103                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1104                 lcd_enabled = 0;
1105                 printf("Supported video modes are:");
1106                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1107                         printf(" %s", p->name);
1108                 }
1109                 printf("\n");
1110                 return;
1111         }
1112         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1113                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1114                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1115                 lcd_enabled = 0;
1116                 return;
1117         }
1118         panel_info.vl_col = p->xres;
1119         panel_info.vl_row = p->yres;
1120
1121         switch (color_depth) {
1122         case 8:
1123                 panel_info.vl_bpix = LCD_COLOR8;
1124                 break;
1125         case 16:
1126                 panel_info.vl_bpix = LCD_COLOR16;
1127                 break;
1128         default:
1129                 panel_info.vl_bpix = LCD_COLOR24;
1130         }
1131
1132         p->pixclock = KHZ2PICOS(refresh *
1133                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1134                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1135                                 1000);
1136         debug("Pixel clock set to %lu.%03lu MHz\n",
1137                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1138
1139         if (p != &fb_mode) {
1140                 int ret;
1141
1142                 debug("Creating new display-timing node from '%s'\n",
1143                         video_mode);
1144                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1145                 if (ret)
1146                         printf("Failed to create new display-timing node from '%s': %d\n",
1147                                 video_mode, ret);
1148         }
1149
1150         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1151         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1152                                         ARRAY_SIZE(stk5_lcd_pads));
1153
1154         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1155         switch (lcd_bus_width) {
1156         case 24:
1157                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1158                 break;
1159
1160         case 18:
1161                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1162                 break;
1163
1164         case 16:
1165                 if (!is_lvds()) {
1166                         pix_fmt = IPU_PIX_FMT_RGB565;
1167                         break;
1168                 }
1169                 /* fallthru */
1170         default:
1171                 lcd_enabled = 0;
1172                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1173                         lcd_bus_width);
1174                 return;
1175         }
1176         if (is_lvds()) {
1177                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1178                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1179                 uint32_t gpr2;
1180
1181                 if (lvds_chan_mask == 0) {
1182                         printf("No LVDS channel active\n");
1183                         lcd_enabled = 0;
1184                         return;
1185                 }
1186
1187                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1188                 if (lcd_bus_width == 24)
1189                         gpr2 |= (1 << 5) | (1 << 7);
1190                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1191                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1192                 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1193                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1194         }
1195         if (karo_load_splashimage(0) == 0) {
1196                 int ret;
1197
1198                 debug("Initializing LCD controller\n");
1199                 ret = ipuv3_fb_init(p, 0, pix_fmt, DI_PCLK_PLL3, di_clk_rate, -1);
1200                 if (ret) {
1201                         printf("Failed to initialize FB driver: %d\n", ret);
1202                         lcd_enabled = 0;
1203                 }
1204         } else {
1205                 debug("Skipping initialization of LCD controller\n");
1206         }
1207 }
1208 #else
1209 #define lcd_enabled 0
1210 #endif /* CONFIG_LCD */
1211
1212 static void stk5_board_init(void)
1213 {
1214         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1215         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1216 }
1217
1218 static void stk5v3_board_init(void)
1219 {
1220         stk5_board_init();
1221 }
1222
1223 static void stk5v5_board_init(void)
1224 {
1225         stk5_board_init();
1226
1227         gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
1228                         "Flexcan Transceiver");
1229         imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO_4_21);
1230 }
1231
1232 static void tx6qdl_set_cpu_clock(void)
1233 {
1234         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1235
1236         if (had_ctrlc() || (wrsr & WRSR_TOUT))
1237                 return;
1238
1239         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1240                 return;
1241
1242         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1243                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1244                 printf("CPU clock set to %lu.%03lu MHz\n",
1245                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1246         } else {
1247                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1248         }
1249 }
1250
1251 static void tx6_init_mac(void)
1252 {
1253         u8 mac[ETH_ALEN];
1254
1255         imx_get_mac_from_fuse(-1, mac);
1256         if (!is_valid_ether_addr(mac)) {
1257                 printf("No valid MAC address programmed\n");
1258                 return;
1259         }
1260
1261         printf("MAC addr from fuse: %pM\n", mac);
1262         eth_setenv_enetaddr("ethaddr", mac);
1263 }
1264
1265 int board_late_init(void)
1266 {
1267         int ret = 0;
1268         const char *baseboard;
1269
1270         tx6qdl_set_cpu_clock();
1271         karo_fdt_move_fdt();
1272
1273         baseboard = getenv("baseboard");
1274         if (!baseboard)
1275                 goto exit;
1276
1277         printf("Baseboard: %s\n", baseboard);
1278
1279         if (strncmp(baseboard, "stk5", 4) == 0) {
1280                 if ((strlen(baseboard) == 4) ||
1281                         strcmp(baseboard, "stk5-v3") == 0) {
1282                         stk5v3_board_init();
1283                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1284                         const char *otg_mode = getenv("otg_mode");
1285
1286                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1287                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1288                                         otg_mode, baseboard);
1289                                 setenv("otg_mode", "none");
1290                         }
1291                         stk5v5_board_init();
1292                 } else {
1293                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1294                                 baseboard + 4);
1295                 }
1296         } else {
1297                 printf("WARNING: Unsupported baseboard: '%s'\n",
1298                         baseboard);
1299                 ret = -EINVAL;
1300         }
1301
1302 exit:
1303         tx6_init_mac();
1304
1305         gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1306         clear_ctrlc();
1307         return ret;
1308 }
1309
1310 int checkboard(void)
1311 {
1312         u32 cpurev = get_cpu_rev();
1313         int cpu_variant = (cpurev >> 12) & 0xff;
1314
1315         tx6qdl_print_cpuinfo();
1316
1317         printf("Board: Ka-Ro TX6%c-%d%d1%d\n",
1318                 cpu_variant == MXC_CPU_MX6Q ? 'Q' : 'U',
1319                 cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
1320                 is_lvds(), 1 - PHYS_SDRAM_1_WIDTH / 64);
1321
1322         return 0;
1323 }
1324
1325 #ifdef CONFIG_SERIAL_TAG
1326 void get_board_serial(struct tag_serialnr *serialnr)
1327 {
1328         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1329         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1330
1331         serialnr->low = readl(&fuse->cfg0);
1332         serialnr->high = readl(&fuse->cfg1);
1333 }
1334 #endif
1335
1336 #if defined(CONFIG_OF_BOARD_SETUP)
1337 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1338 #include <jffs2/jffs2.h>
1339 #include <mtd_node.h>
1340 static struct node_info nodes[] = {
1341         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1342 };
1343 #else
1344 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1345 #endif
1346
1347 static const char *tx6_touchpanels[] = {
1348         "ti,tsc2007",
1349         "edt,edt-ft5x06",
1350         "eeti,egalax_ts",
1351 };
1352
1353 void ft_board_setup(void *blob, bd_t *bd)
1354 {
1355         const char *baseboard = getenv("baseboard");
1356         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1357         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1358         int ret;
1359
1360         ret = fdt_increase_size(blob, 4096);
1361         if (ret)
1362                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1363
1364         if (stk5_v5)
1365                 karo_fdt_enable_node(blob, "stk5led", 0);
1366
1367         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1368         fdt_fixup_ethernet(blob);
1369
1370         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1371                                 ARRAY_SIZE(tx6_touchpanels));
1372         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy");
1373         karo_fdt_fixup_flexcan(blob, stk5_v5);
1374
1375         karo_fdt_update_fb_mode(blob, video_mode);
1376 }
1377 #endif /* CONFIG_OF_BOARD_SETUP */