board/karo/tx6/tx6qdl.c

   1 /*
   2  * Copyright (C) 2012,2013 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * version 2 as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <common.h>
  19 #include <errno.h>
  20 #include <libfdt.h>
  21 #include <fdt_support.h>
  22 #include <lcd.h>
  23 #include <netdev.h>
  24 #include <mmc.h>
  25 #include <fsl_esdhc.h>
  26 #include <video_fb.h>
  27 #include <ipu.h>
  28 #include <mxcfb.h>
  29 #include <i2c.h>
  30 #include <linux/fb.h>
  31 #include <asm/io.h>
  32 #include <asm/gpio.h>
  33 #include <asm/arch/mx6-pins.h>
  34 #include <asm/arch/clock.h>
  35 #include <asm/arch/imx-regs.h>
  36 #include <asm/arch/crm_regs.h>
  37 #include <asm/arch/sys_proto.h>
  38
  39 #include "../common/karo.h"
  40
  41 #define TX6_FEC_RST_GPIO                IMX_GPIO_NR(7, 6)
  42 #define TX6_FEC_PWR_GPIO                IMX_GPIO_NR(3, 20)
  43 #define TX6_FEC_INT_GPIO                IMX_GPIO_NR(2, 4)
  44 #define TX6_LED_GPIO                    IMX_GPIO_NR(2, 20)
  45
  46 #define TX6_LCD_PWR_GPIO                IMX_GPIO_NR(2, 31)
  47 #define TX6_LCD_RST_GPIO                IMX_GPIO_NR(3, 29)
  48 #define TX6_LCD_BACKLIGHT_GPIO          IMX_GPIO_NR(1, 1)
  49
  50 #define TX6_RESET_OUT_GPIO              IMX_GPIO_NR(7, 12)
  51
  52 #define TEMPERATURE_MIN                 -40
  53 #define TEMPERATURE_HOT                 80
  54 #define TEMPERATURE_MAX                 125
  55
  56 DECLARE_GLOBAL_DATA_PTR;
  57
  58 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  59
  60 static const iomux_v3_cfg_t tx6qdl_pads[] = {
  61         /* NAND flash pads */
  62         MX6_PAD_NANDF_CLE__RAWNAND_CLE,
  63         MX6_PAD_NANDF_ALE__RAWNAND_ALE,
  64         MX6_PAD_NANDF_WP_B__RAWNAND_RESETN,
  65         MX6_PAD_NANDF_RB0__RAWNAND_READY0,
  66         MX6_PAD_NANDF_CS0__RAWNAND_CE0N,
  67         MX6_PAD_SD4_CMD__RAWNAND_RDN,
  68         MX6_PAD_SD4_CLK__RAWNAND_WRN,
  69         MX6_PAD_NANDF_D0__RAWNAND_D0,
  70         MX6_PAD_NANDF_D1__RAWNAND_D1,
  71         MX6_PAD_NANDF_D2__RAWNAND_D2,
  72         MX6_PAD_NANDF_D3__RAWNAND_D3,
  73         MX6_PAD_NANDF_D4__RAWNAND_D4,
  74         MX6_PAD_NANDF_D5__RAWNAND_D5,
  75         MX6_PAD_NANDF_D6__RAWNAND_D6,
  76         MX6_PAD_NANDF_D7__RAWNAND_D7,
  77
  78         /* RESET_OUT */
  79         MX6_PAD_GPIO_17__GPIO_7_12,
  80
  81         /* UART pads */
  82 #if CONFIG_MXC_UART_BASE == UART1_BASE
  83         MX6_PAD_SD3_DAT7__UART1_TXD,
  84         MX6_PAD_SD3_DAT6__UART1_RXD,
  85         MX6_PAD_SD3_DAT1__UART1_RTS,
  86         MX6_PAD_SD3_DAT0__UART1_CTS,
  87 #endif
  88 #if CONFIG_MXC_UART_BASE == UART2_BASE
  89         MX6_PAD_SD4_DAT4__UART2_RXD,
  90         MX6_PAD_SD4_DAT7__UART2_TXD,
  91         MX6_PAD_SD4_DAT5__UART2_RTS,
  92         MX6_PAD_SD4_DAT6__UART2_CTS,
  93 #endif
  94 #if CONFIG_MXC_UART_BASE == UART3_BASE
  95         MX6_PAD_EIM_D24__UART3_TXD,
  96         MX6_PAD_EIM_D25__UART3_RXD,
  97         MX6_PAD_SD3_RST__UART3_RTS,
  98         MX6_PAD_SD3_DAT3__UART3_CTS,
  99 #endif
 100         /* internal I2C */
 101         MX6_PAD_EIM_D28__I2C1_SDA,
 102         MX6_PAD_EIM_D21__I2C1_SCL,
 103
 104         /* FEC PHY GPIO functions */
 105         MX6_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */
 106         MX6_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */
 107         MX6_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */
 108 };
 109
 110 static const iomux_v3_cfg_t tx6qdl_fec_pads[] = {
 111         /* FEC functions */
 112         MX6_PAD_ENET_MDC__ENET_MDC,
 113         MX6_PAD_ENET_MDIO__ENET_MDIO,
 114         MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
 115         MX6_PAD_ENET_RX_ER__ENET_RX_ER,
 116         MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
 117         MX6_PAD_ENET_RXD1__ENET_RDATA_1,
 118         MX6_PAD_ENET_RXD0__ENET_RDATA_0,
 119         MX6_PAD_ENET_TX_EN__ENET_TX_EN,
 120         MX6_PAD_ENET_TXD1__ENET_TDATA_1,
 121         MX6_PAD_ENET_TXD0__ENET_TDATA_0,
 122 };
 123
 124 static const struct gpio tx6qdl_gpios[] = {
 125         { TX6_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
 126         { TX6_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 127         { TX6_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 128         { TX6_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
 129 };
 130
 131 /*
 132  * Functions
 133  */
 134 /* placed in section '.data' to prevent overwriting relocation info
 135  * overlayed with bss
 136  */
 137 static u32 wrsr __attribute__((section(".data")));
 138
 139 #define WRSR_POR                        (1 << 4)
 140 #define WRSR_TOUT                       (1 << 1)
 141 #define WRSR_SFTW                       (1 << 0)
 142
 143 static void print_reset_cause(void)
 144 {
 145         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 146         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 147         u32 srsr;
 148         char *dlm = "";
 149
 150         printf("Reset cause: ");
 151
 152         srsr = readl(&src_regs->srsr);
 153         wrsr = readw(wdt_base + 4);
 154
 155         if (wrsr & WRSR_POR) {
 156                 printf("%sPOR", dlm);
 157                 dlm = " | ";
 158         }
 159         if (srsr & 0x00004) {
 160                 printf("%sCSU", dlm);
 161                 dlm = " | ";
 162         }
 163         if (srsr & 0x00008) {
 164                 printf("%sIPP USER", dlm);
 165                 dlm = " | ";
 166         }
 167         if (srsr & 0x00010) {
 168                 if (wrsr & WRSR_SFTW) {
 169                         printf("%sSOFT", dlm);
 170                         dlm = " | ";
 171                 }
 172                 if (wrsr & WRSR_TOUT) {
 173                         printf("%sWDOG", dlm);
 174                         dlm = " | ";
 175                 }
 176         }
 177         if (srsr & 0x00020) {
 178                 printf("%sJTAG HIGH-Z", dlm);
 179                 dlm = " | ";
 180         }
 181         if (srsr & 0x00040) {
 182                 printf("%sJTAG SW", dlm);
 183                 dlm = " | ";
 184         }
 185         if (srsr & 0x10000) {
 186                 printf("%sWARM BOOT", dlm);
 187                 dlm = " | ";
 188         }
 189         if (dlm[0] == '\0')
 190                 printf("unknown");
 191
 192         printf("\n");
 193 }
 194
 195 int read_cpu_temperature(void);
 196 int check_cpu_temperature(int boot);
 197
 198 static void tx6qdl_print_cpuinfo(void)
 199 {
 200         u32 cpurev = get_cpu_rev();
 201         char *cpu_str = "?";
 202
 203         switch ((cpurev >> 12) & 0xff) {
 204         case MXC_CPU_MX6SL:
 205                 cpu_str = "SL";
 206                 break;
 207         case MXC_CPU_MX6DL:
 208                 cpu_str = "DL";
 209                 break;
 210         case MXC_CPU_MX6SOLO:
 211                 cpu_str = "SOLO";
 212                 break;
 213         case MXC_CPU_MX6Q:
 214                 cpu_str = "Q";
 215                 break;
 216         }
 217
 218         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
 219                 cpu_str,
 220                 (cpurev & 0x000F0) >> 4,
 221                 (cpurev & 0x0000F) >> 0,
 222                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 223
 224         print_reset_cause();
 225         check_cpu_temperature(1);
 226 }
 227
 228 #define LTC3676_BUCK1           0x01
 229 #define LTC3676_BUCK2           0x02
 230 #define LTC3676_BUCK3           0x03
 231 #define LTC3676_BUCK4           0x04
 232 #define LTC3676_DVB1A           0x0A
 233 #define LTC3676_DVB1B           0x0B
 234 #define LTC3676_DVB2A           0x0C
 235 #define LTC3676_DVB2B           0x0D
 236 #define LTC3676_DVB3A           0x0E
 237 #define LTC3676_DVB3B           0x0F
 238 #define LTC3676_DVB4A           0x10
 239 #define LTC3676_DVB4B           0x11
 240 #define LTC3676_MSKPG           0x13
 241 #define LTC3676_CLIRQ           0x1f
 242
 243 #define LTC3676_BUCK_DVDT_FAST  (1 << 0)
 244 #define LTC3676_BUCK_KEEP_ALIVE (1 << 1)
 245 #define LTC3676_BUCK_CLK_RATE_LOW (1 << 2)
 246 #define LTC3676_BUCK_PHASE_SEL  (1 << 3)
 247 #define LTC3676_BUCK_ENABLE_300 (1 << 4)
 248 #define LTC3676_BUCK_PULSE_SKIP (0 << 5)
 249 #define LTC3676_BUCK_BURST_MODE (1 << 5)
 250 #define LTC3676_BUCK_CONTINUOUS (2 << 5)
 251 #define LTC3676_BUCK_ENABLE     (1 << 7)
 252
 253 #define LTC3676_PGOOD_MASK      (1 << 5)
 254
 255 #define LTC3676_MSKPG_BUCK1     (1 << 0)
 256 #define LTC3676_MSKPG_BUCK2     (1 << 1)
 257 #define LTC3676_MSKPG_BUCK3     (1 << 2)
 258 #define LTC3676_MSKPG_BUCK4     (1 << 3)
 259 #define LTC3676_MSKPG_LDO2      (1 << 5)
 260 #define LTC3676_MSKPG_LDO3      (1 << 6)
 261 #define LTC3676_MSKPG_LDO4      (1 << 7)
 262
 263 #define VDD_IO_VAL              mV_to_regval(vout_to_vref(3300 * 10, 5))
 264 #define VDD_IO_VAL_LP           mV_to_regval(vout_to_vref(3100 * 10, 5))
 265 #define VDD_IO_VAL_2            mV_to_regval(vout_to_vref(3300 * 10, 5_2))
 266 #define VDD_IO_VAL_2_LP         mV_to_regval(vout_to_vref(3100 * 10, 5_2))
 267 #define VDD_SOC_VAL             mV_to_regval(vout_to_vref(1425 * 10, 6))
 268 #define VDD_SOC_VAL_LP          mV_to_regval(vout_to_vref(900 * 10, 6))
 269 #define VDD_DDR_VAL             mV_to_regval(vout_to_vref(1500 * 10, 7))
 270 #define VDD_CORE_VAL            mV_to_regval(vout_to_vref(1425 * 10, 8))
 271 #define VDD_CORE_VAL_LP         mV_to_regval(vout_to_vref(900 * 10, 8))
 272
 273 /* LDO1 */
 274 #define R1_1                    470
 275 #define R2_1                    150
 276 /* LDO4 */
 277 #define R1_4                    470
 278 #define R2_4                    150
 279 /* Buck1 */
 280 #define R1_5                    390
 281 #define R2_5                    110
 282 #define R1_5_2                  470
 283 #define R2_5_2                  150
 284 /* Buck2 */
 285 #define R1_6                    150
 286 #define R2_6                    180
 287 /* Buck3 */
 288 #define R1_7                    150
 289 #define R2_7                    140
 290 /* Buck4 */
 291 #define R1_8                    150
 292 #define R2_8                    180
 293
 294 /* calculate voltages in 10mV */
 295 #define R1(idx)                 R1_##idx
 296 #define R2(idx)                 R2_##idx
 297
 298 #define vout_to_vref(vout, idx) ((vout) * R2(idx) / (R1(idx) + R2(idx)))
 299 #define vref_to_vout(vref, idx) DIV_ROUND_UP((vref) * (R1(idx) + R2(idx)), R2(idx))
 300
 301 #define mV_to_regval(mV)        DIV_ROUND(((((mV) < 4125) ? 4125 : (mV)) - 4125), 125)
 302 #define regval_to_mV(v)         (((v) * 125 + 4125))
 303
 304 static struct ltc3673_regs {
 305         u8 addr;
 306         u8 val;
 307         u8 mask;
 308 } ltc3676_regs[] = {
 309         { LTC3676_MSKPG, ~LTC3676_MSKPG_BUCK1, },
 310         { LTC3676_DVB2B, VDD_SOC_VAL | LTC3676_PGOOD_MASK, ~0x3f, },
 311         { LTC3676_DVB3B, VDD_DDR_VAL, ~0x3f, },
 312         { LTC3676_DVB4B, VDD_CORE_VAL | LTC3676_PGOOD_MASK, ~0x3f, },
 313         { LTC3676_DVB2A, VDD_SOC_VAL, ~0x3f, },
 314         { LTC3676_DVB3A, VDD_DDR_VAL, ~0x3f, },
 315         { LTC3676_DVB4A, VDD_CORE_VAL, ~0x3f, },
 316         { LTC3676_BUCK1, LTC3676_BUCK_BURST_MODE | LTC3676_BUCK_CLK_RATE_LOW, },
 317         { LTC3676_BUCK2, LTC3676_BUCK_BURST_MODE, },
 318         { LTC3676_BUCK3, LTC3676_BUCK_BURST_MODE, },
 319         { LTC3676_BUCK4, LTC3676_BUCK_BURST_MODE, },
 320         { LTC3676_CLIRQ, 0, }, /* clear interrupt status */
 321 };
 322
 323 static struct ltc3673_regs ltc3676_regs_1[] = {
 324         { LTC3676_DVB1B, VDD_IO_VAL_LP | LTC3676_PGOOD_MASK, ~0x3f, },
 325         { LTC3676_DVB1A, VDD_IO_VAL, ~0x3f, },
 326 };
 327
 328 static struct ltc3673_regs ltc3676_regs_2[] = {
 329         { LTC3676_DVB1B, VDD_IO_VAL_2_LP | LTC3676_PGOOD_MASK, ~0x3f, },
 330         { LTC3676_DVB1A, VDD_IO_VAL_2, ~0x3f, },
 331 };
 332
 333 static int tx6_rev_2(void)
 334 {
 335         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 336         struct fuse_bank5_regs *fuse = (void *)ocotp->bank[5].fuse_regs;
 337         u32 pad_settings = readl(&fuse->pad_settings);
 338
 339         debug("Fuse pad_settings @ %p = %08x\n",
 340                 &fuse->pad_settings, pad_settings);
 341         return pad_settings & 1;
 342 }
 343
 344 static int tx6_ltc3676_setup_regs(struct ltc3673_regs *r, size_t count)
 345 {
 346         int ret;
 347         int i;
 348
 349         for (i = 0; i < count; i++, r++) {
 350 #ifdef DEBUG
 351                 unsigned char value;
 352
 353                 ret = i2c_read(CONFIG_SYS_I2C_SLAVE, r->addr, 1, &value, 1);
 354                 if ((value & ~r->mask) != r->val) {
 355                         printf("Changing PMIC reg %02x from %02x to %02x\n",
 356                                 r->addr, value, r->val);
 357                 }
 358                 if (ret) {
 359                         printf("%s: failed to read PMIC register %02x: %d\n",
 360                                 __func__, r->addr, ret);
 361                         return ret;
 362                 }
 363 #endif
 364                 ret = i2c_write(CONFIG_SYS_I2C_SLAVE,
 365                                 r->addr, 1, &r->val, 1);
 366                 if (ret) {
 367                         printf("%s: failed to write PMIC register %02x: %d\n",
 368                                 __func__, r->addr, ret);
 369                         return ret;
 370                 }
 371         }
 372         return 0;
 373 }
 374
 375 static int setup_pmic_voltages(void)
 376 {
 377         int ret;
 378         unsigned char value;
 379
 380         ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
 381         if (ret != 0) {
 382                 printf("Failed to initialize I2C\n");
 383                 return ret;
 384         }
 385
 386         ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
 387         if (ret) {
 388                 printf("%s: i2c_read error: %d\n", __func__, ret);
 389                 return ret;
 390         }
 391
 392         ret = tx6_ltc3676_setup_regs(ltc3676_regs, ARRAY_SIZE(ltc3676_regs));
 393         if (ret)
 394                 return ret;
 395
 396         printf("VDDCORE set to %umV\n",
 397                 DIV_ROUND(vref_to_vout(regval_to_mV(VDD_CORE_VAL), 8), 10));
 398         printf("VDDSOC  set to %umV\n",
 399                 DIV_ROUND(vref_to_vout(regval_to_mV(VDD_SOC_VAL), 6), 10));
 400
 401         if (tx6_rev_2()) {
 402                 ret = tx6_ltc3676_setup_regs(ltc3676_regs_2,
 403                                 ARRAY_SIZE(ltc3676_regs_2));
 404                 printf("VDDIO   set to %umV\n",
 405                         DIV_ROUND(vref_to_vout(
 406                                         regval_to_mV(VDD_IO_VAL_2), 5_2), 10));
 407         } else {
 408                 ret = tx6_ltc3676_setup_regs(ltc3676_regs_1,
 409                                 ARRAY_SIZE(ltc3676_regs_1));
 410         }
 411         return ret;
 412 }
 413
 414 int board_early_init_f(void)
 415 {
 416         gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
 417         imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
 418
 419         return 0;
 420 }
 421
 422 int board_init(void)
 423 {
 424         int ret;
 425
 426         /* Address of boot parameters */
 427         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 428 #ifdef CONFIG_OF_LIBFDT
 429         gd->bd->bi_arch_number = -1;
 430 #else
 431         gd->bd->bi_arch_number = 4429;
 432 #endif
 433         ret = setup_pmic_voltages();
 434         if (ret) {
 435                 printf("Failed to setup PMIC voltages\n");
 436                 hang();
 437         }
 438         return 0;
 439 }
 440
 441 int dram_init(void)
 442 {
 443         /* dram_init must store complete ramsize in gd->ram_size */
 444         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 445                                 PHYS_SDRAM_1_SIZE);
 446         return 0;
 447 }
 448
 449 void dram_init_banksize(void)
 450 {
 451         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 452         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 453                         PHYS_SDRAM_1_SIZE);
 454 #if CONFIG_NR_DRAM_BANKS > 1
 455         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 456         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 457                         PHYS_SDRAM_2_SIZE);
 458 #endif
 459 }
 460
 461 #ifdef  CONFIG_CMD_MMC
 462 static const iomux_v3_cfg_t mmc0_pads[] = {
 463         MX6_PAD_SD1_CMD__USDHC1_CMD,
 464         MX6_PAD_SD1_CLK__USDHC1_CLK,
 465         MX6_PAD_SD1_DAT0__USDHC1_DAT0,
 466         MX6_PAD_SD1_DAT1__USDHC1_DAT1,
 467         MX6_PAD_SD1_DAT2__USDHC1_DAT2,
 468         MX6_PAD_SD1_DAT3__USDHC1_DAT3,
 469         /* SD1 CD */
 470         MX6_PAD_SD3_CMD__GPIO_7_2,
 471 };
 472
 473 static const iomux_v3_cfg_t mmc1_pads[] = {
 474         MX6_PAD_SD2_CMD__USDHC2_CMD,
 475         MX6_PAD_SD2_CLK__USDHC2_CLK,
 476         MX6_PAD_SD2_DAT0__USDHC2_DAT0,
 477         MX6_PAD_SD2_DAT1__USDHC2_DAT1,
 478         MX6_PAD_SD2_DAT2__USDHC2_DAT2,
 479         MX6_PAD_SD2_DAT3__USDHC2_DAT3,
 480         /* SD2 CD */
 481         MX6_PAD_SD3_CLK__GPIO_7_3,
 482 };
 483
 484 static struct tx6_esdhc_cfg {
 485         const iomux_v3_cfg_t *pads;
 486         int num_pads;
 487         enum mxc_clock clkid;
 488         struct fsl_esdhc_cfg cfg;
 489         int cd_gpio;
 490 } tx6qdl_esdhc_cfg[] = {
 491         {
 492                 .pads = mmc0_pads,
 493                 .num_pads = ARRAY_SIZE(mmc0_pads),
 494                 .clkid = MXC_ESDHC_CLK,
 495                 .cfg = {
 496                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
 497                         .max_bus_width = 4,
 498                 },
 499                 .cd_gpio = IMX_GPIO_NR(7, 2),
 500         },
 501         {
 502                 .pads = mmc1_pads,
 503                 .num_pads = ARRAY_SIZE(mmc1_pads),
 504                 .clkid = MXC_ESDHC2_CLK,
 505                 .cfg = {
 506                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
 507                         .max_bus_width = 4,
 508                 },
 509                 .cd_gpio = IMX_GPIO_NR(7, 3),
 510         },
 511 };
 512
 513 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 514 {
 515         void *p = cfg;
 516
 517         return p - offsetof(struct tx6_esdhc_cfg, cfg);
 518 }
 519
 520 int board_mmc_getcd(struct mmc *mmc)
 521 {
 522         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
 523
 524         if (cfg->cd_gpio < 0)
 525                 return cfg->cd_gpio;
 526
 527         debug("SD card %d is %spresent\n",
 528                 cfg - tx6qdl_esdhc_cfg,
 529                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
 530         return !gpio_get_value(cfg->cd_gpio);
 531 }
 532
 533 int board_mmc_init(bd_t *bis)
 534 {
 535         int i;
 536
 537         for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
 538                 struct mmc *mmc;
 539                 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
 540                 int ret;
 541
 542                 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
 543                         break;
 544
 545                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
 546                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
 547
 548                 ret = gpio_request_one(cfg->cd_gpio,
 549                                 GPIOF_INPUT, "MMC CD");
 550                 if (ret) {
 551                         printf("Error %d requesting GPIO%d_%d\n",
 552                                 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 553                         continue;
 554                 }
 555
 556                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 557                 fsl_esdhc_initialize(bis, &cfg->cfg);
 558
 559                 mmc = find_mmc_device(i);
 560                 if (mmc == NULL)
 561                         continue;
 562                 if (board_mmc_getcd(mmc) > 0)
 563                         mmc_init(mmc);
 564         }
 565         return 0;
 566 }
 567 #endif /* CONFIG_CMD_MMC */
 568
 569 #ifdef CONFIG_FEC_MXC
 570
 571 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
 572                         PAD_CTL_SRE_FAST)
 573 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
 574 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 575
 576 #ifndef ETH_ALEN
 577 #define ETH_ALEN 6
 578 #endif
 579
 580 int board_eth_init(bd_t *bis)
 581 {
 582         int ret;
 583
 584         /* delay at least 21ms for the PHY internal POR signal to deassert */
 585         udelay(22000);
 586
 587         imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads, ARRAY_SIZE(tx6qdl_fec_pads));
 588
 589         /* Deassert RESET to the external phy */
 590         gpio_set_value(TX6_FEC_RST_GPIO, 1);
 591
 592         ret = cpu_eth_init(bis);
 593         if (ret)
 594                 printf("cpu_eth_init() failed: %d\n", ret);
 595
 596         return ret;
 597 }
 598 #endif /* CONFIG_FEC_MXC */
 599
 600 enum {
 601         LED_STATE_INIT = -1,
 602         LED_STATE_OFF,
 603         LED_STATE_ON,
 604 };
 605
 606 static inline int calc_blink_rate(int tmp)
 607 {
 608         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
 609                 (tmp - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
 610                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
 611 }
 612
 613 void show_activity(int arg)
 614 {
 615         static int led_state = LED_STATE_INIT;
 616         static int blink_rate;
 617         static ulong last;
 618
 619         if (led_state == LED_STATE_INIT) {
 620                 last = get_timer(0);
 621                 gpio_set_value(TX6_LED_GPIO, 1);
 622                 led_state = LED_STATE_ON;
 623                 blink_rate = calc_blink_rate(check_cpu_temperature(0));
 624         } else {
 625                 if (get_timer(last) > blink_rate) {
 626                         blink_rate = calc_blink_rate(check_cpu_temperature(0));
 627                         last = get_timer_masked();
 628                         if (led_state == LED_STATE_ON) {
 629                                 gpio_set_value(TX6_LED_GPIO, 0);
 630                         } else {
 631                                 gpio_set_value(TX6_LED_GPIO, 1);
 632                         }
 633                         led_state = 1 - led_state;
 634                 }
 635         }
 636 }
 637
 638 static const iomux_v3_cfg_t stk5_pads[] = {
 639         /* SW controlled LED on STK5 baseboard */
 640         MX6_PAD_EIM_A18__GPIO_2_20,
 641
 642         /* LCD data pins */
 643         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
 644         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
 645         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
 646         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
 647         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
 648         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
 649         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
 650         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
 651         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
 652         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
 653         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
 654         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
 655         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
 656         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
 657         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
 658         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
 659         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
 660         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
 661         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
 662         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
 663         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
 664         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
 665         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
 666         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
 667         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */
 668         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */
 669         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
 670         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
 671
 672         /* I2C bus on DIMM pins 40/41 */
 673         MX6_PAD_GPIO_6__I2C3_SDA,
 674         MX6_PAD_GPIO_3__I2C3_SCL,
 675
 676         /* TSC200x PEN IRQ */
 677         MX6_PAD_EIM_D26__GPIO_3_26,
 678
 679         /* EDT-FT5x06 Polytouch panel */
 680         MX6_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */
 681         MX6_PAD_EIM_A16__GPIO_2_22, /* RESET */
 682         MX6_PAD_EIM_A17__GPIO_2_21, /* WAKE */
 683
 684         /* USBH1 */
 685         MX6_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */
 686         MX6_PAD_EIM_D30__GPIO_3_30, /* OC */
 687         /* USBOTG */
 688         MX6_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */
 689         MX6_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */
 690         MX6_PAD_GPIO_8__GPIO_1_8, /* OC */
 691 };
 692
 693 static const struct gpio stk5_gpios[] = {
 694         { TX6_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 695
 696         { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", },
 697         { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
 698         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 699         { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
 700         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 701 };
 702
 703 #ifdef CONFIG_LCD
 704 vidinfo_t panel_info = {
 705         /* set to max. size supported by SoC */
 706         .vl_col = 1920,
 707         .vl_row = 1080,
 708
 709         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 710 };
 711
 712 static struct fb_videomode tx6_fb_modes[] = {
 713         {
 714                 /* Standard VGA timing */
 715                 .name           = "VGA",
 716                 .refresh        = 60,
 717                 .xres           = 640,
 718                 .yres           = 480,
 719                 .pixclock       = KHZ2PICOS(25175),
 720                 .left_margin    = 48,
 721                 .hsync_len      = 96,
 722                 .right_margin   = 16,
 723                 .upper_margin   = 31,
 724                 .vsync_len      = 2,
 725                 .lower_margin   = 12,
 726                 .sync           = FB_SYNC_CLK_LAT_FALL,
 727         },
 728         {
 729                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 730                  * DE high active, 115.2 mm x 86.4 mm display area
 731                  * VGA compatible timing
 732                  */
 733                 .name           = "ETV570",
 734                 .refresh        = 60,
 735                 .xres           = 640,
 736                 .yres           = 480,
 737                 .pixclock       = KHZ2PICOS(25175),
 738                 .left_margin    = 114,
 739                 .hsync_len      = 30,
 740                 .right_margin   = 16,
 741                 .upper_margin   = 32,
 742                 .vsync_len      = 3,
 743                 .lower_margin   = 10,
 744                 .sync           = FB_SYNC_CLK_LAT_FALL,
 745         },
 746         {
 747                 /* Emerging ET0350G0DH6 320 x 240 display.
 748                  * 70.08 mm x 52.56 mm display area.
 749                  */
 750                 .name           = "ET0350",
 751                 .refresh        = 60,
 752                 .xres           = 320,
 753                 .yres           = 240,
 754                 .pixclock       = KHZ2PICOS(6500),
 755                 .left_margin    = 68 - 34,
 756                 .hsync_len      = 34,
 757                 .right_margin   = 20,
 758                 .upper_margin   = 18 - 3,
 759                 .vsync_len      = 3,
 760                 .lower_margin   = 4,
 761                 .sync           = FB_SYNC_CLK_LAT_FALL,
 762         },
 763         {
 764                 /* Emerging ET0430G0DH6 480 x 272 display.
 765                  * 95.04 mm x 53.856 mm display area.
 766                  */
 767                 .name           = "ET0430",
 768                 .refresh        = 60,
 769                 .xres           = 480,
 770                 .yres           = 272,
 771                 .pixclock       = KHZ2PICOS(9000),
 772                 .left_margin    = 2,
 773                 .hsync_len      = 41,
 774                 .right_margin   = 2,
 775                 .upper_margin   = 2,
 776                 .vsync_len      = 10,
 777                 .lower_margin   = 2,
 778                 .sync           = FB_SYNC_CLK_LAT_FALL,
 779         },
 780         {
 781                 /* Emerging ET0500G0DH6 800 x 480 display.
 782                  * 109.6 mm x 66.4 mm display area.
 783                  */
 784                 .name           = "ET0500",
 785                 .refresh        = 60,
 786                 .xres           = 800,
 787                 .yres           = 480,
 788                 .pixclock       = KHZ2PICOS(33260),
 789                 .left_margin    = 216 - 128,
 790                 .hsync_len      = 128,
 791                 .right_margin   = 1056 - 800 - 216,
 792                 .upper_margin   = 35 - 2,
 793                 .vsync_len      = 2,
 794                 .lower_margin   = 525 - 480 - 35,
 795                 .sync           = FB_SYNC_CLK_LAT_FALL,
 796         },
 797         {
 798                 /* Emerging ETQ570G0DH6 320 x 240 display.
 799                  * 115.2 mm x 86.4 mm display area.
 800                  */
 801                 .name           = "ETQ570",
 802                 .refresh        = 60,
 803                 .xres           = 320,
 804                 .yres           = 240,
 805                 .pixclock       = KHZ2PICOS(6400),
 806                 .left_margin    = 38,
 807                 .hsync_len      = 30,
 808                 .right_margin   = 30,
 809                 .upper_margin   = 16, /* 15 according to datasheet */
 810                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 811                 .lower_margin   = 4, /* 4.5 according to datasheet */
 812                 .sync           = FB_SYNC_CLK_LAT_FALL,
 813         },
 814         {
 815                 /* Emerging ET0700G0DH6 800 x 480 display.
 816                  * 152.4 mm x 91.44 mm display area.
 817                  */
 818                 .name           = "ET0700",
 819                 .refresh        = 60,
 820                 .xres           = 800,
 821                 .yres           = 480,
 822                 .pixclock       = KHZ2PICOS(33260),
 823                 .left_margin    = 216 - 128,
 824                 .hsync_len      = 128,
 825                 .right_margin   = 1056 - 800 - 216,
 826                 .upper_margin   = 35 - 2,
 827                 .vsync_len      = 2,
 828                 .lower_margin   = 525 - 480 - 35,
 829                 .sync           = FB_SYNC_CLK_LAT_FALL,
 830         },
 831         {
 832                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 833                 .refresh        = 60,
 834                 .left_margin    = 48,
 835                 .hsync_len      = 96,
 836                 .right_margin   = 16,
 837                 .upper_margin   = 31,
 838                 .vsync_len      = 2,
 839                 .lower_margin   = 12,
 840                 .sync           = FB_SYNC_CLK_LAT_FALL,
 841         },
 842 };
 843
 844 static int lcd_enabled = 1;
 845
 846 void lcd_enable(void)
 847 {
 848         /* HACK ALERT:
 849          * global variable from common/lcd.c
 850          * Set to 0 here to prevent messages from going to LCD
 851          * rather than serial console
 852          */
 853         lcd_is_enabled = 0;
 854
 855         karo_load_splashimage(1);
 856
 857         if (lcd_enabled) {
 858                 debug("Switching LCD on\n");
 859                 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
 860                 udelay(100);
 861                 gpio_set_value(TX6_LCD_RST_GPIO, 1);
 862                 udelay(300000);
 863                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, 0);
 864         }
 865 }
 866
 867 void lcd_disable(void)
 868 {
 869         if (lcd_enabled) {
 870                 printf("Disabling LCD\n");
 871                 ipuv3_fb_shutdown();
 872         }
 873 }
 874
 875 void lcd_panel_disable(void)
 876 {
 877         if (lcd_enabled) {
 878                 debug("Switching LCD off\n");
 879                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, 1);
 880                 gpio_set_value(TX6_LCD_RST_GPIO, 0);
 881                 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
 882         }
 883 }
 884
 885 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 886         /* LCD RESET */
 887         MX6_PAD_EIM_D29__GPIO_3_29,
 888         /* LCD POWER_ENABLE */
 889         MX6_PAD_EIM_EB3__GPIO_2_31,
 890         /* LCD Backlight (PWM) */
 891         MX6_PAD_GPIO_1__GPIO_1_1,
 892
 893         /* Display */
 894         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
 895         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
 896         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
 897         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
 898         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
 899         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
 900         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
 901         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
 902         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
 903         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
 904         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
 905         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
 906         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
 907         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
 908         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
 909         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
 910         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
 911         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
 912         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
 913         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
 914         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
 915         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
 916         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
 917         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
 918         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
 919         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
 920         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
 921         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
 922 };
 923
 924 static const struct gpio stk5_lcd_gpios[] = {
 925         { TX6_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
 926         { TX6_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
 927         { TX6_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 928 };
 929
 930 void lcd_ctrl_init(void *lcdbase)
 931 {
 932         int color_depth = 24;
 933         const char *video_mode = getenv("video_mode");
 934         const char *vm;
 935         unsigned long val;
 936         int refresh = 60;
 937         struct fb_videomode *p = &tx6_fb_modes[0];
 938         struct fb_videomode fb_mode;
 939         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 940         int pix_fmt = 0;
 941         ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
 942         unsigned long di_clk_rate = 65000000;
 943
 944         if (!lcd_enabled) {
 945                 debug("LCD disabled\n");
 946                 return;
 947         }
 948
 949         if (tstc() || (wrsr & WRSR_TOUT)) {
 950                 debug("Disabling LCD\n");
 951                 lcd_enabled = 0;
 952                 setenv("splashimage", NULL);
 953                 return;
 954         }
 955
 956         karo_fdt_move_fdt();
 957
 958         vm = karo_fdt_set_display(video_mode, "", "/soc/aips-bus/ldb");
 959         if (vm == NULL) {
 960                 debug("Disabling LCD\n");
 961                 lcd_enabled = 0;
 962                 return;
 963         }
 964         video_mode = vm;
 965         if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
 966                 p = &fb_mode;
 967                 debug("Using video mode from FDT\n");
 968                 vm += strlen(vm);
 969                 if (fb_mode.xres > panel_info.vl_col ||
 970                         fb_mode.yres > panel_info.vl_row) {
 971                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
 972                                 fb_mode.xres, fb_mode.yres,
 973                                 panel_info.vl_col, panel_info.vl_row);
 974                         lcd_enabled = 0;
 975                         return;
 976                 }
 977         }
 978         if (p->name != NULL)
 979                 debug("Trying compiled-in video modes\n");
 980         while (p->name != NULL) {
 981                 if (strcmp(p->name, vm) == 0) {
 982                         debug("Using video mode: '%s'\n", p->name);
 983                         vm += strlen(vm);
 984                         break;
 985                 }
 986                 p++;
 987         }
 988         if (*vm != '\0')
 989                 debug("Trying to decode video_mode: '%s'\n", vm);
 990         while (*vm != '\0') {
 991                 if (*vm >= '0' && *vm <= '9') {
 992                         char *end;
 993
 994                         val = simple_strtoul(vm, &end, 0);
 995                         if (end > vm) {
 996                                 if (!xres_set) {
 997                                         if (val > panel_info.vl_col)
 998                                                 val = panel_info.vl_col;
 999                                         p->xres = val;
1000                                         panel_info.vl_col = val;
1001                                         xres_set = 1;
1002                                 } else if (!yres_set) {
1003                                         if (val > panel_info.vl_row)
1004                                                 val = panel_info.vl_row;
1005                                         p->yres = val;
1006                                         panel_info.vl_row = val;
1007                                         yres_set = 1;
1008                                 } else if (!bpp_set) {
1009                                         switch (val) {
1010                                         case 32:
1011                                         case 24:
1012                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666)
1013                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
1014                                                 /* fallthru */
1015                                         case 16:
1016                                         case 8:
1017                                                 color_depth = val;
1018                                                 break;
1019
1020                                         case 18:
1021                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666) {
1022                                                         color_depth = val;
1023                                                         break;
1024                                                 }
1025                                                 /* fallthru */
1026                                         default:
1027                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1028                                                         end - vm, vm, color_depth);
1029                                         }
1030                                         bpp_set = 1;
1031                                 } else if (!refresh_set) {
1032                                         refresh = val;
1033                                         refresh_set = 1;
1034                                 }
1035                         }
1036                         vm = end;
1037                 }
1038                 switch (*vm) {
1039                 case '@':
1040                         bpp_set = 1;
1041                         /* fallthru */
1042                 case '-':
1043                         yres_set = 1;
1044                         /* fallthru */
1045                 case 'x':
1046                         xres_set = 1;
1047                         /* fallthru */
1048                 case 'M':
1049                 case 'R':
1050                         vm++;
1051                         break;
1052
1053                 default:
1054                         if (!pix_fmt) {
1055                                 char *tmp;
1056
1057                                 if (strncmp(vm, "LVDS", 4) == 0) {
1058                                         pix_fmt = IPU_PIX_FMT_LVDS666;
1059                                         di_clk_parent = DI_PCLK_LDB;
1060                                 } else {
1061                                         pix_fmt = IPU_PIX_FMT_RGB24;
1062                                 }
1063                                 tmp = strchr(vm, ':');
1064                                 if (tmp)
1065                                         vm = tmp;
1066                         }
1067                         if (*vm != '\0')
1068                                 vm++;
1069                 }
1070         }
1071         if (p->xres == 0 || p->yres == 0) {
1072                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1073                 lcd_enabled = 0;
1074                 printf("Supported video modes are:");
1075                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1076                         printf(" %s", p->name);
1077                 }
1078                 printf("\n");
1079                 return;
1080         }
1081         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1082                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1083                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1084                 lcd_enabled = 0;
1085                 return;
1086         }
1087         panel_info.vl_col = p->xres;
1088         panel_info.vl_row = p->yres;
1089
1090         switch (color_depth) {
1091         case 8:
1092                 panel_info.vl_bpix = LCD_COLOR8;
1093                 break;
1094         case 16:
1095                 panel_info.vl_bpix = LCD_COLOR16;
1096                 break;
1097         default:
1098                 panel_info.vl_bpix = LCD_COLOR24;
1099         }
1100
1101         p->pixclock = KHZ2PICOS(refresh *
1102                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1103                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
1104                 / 1000);
1105         debug("Pixel clock set to %lu.%03lu MHz\n",
1106                 PICOS2KHZ(p->pixclock) / 1000,
1107                 PICOS2KHZ(p->pixclock) % 1000);
1108
1109         if (p != &fb_mode) {
1110                 int ret;
1111
1112                 debug("Creating new display-timing node from '%s'\n",
1113                         video_mode);
1114                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1115                 if (ret)
1116                         printf("Failed to create new display-timing node from '%s': %d\n",
1117                                 video_mode, ret);
1118         }
1119
1120         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1121         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1122                                         ARRAY_SIZE(stk5_lcd_pads));
1123
1124         debug("Initializing FB driver\n");
1125         if (!pix_fmt)
1126                 pix_fmt = IPU_PIX_FMT_RGB24;
1127         else if (pix_fmt == IPU_PIX_FMT_LVDS666) {
1128                 writel(0x01, IOMUXC_BASE_ADDR + 8);
1129         } else if (pix_fmt == IPU_PIX_FMT_LVDS888) {
1130                 writel(0x21, IOMUXC_BASE_ADDR + 8);
1131         }
1132         if (pix_fmt != IPU_PIX_FMT_RGB24) {
1133                 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1134                 /* enable LDB & DI0 clock */
1135                 writel(readl(&ccm_regs->CCGR3) | MXC_CCM_CCGR3_LDB_DI0_MASK |
1136                         MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK,
1137                         &ccm_regs->CCGR3);
1138         }
1139
1140         if (karo_load_splashimage(0) == 0) {
1141                 debug("Initializing LCD controller\n");
1142                 ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
1143         } else {
1144                 debug("Skipping initialization of LCD controller\n");
1145         }
1146 }
1147 #else
1148 #define lcd_enabled 0
1149 #endif /* CONFIG_LCD */
1150
1151 static void stk5_board_init(void)
1152 {
1153         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1154         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1155 }
1156
1157 static void stk5v3_board_init(void)
1158 {
1159         stk5_board_init();
1160 }
1161
1162 static void stk5v5_board_init(void)
1163 {
1164         stk5_board_init();
1165
1166         gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
1167                         "Flexcan Transceiver");
1168         imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO_4_21);
1169 }
1170
1171 static void tx6qdl_set_cpu_clock(void)
1172 {
1173         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1174
1175         if (tstc() || (wrsr & WRSR_TOUT))
1176                 return;
1177
1178         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1179                 return;
1180
1181         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1182                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1183                 printf("CPU clock set to %lu.%03lu MHz\n",
1184                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1185         } else {
1186                 printf("Failed to set CPU clock to %lu MHz\n", cpu_clk);
1187         }
1188 }
1189
1190 static void tx6_init_mac(void)
1191 {
1192         u8 mac[ETH_ALEN];
1193
1194         imx_get_mac_from_fuse(-1, mac);
1195         if (!is_valid_ether_addr(mac)) {
1196                 printf("No valid MAC address programmed\n");
1197                 return;
1198         }
1199
1200         eth_setenv_enetaddr("ethaddr", mac);
1201         printf("MAC addr from fuse: %pM\n", mac);
1202 }
1203
1204 int board_late_init(void)
1205 {
1206         int ret = 0;
1207         const char *baseboard;
1208
1209         tx6qdl_set_cpu_clock();
1210         karo_fdt_move_fdt();
1211
1212         baseboard = getenv("baseboard");
1213         if (!baseboard)
1214                 goto exit;
1215
1216         printf("Baseboard: %s\n", baseboard);
1217
1218         if (strncmp(baseboard, "stk5", 4) == 0) {
1219                 if ((strlen(baseboard) == 4) ||
1220                         strcmp(baseboard, "stk5-v3") == 0) {
1221                         stk5v3_board_init();
1222                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1223                         const char *otg_mode = getenv("otg_mode");
1224
1225                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1226                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1227                                         otg_mode, baseboard);
1228                                 setenv("otg_mode", "none");
1229                         }
1230                         stk5v5_board_init();
1231                 } else {
1232                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1233                                 baseboard + 4);
1234                 }
1235         } else {
1236                 printf("WARNING: Unsupported baseboard: '%s'\n",
1237                         baseboard);
1238                 ret = -EINVAL;
1239         }
1240
1241 exit:
1242         tx6_init_mac();
1243
1244         gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1245         return ret;
1246 }
1247
1248 int checkboard(void)
1249 {
1250         u32 cpurev = get_cpu_rev();
1251         int cpu_variant = (cpurev >> 12) & 0xff;
1252
1253         tx6qdl_print_cpuinfo();
1254
1255         printf("Board: Ka-Ro TX6%c-%dx1%d\n",
1256                 cpu_variant == MXC_CPU_MX6Q ? 'Q' : 'U',
1257                 cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
1258                 1 - PHYS_SDRAM_1_WIDTH / 64);
1259
1260         return 0;
1261 }
1262
1263 #ifdef CONFIG_SERIAL_TAG
1264 void get_board_serial(struct tag_serialnr *serialnr)
1265 {
1266         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1267         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1268
1269         serialnr->low = readl(&fuse->cfg0);
1270         serialnr->high = readl(&fuse->cfg1);
1271 }
1272 #endif
1273
1274 #if defined(CONFIG_OF_BOARD_SETUP)
1275 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1276 #include <jffs2/jffs2.h>
1277 #include <mtd_node.h>
1278 struct node_info nodes[] = {
1279         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1280 };
1281
1282 #else
1283 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1284 #endif
1285
1286 void ft_board_setup(void *blob, bd_t *bd)
1287 {
1288         const char *baseboard = getenv("baseboard");
1289         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1290         const char *video_mode = getenv("video_mode");
1291
1292         karo_fdt_enable_node(blob, "stk5led", !stk5_v5);
1293
1294         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1295         fdt_fixup_ethernet(blob);
1296
1297         karo_fdt_fixup_touchpanel(blob);
1298         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy");
1299         karo_fdt_fixup_flexcan(blob, stk5_v5);
1300
1301         video_mode = karo_fdt_set_display(video_mode, "", "/soc/aips-bus/ldb");
1302         karo_fdt_update_fb_mode(blob, video_mode);
1303 }
1304 #endif /* CONFIG_OF_BOARD_SETUP */