fdt: karo: add support for LVDS selection via 'video_mode'
[karo-tx-uboot.git] / board / karo / tx6 / tx6qdl.c
1 /*
2  * Copyright (C) 2012,2013 Lothar WaƟmann <LW@KARO-electronics.de>
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License
9  * version 2 as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17
18 #include <common.h>
19 #include <errno.h>
20 #include <libfdt.h>
21 #include <fdt_support.h>
22 #include <lcd.h>
23 #include <netdev.h>
24 #include <mmc.h>
25 #include <fsl_esdhc.h>
26 #include <video_fb.h>
27 #include <ipu.h>
28 #include <mxcfb.h>
29 #include <i2c.h>
30 #include <linux/fb.h>
31 #include <asm/io.h>
32 #include <asm/gpio.h>
33 #include <asm/arch/mx6-pins.h>
34 #include <asm/arch/clock.h>
35 #include <asm/arch/imx-regs.h>
36 #include <asm/arch/crm_regs.h>
37 #include <asm/arch/sys_proto.h>
38
39 #include "../common/karo.h"
40
41 #define TX6_FEC_RST_GPIO                IMX_GPIO_NR(7, 6)
42 #define TX6_FEC_PWR_GPIO                IMX_GPIO_NR(3, 20)
43 #define TX6_FEC_INT_GPIO                IMX_GPIO_NR(2, 4)
44 #define TX6_LED_GPIO                    IMX_GPIO_NR(2, 20)
45
46 #define TX6_LCD_PWR_GPIO                IMX_GPIO_NR(2, 31)
47 #define TX6_LCD_RST_GPIO                IMX_GPIO_NR(3, 29)
48 #define TX6_LCD_BACKLIGHT_GPIO          IMX_GPIO_NR(1, 1)
49
50 #define TX6_RESET_OUT_GPIO              IMX_GPIO_NR(7, 12)
51
52 #define TEMPERATURE_MIN                 -40
53 #define TEMPERATURE_HOT                 80
54 #define TEMPERATURE_MAX                 125
55
56 DECLARE_GLOBAL_DATA_PTR;
57
58 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
59
60 static const iomux_v3_cfg_t tx6qdl_pads[] = {
61         /* NAND flash pads */
62         MX6_PAD_NANDF_CLE__RAWNAND_CLE,
63         MX6_PAD_NANDF_ALE__RAWNAND_ALE,
64         MX6_PAD_NANDF_WP_B__RAWNAND_RESETN,
65         MX6_PAD_NANDF_RB0__RAWNAND_READY0,
66         MX6_PAD_NANDF_CS0__RAWNAND_CE0N,
67         MX6_PAD_SD4_CMD__RAWNAND_RDN,
68         MX6_PAD_SD4_CLK__RAWNAND_WRN,
69         MX6_PAD_NANDF_D0__RAWNAND_D0,
70         MX6_PAD_NANDF_D1__RAWNAND_D1,
71         MX6_PAD_NANDF_D2__RAWNAND_D2,
72         MX6_PAD_NANDF_D3__RAWNAND_D3,
73         MX6_PAD_NANDF_D4__RAWNAND_D4,
74         MX6_PAD_NANDF_D5__RAWNAND_D5,
75         MX6_PAD_NANDF_D6__RAWNAND_D6,
76         MX6_PAD_NANDF_D7__RAWNAND_D7,
77
78         /* RESET_OUT */
79         MX6_PAD_GPIO_17__GPIO_7_12,
80
81         /* UART pads */
82 #if CONFIG_MXC_UART_BASE == UART1_BASE
83         MX6_PAD_SD3_DAT7__UART1_TXD,
84         MX6_PAD_SD3_DAT6__UART1_RXD,
85         MX6_PAD_SD3_DAT1__UART1_RTS,
86         MX6_PAD_SD3_DAT0__UART1_CTS,
87 #endif
88 #if CONFIG_MXC_UART_BASE == UART2_BASE
89         MX6_PAD_SD4_DAT4__UART2_RXD,
90         MX6_PAD_SD4_DAT7__UART2_TXD,
91         MX6_PAD_SD4_DAT5__UART2_RTS,
92         MX6_PAD_SD4_DAT6__UART2_CTS,
93 #endif
94 #if CONFIG_MXC_UART_BASE == UART3_BASE
95         MX6_PAD_EIM_D24__UART3_TXD,
96         MX6_PAD_EIM_D25__UART3_RXD,
97         MX6_PAD_SD3_RST__UART3_RTS,
98         MX6_PAD_SD3_DAT3__UART3_CTS,
99 #endif
100         /* internal I2C */
101         MX6_PAD_EIM_D28__I2C1_SDA,
102         MX6_PAD_EIM_D21__I2C1_SCL,
103
104         /* FEC PHY GPIO functions */
105         MX6_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */
106         MX6_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */
107         MX6_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */
108 };
109
110 static const iomux_v3_cfg_t tx6qdl_fec_pads[] = {
111         /* FEC functions */
112         MX6_PAD_ENET_MDC__ENET_MDC,
113         MX6_PAD_ENET_MDIO__ENET_MDIO,
114         MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
115         MX6_PAD_ENET_RX_ER__ENET_RX_ER,
116         MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
117         MX6_PAD_ENET_RXD1__ENET_RDATA_1,
118         MX6_PAD_ENET_RXD0__ENET_RDATA_0,
119         MX6_PAD_ENET_TX_EN__ENET_TX_EN,
120         MX6_PAD_ENET_TXD1__ENET_TDATA_1,
121         MX6_PAD_ENET_TXD0__ENET_TDATA_0,
122 };
123
124 static const struct gpio tx6qdl_gpios[] = {
125         { TX6_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
126         { TX6_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
127         { TX6_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
128         { TX6_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
129 };
130
131 /*
132  * Functions
133  */
134 /* placed in section '.data' to prevent overwriting relocation info
135  * overlayed with bss
136  */
137 static u32 wrsr __attribute__((section(".data")));
138
139 #define WRSR_POR                        (1 << 4)
140 #define WRSR_TOUT                       (1 << 1)
141 #define WRSR_SFTW                       (1 << 0)
142
143 static void print_reset_cause(void)
144 {
145         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
146         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
147         u32 srsr;
148         char *dlm = "";
149
150         printf("Reset cause: ");
151
152         srsr = readl(&src_regs->srsr);
153         wrsr = readw(wdt_base + 4);
154
155         if (wrsr & WRSR_POR) {
156                 printf("%sPOR", dlm);
157                 dlm = " | ";
158         }
159         if (srsr & 0x00004) {
160                 printf("%sCSU", dlm);
161                 dlm = " | ";
162         }
163         if (srsr & 0x00008) {
164                 printf("%sIPP USER", dlm);
165                 dlm = " | ";
166         }
167         if (srsr & 0x00010) {
168                 if (wrsr & WRSR_SFTW) {
169                         printf("%sSOFT", dlm);
170                         dlm = " | ";
171                 }
172                 if (wrsr & WRSR_TOUT) {
173                         printf("%sWDOG", dlm);
174                         dlm = " | ";
175                 }
176         }
177         if (srsr & 0x00020) {
178                 printf("%sJTAG HIGH-Z", dlm);
179                 dlm = " | ";
180         }
181         if (srsr & 0x00040) {
182                 printf("%sJTAG SW", dlm);
183                 dlm = " | ";
184         }
185         if (srsr & 0x10000) {
186                 printf("%sWARM BOOT", dlm);
187                 dlm = " | ";
188         }
189         if (dlm[0] == '\0')
190                 printf("unknown");
191
192         printf("\n");
193 }
194
195 int read_cpu_temperature(void);
196 int check_cpu_temperature(int boot);
197
198 static void tx6qdl_print_cpuinfo(void)
199 {
200         u32 cpurev = get_cpu_rev();
201         char *cpu_str = "?";
202
203         switch ((cpurev >> 12) & 0xff) {
204         case MXC_CPU_MX6SL:
205                 cpu_str = "SL";
206                 break;
207         case MXC_CPU_MX6DL:
208                 cpu_str = "DL";
209                 break;
210         case MXC_CPU_MX6SOLO:
211                 cpu_str = "SOLO";
212                 break;
213         case MXC_CPU_MX6Q:
214                 cpu_str = "Q";
215                 break;
216         }
217
218         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
219                 cpu_str,
220                 (cpurev & 0x000F0) >> 4,
221                 (cpurev & 0x0000F) >> 0,
222                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
223
224         print_reset_cause();
225         check_cpu_temperature(1);
226 }
227
228 #define LTC3676_DVB2A           0x0C
229 #define LTC3676_DVB2B           0x0D
230 #define LTC3676_DVB4A           0x10
231 #define LTC3676_DVB4B           0x11
232
233 #define VDD_SOC_mV              (1375 + 50)
234 #define VDD_CORE_mV             (1375 + 50)
235
236 #define mV_to_regval(mV)        (((mV) * 360 / 330 - 825 + 1) / 25)
237 #define regval_to_mV(v)         (((v) * 25 + 825) * 330 / 360)
238
239 static int setup_pmic_voltages(void)
240 {
241         int ret;
242         unsigned char value;
243
244         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
245
246         ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
247         if (ret != 0) {
248                 printf("Failed to initialize I2C\n");
249                 return ret;
250         }
251
252         ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
253         if (ret) {
254                 printf("%s: i2c_read error: %d\n", __func__, ret);
255                 return ret;
256         }
257
258         /* VDDCORE/VDDSOC default 1.375V is not enough, considering
259            pfuze tolerance and IR drop and ripple, need increase
260            to 1.425V for SabreSD */
261
262         value = 0x39; /* VB default value & PGOOD not forced when slewing */
263         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB2B, 1, &value, 1);
264         if (ret) {
265                 printf("%s: failed to write PMIC DVB2B register: %d\n",
266                         __func__, ret);
267                 return ret;
268         }
269         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB4B, 1, &value, 1);
270         if (ret) {
271                 printf("%s: failed to write PMIC DVB4B register: %d\n",
272                         __func__, ret);
273                 return ret;
274         }
275
276         value = mV_to_regval(VDD_SOC_mV);
277         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB2A, 1, &value, 1);
278         if (ret) {
279                 printf("%s: failed to write PMIC DVB2A register: %d\n",
280                         __func__, ret);
281                 return ret;
282         }
283         printf("VDDSOC  set to %dmV\n", regval_to_mV(value));
284
285         value = mV_to_regval(VDD_CORE_mV);
286         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB4A, 1, &value, 1);
287         if (ret) {
288                 printf("%s: failed to write PMIC DVB4A register: %d\n",
289                         __func__, ret);
290                 return ret;
291         }
292         printf("VDDCORE set to %dmV\n", regval_to_mV(value));
293         return 0;
294 }
295
296 int board_early_init_f(void)
297 {
298         gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
299         imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
300
301         return 0;
302 }
303
304 int board_init(void)
305 {
306         int ret;
307
308         /* Address of boot parameters */
309         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
310 #ifdef CONFIG_OF_LIBFDT
311         gd->bd->bi_arch_number = -1;
312 #else
313         gd->bd->bi_arch_number = 4429;
314 #endif
315         ret = setup_pmic_voltages();
316         if (ret) {
317                 printf("Failed to setup PMIC voltages\n");
318                 hang();
319         }
320         return 0;
321 }
322
323 int dram_init(void)
324 {
325         /* dram_init must store complete ramsize in gd->ram_size */
326         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
327                                 PHYS_SDRAM_1_SIZE);
328         return 0;
329 }
330
331 void dram_init_banksize(void)
332 {
333         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
334         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
335                         PHYS_SDRAM_1_SIZE);
336 #if CONFIG_NR_DRAM_BANKS > 1
337         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
338         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
339                         PHYS_SDRAM_2_SIZE);
340 #endif
341 }
342
343 #ifdef  CONFIG_CMD_MMC
344 static const iomux_v3_cfg_t mmc0_pads[] = {
345         MX6_PAD_SD1_CMD__USDHC1_CMD,
346         MX6_PAD_SD1_CLK__USDHC1_CLK,
347         MX6_PAD_SD1_DAT0__USDHC1_DAT0,
348         MX6_PAD_SD1_DAT1__USDHC1_DAT1,
349         MX6_PAD_SD1_DAT2__USDHC1_DAT2,
350         MX6_PAD_SD1_DAT3__USDHC1_DAT3,
351         /* SD1 CD */
352         MX6_PAD_SD3_CMD__GPIO_7_2,
353 };
354
355 static const iomux_v3_cfg_t mmc1_pads[] = {
356         MX6_PAD_SD2_CMD__USDHC2_CMD,
357         MX6_PAD_SD2_CLK__USDHC2_CLK,
358         MX6_PAD_SD2_DAT0__USDHC2_DAT0,
359         MX6_PAD_SD2_DAT1__USDHC2_DAT1,
360         MX6_PAD_SD2_DAT2__USDHC2_DAT2,
361         MX6_PAD_SD2_DAT3__USDHC2_DAT3,
362         /* SD2 CD */
363         MX6_PAD_SD3_CLK__GPIO_7_3,
364 };
365
366 static struct tx6_esdhc_cfg {
367         const iomux_v3_cfg_t *pads;
368         int num_pads;
369         enum mxc_clock clkid;
370         struct fsl_esdhc_cfg cfg;
371         int cd_gpio;
372 } tx6qdl_esdhc_cfg[] = {
373         {
374                 .pads = mmc0_pads,
375                 .num_pads = ARRAY_SIZE(mmc0_pads),
376                 .clkid = MXC_ESDHC_CLK,
377                 .cfg = {
378                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
379                         .max_bus_width = 4,
380                 },
381                 .cd_gpio = IMX_GPIO_NR(7, 2),
382         },
383         {
384                 .pads = mmc1_pads,
385                 .num_pads = ARRAY_SIZE(mmc1_pads),
386                 .clkid = MXC_ESDHC2_CLK,
387                 .cfg = {
388                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
389                         .max_bus_width = 4,
390                 },
391                 .cd_gpio = IMX_GPIO_NR(7, 3),
392         },
393 };
394
395 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
396 {
397         void *p = cfg;
398
399         return p - offsetof(struct tx6_esdhc_cfg, cfg);
400 }
401
402 int board_mmc_getcd(struct mmc *mmc)
403 {
404         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
405
406         if (cfg->cd_gpio < 0)
407                 return cfg->cd_gpio;
408
409         debug("SD card %d is %spresent\n",
410                 cfg - tx6qdl_esdhc_cfg,
411                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
412         return !gpio_get_value(cfg->cd_gpio);
413 }
414
415 int board_mmc_init(bd_t *bis)
416 {
417         int i;
418
419         for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
420                 struct mmc *mmc;
421                 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
422                 int ret;
423
424                 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
425                         break;
426
427                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
428                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
429
430                 ret = gpio_request_one(cfg->cd_gpio,
431                                 GPIOF_INPUT, "MMC CD");
432                 if (ret) {
433                         printf("Error %d requesting GPIO%d_%d\n",
434                                 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
435                         continue;
436                 }
437
438                 debug("%s: Initializing MMC slot %d\n", __func__, i);
439                 fsl_esdhc_initialize(bis, &cfg->cfg);
440
441                 mmc = find_mmc_device(i);
442                 if (mmc == NULL)
443                         continue;
444                 if (board_mmc_getcd(mmc) > 0)
445                         mmc_init(mmc);
446         }
447         return 0;
448 }
449 #endif /* CONFIG_CMD_MMC */
450
451 #ifdef CONFIG_FEC_MXC
452
453 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
454                         PAD_CTL_SRE_FAST)
455 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
456 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
457
458 #ifndef ETH_ALEN
459 #define ETH_ALEN 6
460 #endif
461
462 int board_eth_init(bd_t *bis)
463 {
464         int ret;
465
466         /* delay at least 21ms for the PHY internal POR signal to deassert */
467         udelay(22000);
468
469         imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads, ARRAY_SIZE(tx6qdl_fec_pads));
470
471         /* Deassert RESET to the external phy */
472         gpio_set_value(TX6_FEC_RST_GPIO, 1);
473
474         ret = cpu_eth_init(bis);
475         if (ret)
476                 printf("cpu_eth_init() failed: %d\n", ret);
477
478         return ret;
479 }
480 #endif /* CONFIG_FEC_MXC */
481
482 enum {
483         LED_STATE_INIT = -1,
484         LED_STATE_OFF,
485         LED_STATE_ON,
486 };
487
488 static inline int calc_blink_rate(int tmp)
489 {
490         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
491                 (tmp - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
492                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
493 }
494
495 void show_activity(int arg)
496 {
497         static int led_state = LED_STATE_INIT;
498         static int blink_rate;
499         static ulong last;
500
501         if (led_state == LED_STATE_INIT) {
502                 last = get_timer(0);
503                 gpio_set_value(TX6_LED_GPIO, 1);
504                 led_state = LED_STATE_ON;
505                 blink_rate = calc_blink_rate(check_cpu_temperature(0));
506         } else {
507                 if (get_timer(last) > blink_rate) {
508                         blink_rate = calc_blink_rate(check_cpu_temperature(0));
509                         last = get_timer_masked();
510                         if (led_state == LED_STATE_ON) {
511                                 gpio_set_value(TX6_LED_GPIO, 0);
512                         } else {
513                                 gpio_set_value(TX6_LED_GPIO, 1);
514                         }
515                         led_state = 1 - led_state;
516                 }
517         }
518 }
519
520 static const iomux_v3_cfg_t stk5_pads[] = {
521         /* SW controlled LED on STK5 baseboard */
522         MX6_PAD_EIM_A18__GPIO_2_20,
523
524         /* LCD data pins */
525         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
526         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
527         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
528         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
529         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
530         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
531         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
532         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
533         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
534         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
535         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
536         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
537         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
538         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
539         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
540         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
541         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
542         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
543         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
544         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
545         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
546         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
547         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
548         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
549         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */
550         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */
551         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
552         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
553
554         /* I2C bus on DIMM pins 40/41 */
555         MX6_PAD_GPIO_6__I2C3_SDA,
556         MX6_PAD_GPIO_3__I2C3_SCL,
557
558         /* TSC200x PEN IRQ */
559         MX6_PAD_EIM_D26__GPIO_3_26,
560
561         /* EDT-FT5x06 Polytouch panel */
562         MX6_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */
563         MX6_PAD_EIM_A16__GPIO_2_22, /* RESET */
564         MX6_PAD_EIM_A17__GPIO_2_21, /* WAKE */
565
566         /* USBH1 */
567         MX6_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */
568         MX6_PAD_EIM_D30__GPIO_3_30, /* OC */
569         /* USBOTG */
570         MX6_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */
571         MX6_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */
572         MX6_PAD_GPIO_8__GPIO_1_8, /* OC */
573 };
574
575 static const struct gpio stk5_gpios[] = {
576         { TX6_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
577
578         { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", },
579         { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
580         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
581         { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
582         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
583 };
584
585 #ifdef CONFIG_LCD
586 vidinfo_t panel_info = {
587         /* set to max. size supported by SoC */
588         .vl_col = 1920,
589         .vl_row = 1080,
590
591         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
592 };
593
594 static struct fb_videomode tx6_fb_modes[] = {
595         {
596                 /* Standard VGA timing */
597                 .name           = "VGA",
598                 .refresh        = 60,
599                 .xres           = 640,
600                 .yres           = 480,
601                 .pixclock       = KHZ2PICOS(25175),
602                 .left_margin    = 48,
603                 .hsync_len      = 96,
604                 .right_margin   = 16,
605                 .upper_margin   = 31,
606                 .vsync_len      = 2,
607                 .lower_margin   = 12,
608                 .sync           = FB_SYNC_CLK_LAT_FALL,
609         },
610         {
611                 /* Emerging ETV570 640 x 480 display. Syncs low active,
612                  * DE high active, 115.2 mm x 86.4 mm display area
613                  * VGA compatible timing
614                  */
615                 .name           = "ETV570",
616                 .refresh        = 60,
617                 .xres           = 640,
618                 .yres           = 480,
619                 .pixclock       = KHZ2PICOS(25175),
620                 .left_margin    = 114,
621                 .hsync_len      = 30,
622                 .right_margin   = 16,
623                 .upper_margin   = 32,
624                 .vsync_len      = 3,
625                 .lower_margin   = 10,
626                 .sync           = FB_SYNC_CLK_LAT_FALL,
627         },
628         {
629                 /* Emerging ET0350G0DH6 320 x 240 display.
630                  * 70.08 mm x 52.56 mm display area.
631                  */
632                 .name           = "ET0350",
633                 .refresh        = 60,
634                 .xres           = 320,
635                 .yres           = 240,
636                 .pixclock       = KHZ2PICOS(6500),
637                 .left_margin    = 68 - 34,
638                 .hsync_len      = 34,
639                 .right_margin   = 20,
640                 .upper_margin   = 18 - 3,
641                 .vsync_len      = 3,
642                 .lower_margin   = 4,
643                 .sync           = FB_SYNC_CLK_LAT_FALL,
644         },
645         {
646                 /* Emerging ET0430G0DH6 480 x 272 display.
647                  * 95.04 mm x 53.856 mm display area.
648                  */
649                 .name           = "ET0430",
650                 .refresh        = 60,
651                 .xres           = 480,
652                 .yres           = 272,
653                 .pixclock       = KHZ2PICOS(9000),
654                 .left_margin    = 2,
655                 .hsync_len      = 41,
656                 .right_margin   = 2,
657                 .upper_margin   = 2,
658                 .vsync_len      = 10,
659                 .lower_margin   = 2,
660                 .sync           = FB_SYNC_CLK_LAT_FALL,
661         },
662         {
663                 /* Emerging ET0500G0DH6 800 x 480 display.
664                  * 109.6 mm x 66.4 mm display area.
665                  */
666                 .name           = "ET0500",
667                 .refresh        = 60,
668                 .xres           = 800,
669                 .yres           = 480,
670                 .pixclock       = KHZ2PICOS(33260),
671                 .left_margin    = 216 - 128,
672                 .hsync_len      = 128,
673                 .right_margin   = 1056 - 800 - 216,
674                 .upper_margin   = 35 - 2,
675                 .vsync_len      = 2,
676                 .lower_margin   = 525 - 480 - 35,
677                 .sync           = FB_SYNC_CLK_LAT_FALL,
678         },
679         {
680                 /* Emerging ETQ570G0DH6 320 x 240 display.
681                  * 115.2 mm x 86.4 mm display area.
682                  */
683                 .name           = "ETQ570",
684                 .refresh        = 60,
685                 .xres           = 320,
686                 .yres           = 240,
687                 .pixclock       = KHZ2PICOS(6400),
688                 .left_margin    = 38,
689                 .hsync_len      = 30,
690                 .right_margin   = 30,
691                 .upper_margin   = 16, /* 15 according to datasheet */
692                 .vsync_len      = 3, /* TVP -> 1>x>5 */
693                 .lower_margin   = 4, /* 4.5 according to datasheet */
694                 .sync           = FB_SYNC_CLK_LAT_FALL,
695         },
696         {
697                 /* Emerging ET0700G0DH6 800 x 480 display.
698                  * 152.4 mm x 91.44 mm display area.
699                  */
700                 .name           = "ET0700",
701                 .refresh        = 60,
702                 .xres           = 800,
703                 .yres           = 480,
704                 .pixclock       = KHZ2PICOS(33260),
705                 .left_margin    = 216 - 128,
706                 .hsync_len      = 128,
707                 .right_margin   = 1056 - 800 - 216,
708                 .upper_margin   = 35 - 2,
709                 .vsync_len      = 2,
710                 .lower_margin   = 525 - 480 - 35,
711                 .sync           = FB_SYNC_CLK_LAT_FALL,
712         },
713         {
714                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
715                 .refresh        = 60,
716                 .left_margin    = 48,
717                 .hsync_len      = 96,
718                 .right_margin   = 16,
719                 .upper_margin   = 31,
720                 .vsync_len      = 2,
721                 .lower_margin   = 12,
722                 .sync           = FB_SYNC_CLK_LAT_FALL,
723         },
724 };
725
726 static int lcd_enabled = 1;
727
728 void lcd_enable(void)
729 {
730         /* HACK ALERT:
731          * global variable from common/lcd.c
732          * Set to 0 here to prevent messages from going to LCD
733          * rather than serial console
734          */
735         lcd_is_enabled = 0;
736
737         karo_load_splashimage(1);
738
739         if (lcd_enabled) {
740                 debug("Switching LCD on\n");
741                 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
742                 udelay(100);
743                 gpio_set_value(TX6_LCD_RST_GPIO, 1);
744                 udelay(300000);
745                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, 0);
746         }
747 }
748
749 void lcd_disable(void)
750 {
751         if (lcd_enabled) {
752                 printf("Disabling LCD\n");
753                 ipuv3_fb_shutdown();
754         }
755 }
756
757 void lcd_panel_disable(void)
758 {
759         if (lcd_enabled) {
760                 debug("Switching LCD off\n");
761                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, 1);
762                 gpio_set_value(TX6_LCD_RST_GPIO, 0);
763                 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
764         }
765 }
766
767 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
768         /* LCD RESET */
769         MX6_PAD_EIM_D29__GPIO_3_29,
770         /* LCD POWER_ENABLE */
771         MX6_PAD_EIM_EB3__GPIO_2_31,
772         /* LCD Backlight (PWM) */
773         MX6_PAD_GPIO_1__GPIO_1_1,
774
775         /* Display */
776         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
777         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
778         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
779         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
780         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
781         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
782         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
783         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
784         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
785         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
786         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
787         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
788         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
789         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
790         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
791         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
792         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
793         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
794         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
795         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
796         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
797         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
798         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
799         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
800         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
801         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
802         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
803         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
804 };
805
806 static const struct gpio stk5_lcd_gpios[] = {
807         { TX6_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
808         { TX6_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
809         { TX6_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
810 };
811
812 void lcd_ctrl_init(void *lcdbase)
813 {
814         int color_depth = 24;
815         char *video_mode = getenv("video_mode");
816         char *vm;
817         unsigned long val;
818         int refresh = 60;
819         struct fb_videomode *p = &tx6_fb_modes[0];
820         struct fb_videomode fb_mode;
821         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
822         int pix_fmt = 0;
823         ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
824         unsigned long di_clk_rate = 65000000;
825
826         if (!lcd_enabled) {
827                 debug("LCD disabled\n");
828                 return;
829         }
830
831         if (tstc() || (wrsr & WRSR_TOUT)) {
832                 debug("Disabling LCD\n");
833                 lcd_enabled = 0;
834                 setenv("splashimage", NULL);
835                 return;
836         }
837
838         karo_fdt_move_fdt();
839
840         vm = karo_fdt_set_display(video_mode, "", "/soc/aips-bus/ldb");
841         if (vm == NULL) {
842                 debug("Disabling LCD\n");
843                 lcd_enabled = 0;
844                 return;
845         }
846         video_mode = vm;
847         if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
848                 p = &fb_mode;
849                 debug("Using video mode from FDT\n");
850                 vm += strlen(vm);
851                 if (fb_mode.xres > panel_info.vl_col ||
852                         fb_mode.yres > panel_info.vl_row) {
853                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
854                                 fb_mode.xres, fb_mode.yres,
855                                 panel_info.vl_col, panel_info.vl_row);
856                         lcd_enabled = 0;
857                         return;
858                 }
859         }
860         if (p->name != NULL)
861                 debug("Trying compiled-in video modes\n");
862         while (p->name != NULL) {
863                 if (strcmp(p->name, vm) == 0) {
864                         debug("Using video mode: '%s'\n", p->name);
865                         vm += strlen(vm);
866                         break;
867                 }
868                 p++;
869         }
870         if (*vm != '\0')
871                 debug("Trying to decode video_mode: '%s'\n", vm);
872         while (*vm != '\0') {
873                 if (*vm >= '0' && *vm <= '9') {
874                         char *end;
875
876                         val = simple_strtoul(vm, &end, 0);
877                         if (end > vm) {
878                                 if (!xres_set) {
879                                         if (val > panel_info.vl_col)
880                                                 val = panel_info.vl_col;
881                                         p->xres = val;
882                                         panel_info.vl_col = val;
883                                         xres_set = 1;
884                                 } else if (!yres_set) {
885                                         if (val > panel_info.vl_row)
886                                                 val = panel_info.vl_row;
887                                         p->yres = val;
888                                         panel_info.vl_row = val;
889                                         yres_set = 1;
890                                 } else if (!bpp_set) {
891                                         switch (val) {
892                                         case 32:
893                                         case 24:
894                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666)
895                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
896                                                 /* fallthru */
897                                         case 16:
898                                         case 8:
899                                                 color_depth = val;
900                                                 break;
901
902                                         case 18:
903                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666) {
904                                                         color_depth = val;
905                                                         break;
906                                                 }
907                                                 /* fallthru */
908                                         default:
909                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
910                                                         end - vm, vm, color_depth);
911                                         }
912                                         bpp_set = 1;
913                                 } else if (!refresh_set) {
914                                         refresh = val;
915                                         refresh_set = 1;
916                                 }
917                         }
918                         vm = end;
919                 }
920                 switch (*vm) {
921                 case '@':
922                         bpp_set = 1;
923                         /* fallthru */
924                 case '-':
925                         yres_set = 1;
926                         /* fallthru */
927                 case 'x':
928                         xres_set = 1;
929                         /* fallthru */
930                 case 'M':
931                 case 'R':
932                         vm++;
933                         break;
934
935                 default:
936                         if (!pix_fmt) {
937                                 char *tmp;
938
939                                 if (strncmp(vm, "LVDS", 4) == 0) {
940                                         pix_fmt = IPU_PIX_FMT_LVDS666;
941                                         di_clk_parent = DI_PCLK_LDB;
942                                 } else {
943                                         pix_fmt = IPU_PIX_FMT_RGB24;
944                                 }
945                                 tmp = strchr(vm, ':');
946                                 if (tmp)
947                                         vm = tmp;
948                         }
949                         if (*vm != '\0')
950                                 vm++;
951                 }
952         }
953         if (p->xres == 0 || p->yres == 0) {
954                 printf("Invalid video mode: %s\n", getenv("video_mode"));
955                 lcd_enabled = 0;
956                 printf("Supported video modes are:");
957                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
958                         printf(" %s", p->name);
959                 }
960                 printf("\n");
961                 return;
962         }
963         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
964                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
965                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
966                 lcd_enabled = 0;
967                 return;
968         }
969         panel_info.vl_col = p->xres;
970         panel_info.vl_row = p->yres;
971
972         switch (color_depth) {
973         case 8:
974                 panel_info.vl_bpix = LCD_COLOR8;
975                 break;
976         case 16:
977                 panel_info.vl_bpix = LCD_COLOR16;
978                 break;
979         default:
980                 panel_info.vl_bpix = LCD_COLOR24;
981         }
982
983         p->pixclock = KHZ2PICOS(refresh *
984                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
985                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
986                 / 1000);
987         debug("Pixel clock set to %lu.%03lu MHz\n",
988                 PICOS2KHZ(p->pixclock) / 1000,
989                 PICOS2KHZ(p->pixclock) % 1000);
990
991         if (p != &fb_mode) {
992                 int ret;
993
994                 printf("Creating new display-timing node from '%s'\n",
995                         video_mode);
996                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
997                 if (ret)
998                         printf("Failed to create new display-timing node from '%s': %d\n",
999                                 video_mode, ret);
1000         }
1001
1002         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1003         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1004                                         ARRAY_SIZE(stk5_lcd_pads));
1005
1006         debug("Initializing FB driver\n");
1007         if (!pix_fmt)
1008                 pix_fmt = IPU_PIX_FMT_RGB24;
1009         else if (pix_fmt == IPU_PIX_FMT_LVDS666) {
1010                 writel(0x01, IOMUXC_BASE_ADDR + 8);
1011         } else if (pix_fmt == IPU_PIX_FMT_LVDS888) {
1012                 writel(0x21, IOMUXC_BASE_ADDR + 8);
1013         }
1014         if (pix_fmt != IPU_PIX_FMT_RGB24) {
1015                 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1016                 /* enable LDB & DI0 clock */
1017                 writel(readl(&ccm_regs->CCGR3) | MXC_CCM_CCGR3_LDB_DI0_MASK |
1018                         MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK,
1019                         &ccm_regs->CCGR3);
1020         }
1021
1022         if (karo_load_splashimage(0) == 0) {
1023                 debug("Initializing LCD controller\n");
1024                 ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
1025         } else {
1026                 debug("Skipping initialization of LCD controller\n");
1027         }
1028 }
1029 #else
1030 #define lcd_enabled 0
1031 #endif /* CONFIG_LCD */
1032
1033 static void stk5_board_init(void)
1034 {
1035         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1036         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1037 }
1038
1039 static void stk5v3_board_init(void)
1040 {
1041         stk5_board_init();
1042 }
1043
1044 static void stk5v5_board_init(void)
1045 {
1046         stk5_board_init();
1047
1048         gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
1049                         "Flexcan Transceiver");
1050         imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO_4_21);
1051 }
1052
1053 static void tx6qdl_set_cpu_clock(void)
1054 {
1055         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1056
1057         if (tstc() || (wrsr & WRSR_TOUT))
1058                 return;
1059
1060         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1061                 return;
1062
1063         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1064                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1065                 printf("CPU clock set to %lu.%03lu MHz\n",
1066                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1067         } else {
1068                 printf("Failed to set CPU clock to %lu MHz\n", cpu_clk);
1069         }
1070 }
1071
1072 static void tx6_init_mac(void)
1073 {
1074         u8 mac[ETH_ALEN];
1075
1076         imx_get_mac_from_fuse(-1, mac);
1077         if (!is_valid_ether_addr(mac)) {
1078                 printf("No valid MAC address programmed\n");
1079                 return;
1080         }
1081
1082         eth_setenv_enetaddr("ethaddr", mac);
1083         printf("MAC addr from fuse: %pM\n", mac);
1084 }
1085
1086 int board_late_init(void)
1087 {
1088         int ret = 0;
1089         const char *baseboard;
1090
1091         tx6qdl_set_cpu_clock();
1092         karo_fdt_move_fdt();
1093
1094         baseboard = getenv("baseboard");
1095         if (!baseboard)
1096                 goto exit;
1097
1098         printf("Baseboard: %s\n", baseboard);
1099
1100         if (strncmp(baseboard, "stk5", 4) == 0) {
1101                 if ((strlen(baseboard) == 4) ||
1102                         strcmp(baseboard, "stk5-v3") == 0) {
1103                         stk5v3_board_init();
1104                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1105                         const char *otg_mode = getenv("otg_mode");
1106
1107                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1108                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1109                                         otg_mode, baseboard);
1110                                 setenv("otg_mode", "none");
1111                         }
1112                         stk5v5_board_init();
1113                 } else {
1114                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1115                                 baseboard + 4);
1116                 }
1117         } else {
1118                 printf("WARNING: Unsupported baseboard: '%s'\n",
1119                         baseboard);
1120                 ret = -EINVAL;
1121         }
1122
1123 exit:
1124         tx6_init_mac();
1125
1126         gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1127         return ret;
1128 }
1129
1130 int checkboard(void)
1131 {
1132         u32 cpurev = get_cpu_rev();
1133         int cpu_variant = (cpurev >> 12) & 0xff;
1134
1135         tx6qdl_print_cpuinfo();
1136
1137         printf("Board: Ka-Ro TX6%c-%dxx%d\n",
1138                 cpu_variant == MXC_CPU_MX6Q ? 'Q' : 'U',
1139                 cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
1140                 1 - PHYS_SDRAM_1_WIDTH / 64);
1141
1142         return 0;
1143 }
1144
1145 #ifdef CONFIG_SERIAL_TAG
1146 void get_board_serial(struct tag_serialnr *serialnr)
1147 {
1148         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1149         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1150
1151         serialnr->low = readl(&fuse->cfg0);
1152         serialnr->high = readl(&fuse->cfg1);
1153 }
1154 #endif
1155
1156 #if defined(CONFIG_OF_BOARD_SETUP)
1157 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1158 #include <jffs2/jffs2.h>
1159 #include <mtd_node.h>
1160 struct node_info nodes[] = {
1161         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1162 };
1163
1164 #else
1165 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1166 #endif
1167
1168 void ft_board_setup(void *blob, bd_t *bd)
1169 {
1170         const char *baseboard = getenv("baseboard");
1171         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1172         char *video_mode = getenv("video_mode");
1173
1174         karo_fdt_enable_node(blob, "stk5led", !stk5_v5);
1175
1176         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1177         fdt_fixup_ethernet(blob);
1178
1179         karo_fdt_fixup_touchpanel(blob);
1180         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy");
1181         karo_fdt_fixup_flexcan(blob, stk5_v5);
1182
1183         video_mode = karo_fdt_set_display(video_mode, "", "/soc/aips-bus/ldb");
1184         karo_fdt_update_fb_mode(blob, video_mode);
1185 }
1186 #endif /* CONFIG_OF_BOARD_SETUP */