board/karo/tx6/tx6qdl.c

   1 /*
   2  * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22 #define DEBUG
  23 //#define TIMER_TEST
  24
  25 #include <common.h>
  26 #include <errno.h>
  27 #include <libfdt.h>
  28 #include <fdt_support.h>
  29 #include <lcd.h>
  30 #include <netdev.h>
  31 #include <mmc.h>
  32 #include <fsl_esdhc.h>
  33 #include <video_fb.h>
  34 #include <ipu.h>
  35 #include <mx2fb.h>
  36 #include <linux/fb.h>
  37 #include <i2c.h>
  38 #include <asm/io.h>
  39 #include <asm/gpio.h>
  40 #include <asm/arch/iomux-mx6.h>
  41 #include <asm/arch/clock.h>
  42 #include <asm/arch/imx-regs.h>
  43 #include <asm/arch/crm_regs.h>
  44 #include <asm/arch/sys_proto.h>
  45
  46 #include "../common/karo.h"
  47
  48 #define TX6_FEC_RST_GPIO                IMX_GPIO_NR(7, 6)
  49 #define TX6_FEC_PWR_GPIO                IMX_GPIO_NR(3, 20)
  50 #define TX6_FEC_INT_GPIO                IMX_GPIO_NR(2, 4)
  51 #define TX6_LED_GPIO                    IMX_GPIO_NR(2, 20)
  52
  53 #define TX6_LCD_PWR_GPIO                IMX_GPIO_NR(2, 31)
  54 #define TX6_LCD_RST_GPIO                IMX_GPIO_NR(3, 29)
  55 #define TX6_LCD_BACKLIGHT_GPIO          IMX_GPIO_NR(1, 1)
  56
  57 #define TX6_RESET_OUT_GPIO              IMX_GPIO_NR(7, 12)
  58
  59 #define TEMPERATURE_MIN                 -40
  60 #define TEMPERATURE_HOT                 80
  61 #define TEMPERATURE_MAX                 125
  62
  63 DECLARE_GLOBAL_DATA_PTR;
  64
  65 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, MUX_CONFIG_SION, 0, 0, 0)
  66
  67 static const iomux_v3_cfg_t tx6qdl_pads[] = {
  68         /* NAND flash pads */
  69         MX6_PAD_NANDF_CLE__RAWNAND_CLE,
  70         MX6_PAD_NANDF_ALE__RAWNAND_ALE,
  71         MX6_PAD_NANDF_WP_B__RAWNAND_RESETN,
  72         MX6_PAD_NANDF_RB0__RAWNAND_READY0,
  73         MX6_PAD_NANDF_CS0__RAWNAND_CE0N,
  74         MX6_PAD_SD4_CMD__RAWNAND_RDN,
  75         MX6_PAD_SD4_CLK__RAWNAND_WRN,
  76         MX6_PAD_NANDF_D0__RAWNAND_D0,
  77         MX6_PAD_NANDF_D1__RAWNAND_D1,
  78         MX6_PAD_NANDF_D2__RAWNAND_D2,
  79         MX6_PAD_NANDF_D3__RAWNAND_D3,
  80         MX6_PAD_NANDF_D4__RAWNAND_D4,
  81         MX6_PAD_NANDF_D5__RAWNAND_D5,
  82         MX6_PAD_NANDF_D6__RAWNAND_D6,
  83         MX6_PAD_NANDF_D7__RAWNAND_D7,
  84
  85         /* RESET_OUT */
  86         MX6_PAD_GPIO_17__GPIO_7_12,
  87
  88         /* UART pads */
  89 #if CONFIG_MXC_UART_BASE == UART1_BASE
  90         MX6_PAD_SD3_DAT7__UART1_TXD,
  91         MX6_PAD_SD3_DAT6__UART1_RXD,
  92         MX6_PAD_SD3_DAT1__UART1_RTS,
  93         MX6_PAD_SD3_DAT0__UART1_CTS,
  94 #endif
  95 #if CONFIG_MXC_UART_BASE == UART2_BASE
  96         MX6_PAD_SD4_DAT4__UART2_RXD,
  97         MX6_PAD_SD4_DAT7__UART2_TXD,
  98         MX6_PAD_SD4_DAT5__UART2_RTS,
  99         MX6_PAD_SD4_DAT6__UART2_CTS,
 100 #endif
 101 #if CONFIG_MXC_UART_BASE == UART3_BASE
 102         MX6_PAD_EIM_D24__UART3_TXD,
 103         MX6_PAD_EIM_D25__UART3_RXD,
 104         MX6_PAD_SD3_RST__UART3_RTS,
 105         MX6_PAD_SD3_DAT3__UART3_CTS,
 106 #endif
 107         /* internal I2C */
 108         MX6_PAD_EIM_D28__I2C1_SDA,
 109         MX6_PAD_EIM_D21__I2C1_SCL,
 110
 111         /* FEC PHY GPIO functions */
 112         MX6_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */
 113         MX6_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */
 114         MX6_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */
 115 };
 116
 117 static const iomux_v3_cfg_t tx6qdl_fec_pads[] = {
 118         /* FEC functions */
 119         MX6_PAD_ENET_MDC__ENET_MDC,
 120         MX6_PAD_ENET_MDIO__ENET_MDIO,
 121         MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
 122         MX6_PAD_ENET_RX_ER__ENET_RX_ER,
 123         MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
 124         MX6_PAD_ENET_RXD1__ENET_RDATA_1,
 125         MX6_PAD_ENET_RXD0__ENET_RDATA_0,
 126         MX6_PAD_ENET_TX_EN__ENET_TX_EN,
 127         MX6_PAD_ENET_TXD1__ENET_TDATA_1,
 128         MX6_PAD_ENET_TXD0__ENET_TDATA_0,
 129 };
 130
 131 static const struct gpio tx6qdl_gpios[] = {
 132         { TX6_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
 133         { TX6_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 134         { TX6_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 135         { TX6_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
 136 };
 137
 138 /*
 139  * Functions
 140  */
 141 /* placed in section '.data' to prevent overwriting relocation info
 142  * overlayed with bss
 143  */
 144 static u32 wrsr __attribute__((section(".data")));
 145
 146 #define WRSR_POR                        (1 << 4)
 147 #define WRSR_TOUT                       (1 << 1)
 148 #define WRSR_SFTW                       (1 << 0)
 149
 150 static void print_reset_cause(void)
 151 {
 152         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 153         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 154         u32 srsr;
 155         char *dlm = "";
 156
 157         printf("Reset cause: ");
 158
 159         srsr = readl(&src_regs->srsr);
 160         wrsr = readw(wdt_base + 4);
 161
 162         if (wrsr & WRSR_POR) {
 163                 printf("%sPOR", dlm);
 164                 dlm = " | ";
 165         }
 166         if (srsr & 0x00004) {
 167                 printf("%sCSU", dlm);
 168                 dlm = " | ";
 169         }
 170         if (srsr & 0x00008) {
 171                 printf("%sIPP USER", dlm);
 172                 dlm = " | ";
 173         }
 174         if (srsr & 0x00010) {
 175                 if (wrsr & WRSR_SFTW) {
 176                         printf("%sSOFT", dlm);
 177                         dlm = " | ";
 178                 }
 179                 if (wrsr & WRSR_TOUT) {
 180                         printf("%sWDOG", dlm);
 181                         dlm = " | ";
 182                 }
 183         }
 184         if (srsr & 0x00020) {
 185                 printf("%sJTAG HIGH-Z", dlm);
 186                 dlm = " | ";
 187         }
 188         if (srsr & 0x00040) {
 189                 printf("%sJTAG SW", dlm);
 190                 dlm = " | ";
 191         }
 192         if (srsr & 0x10000) {
 193                 printf("%sWARM BOOT", dlm);
 194                 dlm = " | ";
 195         }
 196         if (dlm[0] == '\0')
 197                 printf("unknown");
 198
 199         printf("\n");
 200 }
 201
 202 int read_cpu_temperature(void);
 203 int check_cpu_temperature(int boot);
 204
 205 static void print_cpuinfo(void)
 206 {
 207         u32 cpurev = get_cpu_rev();
 208         char *cpu_str = "?";
 209
 210         switch ((cpurev >> 12) & 0xff) {
 211         case MXC_CPU_MX6SL:
 212                 cpu_str = "SL";
 213                 break;
 214         case MXC_CPU_MX6DL:
 215                 cpu_str = "DL";
 216                 break;
 217         case MXC_CPU_MX6SOLO:
 218                 cpu_str = "SOLO";
 219                 break;
 220         case MXC_CPU_MX6Q:
 221                 cpu_str = "Q";
 222                 break;
 223         }
 224
 225         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
 226                 cpu_str,
 227                 (cpurev & 0x000F0) >> 4,
 228                 (cpurev & 0x0000F) >> 0,
 229                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 230
 231         print_reset_cause();
 232         check_cpu_temperature(1);
 233 }
 234
 235 #define LTC3676_DVB2A           0x0C
 236 #define LTC3676_DVB2B           0x0D
 237 #define LTC3676_DVB4A           0x10
 238 #define LTC3676_DVB4B           0x11
 239
 240 #define VDD_SOC_mV              (1375 + 50)
 241 #define VDD_CORE_mV             (1375 + 50)
 242
 243 #define mV_to_regval(mV)        (((mV) * 360 / 330 - 825 + 1) / 25)
 244 #define regval_to_mV(v)         (((v) * 25 + 825) * 330 / 360)
 245
 246 static int setup_pmic_voltages(void)
 247 {
 248         int ret;
 249         unsigned char value;
 250
 251         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 252
 253         ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
 254         if (ret != 0) {
 255                 printf("Failed to initialize I2C\n");
 256                 return ret;
 257         }
 258
 259         ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
 260         if (ret) {
 261                 printf("%s: i2c_read error: %d\n", __func__, ret);
 262                 return ret;
 263         }
 264
 265         /* VDDCORE/VDDSOC default 1.375V is not enough, considering
 266            pfuze tolerance and IR drop and ripple, need increase
 267            to 1.425V for SabreSD */
 268
 269         value = 0x39; /* VB default value & PGOOD not forced when slewing */
 270         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB2B, 1, &value, 1);
 271         if (ret) {
 272                 printf("%s: failed to write PMIC DVB2B register: %d\n",
 273                         __func__, ret);
 274                 return ret;
 275         }
 276         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB4B, 1, &value, 1);
 277         if (ret) {
 278                 printf("%s: failed to write PMIC DVB4B register: %d\n",
 279                         __func__, ret);
 280                 return ret;
 281         }
 282
 283         value = mV_to_regval(VDD_SOC_mV);
 284         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB2A, 1, &value, 1);
 285         if (ret) {
 286                 printf("%s: failed to write PMIC DVB2A register: %d\n",
 287                         __func__, ret);
 288                 return ret;
 289         }
 290         printf("VDDSOC  set to %dmV\n", regval_to_mV(value));
 291
 292         value = mV_to_regval(VDD_CORE_mV);
 293         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB4A, 1, &value, 1);
 294         if (ret) {
 295                 printf("%s: failed to write PMIC DVB4A register: %d\n",
 296                         __func__, ret);
 297                 return ret;
 298         }
 299         printf("VDDCORE set to %dmV\n", regval_to_mV(value));
 300         return 0;
 301 }
 302
 303 int board_early_init_f(void)
 304 {
 305         gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
 306         imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
 307
 308         return 0;
 309 }
 310
 311 int board_init(void)
 312 {
 313         int ret;
 314
 315         /* Address of boot parameters */
 316         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 317 #ifdef CONFIG_OF_LIBFDT
 318         gd->bd->bi_arch_number = -1;
 319 #else
 320         gd->bd->bi_arch_number = 4429;
 321 #endif
 322         ret = setup_pmic_voltages();
 323         if (ret) {
 324                 printf("Failed to setup PMIC voltages\n");
 325                 hang();
 326         }
 327         return 0;
 328 }
 329
 330 int dram_init(void)
 331 {
 332         /* dram_init must store complete ramsize in gd->ram_size */
 333         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 334                                 PHYS_SDRAM_1_SIZE);
 335         return 0;
 336 }
 337
 338 void dram_init_banksize(void)
 339 {
 340         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 341         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 342                         PHYS_SDRAM_1_SIZE);
 343 #if CONFIG_NR_DRAM_BANKS > 1
 344         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 345         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 346                         PHYS_SDRAM_2_SIZE);
 347 #endif
 348 }
 349
 350 #ifdef  CONFIG_CMD_MMC
 351 static const iomux_v3_cfg_t mmc0_pads[] = {
 352         MX6_PAD_SD1_CMD__USDHC1_CMD,
 353         MX6_PAD_SD1_CLK__USDHC1_CLK,
 354         MX6_PAD_SD1_DAT0__USDHC1_DAT0,
 355         MX6_PAD_SD1_DAT1__USDHC1_DAT1,
 356         MX6_PAD_SD1_DAT2__USDHC1_DAT2,
 357         MX6_PAD_SD1_DAT3__USDHC1_DAT3,
 358         /* SD1 CD */
 359         MX6_PAD_SD3_CMD__GPIO_7_2,
 360 };
 361
 362 static const iomux_v3_cfg_t mmc1_pads[] = {
 363         MX6_PAD_SD2_CMD__USDHC2_CMD,
 364         MX6_PAD_SD2_CLK__USDHC2_CLK,
 365         MX6_PAD_SD2_DAT0__USDHC2_DAT0,
 366         MX6_PAD_SD2_DAT1__USDHC2_DAT1,
 367         MX6_PAD_SD2_DAT2__USDHC2_DAT2,
 368         MX6_PAD_SD2_DAT3__USDHC2_DAT3,
 369         /* SD2 CD */
 370         MX6_PAD_SD3_CLK__GPIO_7_3,
 371 };
 372
 373 static struct tx6q_esdhc_cfg {
 374         const iomux_v3_cfg_t *pads;
 375         int num_pads;
 376         enum mxc_clock clkid;
 377         struct fsl_esdhc_cfg cfg;
 378 } tx6qdl_esdhc_cfg[] = {
 379         {
 380                 .pads = mmc0_pads,
 381                 .num_pads = ARRAY_SIZE(mmc0_pads),
 382                 .clkid = MXC_ESDHC_CLK,
 383                 .cfg = {
 384                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
 385                         .cd_gpio = IMX_GPIO_NR(7, 2),
 386                         .wp_gpio = -EINVAL,
 387                 },
 388         },
 389         {
 390                 .pads = mmc1_pads,
 391                 .num_pads = ARRAY_SIZE(mmc1_pads),
 392                 .clkid = MXC_ESDHC2_CLK,
 393                 .cfg = {
 394                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
 395                         .cd_gpio = IMX_GPIO_NR(7, 3),
 396                         .wp_gpio = -EINVAL,
 397                 },
 398         },
 399 };
 400
 401 static inline struct tx6q_esdhc_cfg *to_tx6q_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 402 {
 403         void *p = cfg;
 404
 405         return p - offsetof(struct tx6q_esdhc_cfg, cfg);
 406 }
 407
 408 int board_mmc_getcd(struct mmc *mmc)
 409 {
 410         struct fsl_esdhc_cfg *cfg = mmc->priv;
 411
 412         if (cfg->cd_gpio < 0)
 413                 return cfg->cd_gpio;
 414
 415         debug("SD card %d is %spresent\n",
 416                 to_tx6q_esdhc_cfg(cfg) - tx6qdl_esdhc_cfg,
 417                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
 418         return !gpio_get_value(cfg->cd_gpio);
 419 }
 420
 421 int board_mmc_init(bd_t *bis)
 422 {
 423         int i;
 424
 425         for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
 426                 struct mmc *mmc;
 427                 struct fsl_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i].cfg;
 428
 429                 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
 430                         break;
 431
 432                 cfg->sdhc_clk = mxc_get_clock(tx6qdl_esdhc_cfg[i].clkid);
 433                 imx_iomux_v3_setup_multiple_pads(tx6qdl_esdhc_cfg[i].pads,
 434                                                 tx6qdl_esdhc_cfg[i].num_pads);
 435
 436                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 437                 fsl_esdhc_initialize(bis, cfg);
 438
 439                 mmc = find_mmc_device(i);
 440                 if (mmc == NULL)
 441                         continue;
 442                 if (board_mmc_getcd(mmc) > 0)
 443                         mmc_init(mmc);
 444         }
 445         return 0;
 446 }
 447 #endif /* CONFIG_CMD_MMC */
 448
 449 #ifdef CONFIG_FEC_MXC
 450
 451 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
 452                         PAD_CTL_SRE_FAST)
 453 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
 454 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 455
 456 #ifndef ETH_ALEN
 457 #define ETH_ALEN 6
 458 #endif
 459
 460 int board_eth_init(bd_t *bis)
 461 {
 462         int ret;
 463
 464         /* delay at least 21ms for the PHY internal POR signal to deassert */
 465         udelay(22000);
 466
 467         imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads, ARRAY_SIZE(tx6qdl_fec_pads));
 468
 469         /* Deassert RESET to the external phy */
 470         gpio_set_value(TX6_FEC_RST_GPIO, 1);
 471
 472         ret = cpu_eth_init(bis);
 473         if (ret)
 474                 printf("cpu_eth_init() failed: %d\n", ret);
 475
 476         return ret;
 477 }
 478 #endif /* CONFIG_FEC_MXC */
 479
 480 enum {
 481         LED_STATE_INIT = -1,
 482         LED_STATE_OFF,
 483         LED_STATE_ON,
 484 };
 485
 486 static inline int calc_blink_rate(int tmp)
 487 {
 488         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
 489                 (tmp - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
 490                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
 491 }
 492
 493 void show_activity(int arg)
 494 {
 495         static int led_state = LED_STATE_INIT;
 496         static int blink_rate;
 497         static ulong last;
 498
 499         if (led_state == LED_STATE_INIT) {
 500                 last = get_timer(0);
 501                 gpio_set_value(TX6_LED_GPIO, 1);
 502                 led_state = LED_STATE_ON;
 503                 blink_rate = calc_blink_rate(check_cpu_temperature(0));
 504         } else {
 505                 if (get_timer(last) > blink_rate) {
 506                         blink_rate = calc_blink_rate(check_cpu_temperature(0));
 507                         last = get_timer_masked();
 508                         if (led_state == LED_STATE_ON) {
 509                                 gpio_set_value(TX6_LED_GPIO, 0);
 510                         } else {
 511                                 gpio_set_value(TX6_LED_GPIO, 1);
 512                         }
 513                         led_state = 1 - led_state;
 514                 }
 515         }
 516 }
 517
 518 static const iomux_v3_cfg_t stk5_pads[] = {
 519         /* SW controlled LED on STK5 baseboard */
 520         MX6_PAD_EIM_A18__GPIO_2_20,
 521
 522         /* LCD data pins */
 523         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
 524         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
 525         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
 526         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
 527         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
 528         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
 529         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
 530         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
 531         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
 532         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
 533         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
 534         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
 535         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
 536         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
 537         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
 538         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
 539         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
 540         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
 541         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
 542         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
 543         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
 544         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
 545         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
 546         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
 547         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */
 548         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */
 549         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
 550         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
 551
 552         /* I2C bus on DIMM pins 40/41 */
 553         MX6_PAD_GPIO_6__I2C3_SDA,
 554         MX6_PAD_GPIO_3__I2C3_SCL,
 555
 556         /* TSC200x PEN IRQ */
 557         MX6_PAD_EIM_D26__GPIO_3_26,
 558
 559         /* EDT-FT5x06 Polytouch panel */
 560         MX6_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */
 561         MX6_PAD_EIM_A16__GPIO_2_22, /* RESET */
 562         MX6_PAD_EIM_A17__GPIO_2_21, /* WAKE */
 563
 564         /* USBH1 */
 565         MX6_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */
 566         MX6_PAD_EIM_D30__GPIO_3_30, /* OC */
 567         /* USBOTG */
 568         MX6_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */
 569         MX6_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */
 570         MX6_PAD_GPIO_8__GPIO_1_8, /* OC */
 571 };
 572
 573 static const struct gpio stk5_gpios[] = {
 574         { TX6_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 575
 576         { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", },
 577         { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
 578         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 579         { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
 580         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 581 };
 582
 583 #ifdef CONFIG_LCD
 584 vidinfo_t panel_info = {
 585         /* set to max. size supported by SoC */
 586         .vl_col = 1920,
 587         .vl_row = 1080,
 588
 589         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 590 };
 591
 592 static struct fb_videomode tx6_fb_modes[] = {
 593         {
 594                 /* Standard VGA timing */
 595                 .name           = "VGA",
 596                 .refresh        = 60,
 597                 .xres           = 640,
 598                 .yres           = 480,
 599                 .pixclock       = KHZ2PICOS(25175),
 600                 .left_margin    = 48,
 601                 .hsync_len      = 96,
 602                 .right_margin   = 16,
 603                 .upper_margin   = 31,
 604                 .vsync_len      = 2,
 605                 .lower_margin   = 12,
 606                 .sync           = FB_SYNC_CLK_LAT_FALL,
 607         },
 608         {
 609                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 610                  * DE high active, 115.2 mm x 86.4 mm display area
 611                  * VGA compatible timing
 612                  */
 613                 .name           = "ETV570",
 614                 .refresh        = 60,
 615                 .xres           = 640,
 616                 .yres           = 480,
 617                 .pixclock       = KHZ2PICOS(25175),
 618                 .left_margin    = 114,
 619                 .hsync_len      = 30,
 620                 .right_margin   = 16,
 621                 .upper_margin   = 32,
 622                 .vsync_len      = 3,
 623                 .lower_margin   = 10,
 624                 .sync           = FB_SYNC_CLK_LAT_FALL,
 625         },
 626         {
 627                 /* Emerging ET0350G0DH6 320 x 240 display.
 628                  * 70.08 mm x 52.56 mm display area.
 629                  */
 630                 .name           = "ET0350",
 631                 .refresh        = 60,
 632                 .xres           = 320,
 633                 .yres           = 240,
 634                 .pixclock       = KHZ2PICOS(6500),
 635                 .left_margin    = 68 - 34,
 636                 .hsync_len      = 34,
 637                 .right_margin   = 20,
 638                 .upper_margin   = 18 - 3,
 639                 .vsync_len      = 3,
 640                 .lower_margin   = 4,
 641                 .sync           = FB_SYNC_CLK_LAT_FALL,
 642         },
 643         {
 644                 /* Emerging ET0430G0DH6 480 x 272 display.
 645                  * 95.04 mm x 53.856 mm display area.
 646                  */
 647                 .name           = "ET0430",
 648                 .refresh        = 60,
 649                 .xres           = 480,
 650                 .yres           = 272,
 651                 .pixclock       = KHZ2PICOS(9000),
 652                 .left_margin    = 2,
 653                 .hsync_len      = 41,
 654                 .right_margin   = 2,
 655                 .upper_margin   = 2,
 656                 .vsync_len      = 10,
 657                 .lower_margin   = 2,
 658                 .sync           = FB_SYNC_CLK_LAT_FALL,
 659         },
 660         {
 661                 /* Emerging ET0500G0DH6 800 x 480 display.
 662                  * 109.6 mm x 66.4 mm display area.
 663                  */
 664                 .name           = "ET0500",
 665                 .refresh        = 60,
 666                 .xres           = 800,
 667                 .yres           = 480,
 668                 .pixclock       = KHZ2PICOS(33260),
 669                 .left_margin    = 216 - 128,
 670                 .hsync_len      = 128,
 671                 .right_margin   = 1056 - 800 - 216,
 672                 .upper_margin   = 35 - 2,
 673                 .vsync_len      = 2,
 674                 .lower_margin   = 525 - 480 - 35,
 675                 .sync           = FB_SYNC_CLK_LAT_FALL,
 676         },
 677         {
 678                 /* Emerging ETQ570G0DH6 320 x 240 display.
 679                  * 115.2 mm x 86.4 mm display area.
 680                  */
 681                 .name           = "ETQ570",
 682                 .refresh        = 60,
 683                 .xres           = 320,
 684                 .yres           = 240,
 685                 .pixclock       = KHZ2PICOS(6400),
 686                 .left_margin    = 38,
 687                 .hsync_len      = 30,
 688                 .right_margin   = 30,
 689                 .upper_margin   = 16, /* 15 according to datasheet */
 690                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 691                 .lower_margin   = 4, /* 4.5 according to datasheet */
 692                 .sync           = FB_SYNC_CLK_LAT_FALL,
 693         },
 694         {
 695                 /* Emerging ET0700G0DH6 800 x 480 display.
 696                  * 152.4 mm x 91.44 mm display area.
 697                  */
 698                 .name           = "ET0700",
 699                 .refresh        = 60,
 700                 .xres           = 800,
 701                 .yres           = 480,
 702                 .pixclock       = KHZ2PICOS(33260),
 703                 .left_margin    = 216 - 128,
 704                 .hsync_len      = 128,
 705                 .right_margin   = 1056 - 800 - 216,
 706                 .upper_margin   = 35 - 2,
 707                 .vsync_len      = 2,
 708                 .lower_margin   = 525 - 480 - 35,
 709                 .sync           = FB_SYNC_CLK_LAT_FALL,
 710         },
 711         {
 712                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 713                 .refresh        = 60,
 714                 .left_margin    = 48,
 715                 .hsync_len      = 96,
 716                 .right_margin   = 16,
 717                 .upper_margin   = 31,
 718                 .vsync_len      = 2,
 719                 .lower_margin   = 12,
 720                 .sync           = FB_SYNC_CLK_LAT_FALL,
 721         },
 722 };
 723
 724 static int lcd_enabled = 1;
 725
 726 void lcd_enable(void)
 727 {
 728         /* HACK ALERT:
 729          * global variable from common/lcd.c
 730          * Set to 0 here to prevent messages from going to LCD
 731          * rather than serial console
 732          */
 733         lcd_is_enabled = 0;
 734
 735         karo_load_splashimage(1);
 736         if (lcd_enabled) {
 737                 debug("Switching LCD on\n");
 738                 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
 739                 udelay(100);
 740                 gpio_set_value(TX6_LCD_RST_GPIO, 1);
 741                 udelay(300000);
 742                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, 0);
 743         }
 744 }
 745
 746 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 747         /* LCD RESET */
 748         MX6_PAD_EIM_D29__GPIO_3_29,
 749         /* LCD POWER_ENABLE */
 750         MX6_PAD_EIM_EB3__GPIO_2_31,
 751         /* LCD Backlight (PWM) */
 752         MX6_PAD_GPIO_1__GPIO_1_1,
 753
 754         /* Display */
 755         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
 756         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
 757         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
 758         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
 759         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
 760         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
 761         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
 762         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
 763         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
 764         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
 765         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
 766         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
 767         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
 768         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
 769         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
 770         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
 771         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
 772         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
 773         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
 774         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
 775         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
 776         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
 777         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
 778         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
 779         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
 780         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
 781         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
 782         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
 783 };
 784
 785 static const struct gpio stk5_lcd_gpios[] = {
 786         { TX6_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
 787         { TX6_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
 788         { TX6_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 789 };
 790
 791 void lcd_ctrl_init(void *lcdbase)
 792 {
 793         int color_depth = 24;
 794         char *vm;
 795         unsigned long val;
 796         int refresh = 60;
 797         struct fb_videomode *p = &tx6_fb_modes[0];
 798         struct fb_videomode fb_mode;
 799         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 800         int pix_fmt = 0;
 801         ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
 802         unsigned long di_clk_rate = 65000000;
 803
 804         if (!lcd_enabled) {
 805                 debug("LCD disabled\n");
 806                 return;
 807         }
 808
 809         if (tstc() || (wrsr & WRSR_TOUT)) {
 810                 debug("Disabling LCD\n");
 811                 lcd_enabled = 0;
 812                 return;
 813         }
 814
 815         karo_fdt_move_fdt();
 816
 817         vm = getenv("video_mode");
 818         if (vm == NULL) {
 819                 debug("Disabling LCD\n");
 820                 lcd_enabled = 0;
 821                 return;
 822         }
 823         if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
 824                 p = &fb_mode;
 825                 debug("Using video mode from FDT\n");
 826                 vm += strlen(vm);
 827                 if (fb_mode.xres < panel_info.vl_col)
 828                         panel_info.vl_col = fb_mode.xres;
 829                 if (fb_mode.yres < panel_info.vl_row)
 830                         panel_info.vl_row = fb_mode.yres;
 831         }
 832         if (p->name != NULL)
 833                 debug("Trying compiled-in video modes\n");
 834         while (p->name != NULL) {
 835                 if (strcmp(p->name, vm) == 0) {
 836                         debug("Using video mode: '%s'\n", p->name);
 837                         vm += strlen(vm);
 838                         break;
 839                 }
 840                 p++;
 841         }
 842         if (*vm != '\0')
 843                 debug("Trying to decode video_mode: '%s'\n", vm);
 844         while (*vm != '\0') {
 845                 if (*vm >= '0' && *vm <= '9') {
 846                         char *end;
 847
 848                         val = simple_strtoul(vm, &end, 0);
 849                         if (end > vm) {
 850                                 if (!xres_set) {
 851                                         if (val > panel_info.vl_col)
 852                                                 val = panel_info.vl_col;
 853                                         p->xres = val;
 854                                         panel_info.vl_col = val;
 855                                         xres_set = 1;
 856                                 } else if (!yres_set) {
 857                                         if (val > panel_info.vl_row)
 858                                                 val = panel_info.vl_row;
 859                                         p->yres = val;
 860                                         panel_info.vl_row = val;
 861                                         yres_set = 1;
 862                                 } else if (!bpp_set) {
 863                                         switch (val) {
 864                                         case 24:
 865                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666)
 866                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
 867                                                 /* fallthru */
 868                                         case 16:
 869                                         case 8:
 870                                                 color_depth = val;
 871                                                 break;
 872
 873                                         case 18:
 874                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666) {
 875                                                         color_depth = val;
 876                                                         break;
 877                                                 }
 878                                                 /* fallthru */
 879                                         default:
 880                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
 881                                                         end - vm, vm, color_depth);
 882                                         }
 883                                         bpp_set = 1;
 884                                 } else if (!refresh_set) {
 885                                         refresh = val;
 886                                         refresh_set = 1;
 887                                 }
 888                         }
 889                         vm = end;
 890                 }
 891                 switch (*vm) {
 892                 case '@':
 893                         bpp_set = 1;
 894                         /* fallthru */
 895                 case '-':
 896                         yres_set = 1;
 897                         /* fallthru */
 898                 case 'x':
 899                         xres_set = 1;
 900                         /* fallthru */
 901                 case 'M':
 902                 case 'R':
 903                         vm++;
 904                         break;
 905
 906                 default:
 907                         if (!pix_fmt) {
 908                                 char *tmp;
 909
 910                                 if (strncmp(vm, "LVDS", 4) == 0) {
 911                                         pix_fmt = IPU_PIX_FMT_LVDS666;
 912                                         di_clk_parent = DI_PCLK_LDB;
 913                                 } else {
 914                                         pix_fmt = IPU_PIX_FMT_RGB24;
 915                                 }
 916                                 tmp = strchr(vm, ':');
 917                                 if (tmp)
 918                                         vm = tmp;
 919                         }
 920                         if (*vm != '\0')
 921                                 vm++;
 922                 }
 923         }
 924         if (p->xres == 0 || p->yres == 0) {
 925                 printf("Invalid video mode: %s\n", getenv("video_mode"));
 926                 lcd_enabled = 0;
 927                 printf("Supported video modes are:");
 928                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
 929                         printf(" %s", p->name);
 930                 }
 931                 printf("\n");
 932                 return;
 933         }
 934
 935         p->pixclock = KHZ2PICOS(refresh *
 936                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
 937                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
 938                 / 1000);
 939         debug("Pixel clock set to %lu.%03lu MHz\n",
 940                 PICOS2KHZ(p->pixclock) / 1000,
 941                 PICOS2KHZ(p->pixclock) % 1000);
 942
 943         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
 944         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
 945                                         ARRAY_SIZE(stk5_lcd_pads));
 946
 947         debug("Initializing FB driver\n");
 948         if (!pix_fmt)
 949                 pix_fmt = IPU_PIX_FMT_RGB24;
 950         else if (pix_fmt == IPU_PIX_FMT_LVDS666) {
 951                 writel(0x01, IOMUXC_BASE_ADDR + 8);
 952         } else if (pix_fmt == IPU_PIX_FMT_LVDS888) {
 953                 writel(0x21, IOMUXC_BASE_ADDR + 8);
 954         }
 955         if (pix_fmt != IPU_PIX_FMT_RGB24) {
 956                 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 957                 /* enable LDB & DI0 clock */
 958                 writel(readl(&ccm_regs->CCGR3) | (3 << 12) | (3 << 2),
 959                         &ccm_regs->CCGR3);
 960         }
 961
 962         if (karo_load_splashimage(0) == 0) {
 963                 debug("Initializing LCD controller\n");
 964                 ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
 965         } else {
 966                 debug("Skipping initialization of LCD controller\n");
 967         }
 968 }
 969 #else
 970 #define lcd_enabled 0
 971 #endif /* CONFIG_LCD */
 972
 973 static void stk5_board_init(void)
 974 {
 975         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
 976         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
 977 }
 978
 979 static void stk5v3_board_init(void)
 980 {
 981         stk5_board_init();
 982 }
 983
 984 static void stk5v5_board_init(void)
 985 {
 986         stk5_board_init();
 987
 988         gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
 989                         "Flexcan Transceiver");
 990         imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO_4_21);
 991 }
 992
 993 static void tx6qdl_set_cpu_clock(void)
 994 {
 995         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
 996
 997         if (tstc() || (wrsr & WRSR_TOUT))
 998                 return;
 999
1000         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1001                 return;
1002
1003         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1004                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1005                 printf("CPU clock set to %lu.%03lu MHz\n",
1006                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1007         } else {
1008                 printf("Failed to set CPU clock to %lu MHz\n", cpu_clk);
1009         }
1010 }
1011
1012 static void tx6_init_mac(void)
1013 {
1014         u8 mac[ETH_ALEN];
1015         char mac_str[ETH_ALEN * 3] = "";
1016
1017         imx_get_mac_from_fuse(-1, mac);
1018         if (!is_valid_ether_addr(mac)) {
1019                 printf("No valid MAC address programmed\n");
1020                 return;
1021         }
1022
1023         snprintf(mac_str, sizeof(mac_str), "%02x:%02x:%02x:%02x:%02x:%02x",
1024                 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
1025         setenv("ethaddr", mac_str);
1026         printf("MAC addr from fuse: %02x:%02x:%02x:%02x:%02x:%02x\n",
1027                 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
1028 }
1029
1030 int board_late_init(void)
1031 {
1032         int ret = 0;
1033         const char *baseboard;
1034
1035         tx6qdl_set_cpu_clock();
1036         karo_fdt_move_fdt();
1037
1038         baseboard = getenv("baseboard");
1039         if (!baseboard)
1040                 goto exit;
1041
1042         printf("Baseboard: %s\n", baseboard);
1043
1044         if (strncmp(baseboard, "stk5", 4) == 0) {
1045                 if ((strlen(baseboard) == 4) ||
1046                         strcmp(baseboard, "stk5-v3") == 0) {
1047                         stk5v3_board_init();
1048                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1049                         stk5v5_board_init();
1050                 } else {
1051                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1052                                 baseboard + 4);
1053                 }
1054         } else {
1055                 printf("WARNING: Unsupported baseboard: '%s'\n",
1056                         baseboard);
1057                 ret = -EINVAL;
1058         }
1059
1060 exit:
1061         tx6_init_mac();
1062
1063         gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1064         return ret;
1065 }
1066
1067 int checkboard(void)
1068 {
1069         print_cpuinfo();
1070 #if defined(CONFIG_MX6Q)
1071         printf("Board: Ka-Ro TX6Q\n");
1072 #elif defined(CONFIG_MX6DL)
1073         printf("Board: Ka-Ro TX6DL\n");
1074 #else
1075 #error Unsupported i.MX6 variant selected
1076 #endif
1077
1078 #ifdef TIMER_TEST
1079         {
1080                 struct mxc_gpt {
1081                         unsigned int control;
1082                         unsigned int prescaler;
1083                         unsigned int status;
1084                         unsigned int nouse[6];
1085                         unsigned int counter;
1086                 };
1087                 const int us_delay = 10;
1088                 unsigned long start = get_timer(0);
1089                 unsigned long last = gd->arch.tbl;
1090                 unsigned long loop = 0;
1091                 unsigned long cnt = 0;
1092                 static struct mxc_gpt *timer_base = (struct mxc_gpt *)GPT1_BASE_ADDR;
1093
1094                 printf("GPT prescaler=%u\n", readl(&timer_base->prescaler) + 1);
1095                 printf("clock tick rate: %lu.%03lukHz\n",
1096                         gd->arch.timer_rate_hz / 1000, gd->arch.timer_rate_hz % 1000);
1097                 printf("ticks/us=%lu\n", gd->arch.timer_rate_hz / CONFIG_SYS_HZ / 1000);
1098
1099                 while (!tstc()) {
1100                         unsigned long elapsed = get_timer(start);
1101                         unsigned long diff = gd->arch.tbl - last;
1102
1103                         loop++;
1104                         last = gd->arch.tbl;
1105
1106                         printf("loop %4lu: t=%08lx diff=%08lx steps=%6lu elapsed time: %4lu",
1107                                 loop, gd->arch.tbl, diff, cnt, elapsed / CONFIG_SYS_HZ);
1108                         cnt = 0;
1109                         while (get_timer(elapsed + start) < CONFIG_SYS_HZ) {
1110                                 cnt++;
1111                                 udelay(us_delay);
1112                         }
1113                         printf(" counter=%08x udelay(%u)=%lu.%03luus\n",
1114                                 readl(&timer_base->counter), us_delay,
1115                                 1000000000 / cnt / 1000, 1000000000 / cnt % 1000);
1116                 }
1117         }
1118 #endif
1119         return 0;
1120 }
1121
1122 #ifdef CONFIG_SERIAL_TAG
1123 void get_board_serial(struct tag_serialnr *serialnr)
1124 {
1125         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
1126         struct fuse_bank0_regs *fuse = (void *)iim->bank[0].fuse_regs;
1127
1128         serialnr->low = readl(&fuse->cfg0);
1129         serialnr->high = readl(&fuse->cfg1);
1130 }
1131 #endif
1132
1133 #if defined(CONFIG_OF_BOARD_SETUP)
1134 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1135 #include <jffs2/jffs2.h>
1136 #include <mtd_node.h>
1137 struct node_info nodes[] = {
1138         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1139 };
1140
1141 #else
1142 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1143 #endif
1144
1145 static void tx6qdl_fixup_flexcan(void *blob)
1146 {
1147         const char *baseboard = getenv("baseboard");
1148
1149         if (baseboard && strcmp(baseboard, "stk5-v5") == 0)
1150                 return;
1151
1152         karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x02090000, "transceiver-switch");
1153         karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x02094000, "transceiver-switch");
1154 }
1155
1156 void ft_board_setup(void *blob, bd_t *bd)
1157 {
1158         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1159         fdt_fixup_ethernet(blob);
1160
1161         karo_fdt_fixup_touchpanel(blob);
1162         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy");
1163         tx6qdl_fixup_flexcan(blob);
1164         karo_fdt_update_fb_mode(blob, getenv("video_mode"));
1165 }
1166 #endif