board/karo/tx6/tx6qdl.c

   1 /*
   2  * Copyright (C) 2012-2015 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * version 2 as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17 #include <common.h>
  18 #include <errno.h>
  19 #include <libfdt.h>
  20 #include <fdt_support.h>
  21 #include <lcd.h>
  22 #include <netdev.h>
  23 #include <mmc.h>
  24 #include <fsl_esdhc.h>
  25 #include <video_fb.h>
  26 #include <ipu.h>
  27 #include <mxcfb.h>
  28 #include <i2c.h>
  29 #include <linux/fb.h>
  30 #include <asm/io.h>
  31 #include <asm/gpio.h>
  32 #include <asm/arch/mx6-pins.h>
  33 #include <asm/arch/clock.h>
  34 #include <asm/arch/imx-regs.h>
  35 #include <asm/arch/crm_regs.h>
  36 #include <asm/arch/sys_proto.h>
  37
  38 #include "../common/karo.h"
  39 #include "pmic.h"
  40
  41 #define __data __attribute__((section(".data")))
  42
  43 #define TX6_FEC_RST_GPIO                IMX_GPIO_NR(7, 6)
  44 #define TX6_FEC_PWR_GPIO                IMX_GPIO_NR(3, 20)
  45 #define TX6_FEC_INT_GPIO                IMX_GPIO_NR(7, 1)
  46 #define TX6_LED_GPIO                    IMX_GPIO_NR(2, 20)
  47
  48 #define TX6_LCD_PWR_GPIO                IMX_GPIO_NR(2, 31)
  49 #define TX6_LCD_RST_GPIO                IMX_GPIO_NR(3, 29)
  50 #define TX6_LCD_BACKLIGHT_GPIO          IMX_GPIO_NR(1, 1)
  51
  52 #define TX6_RESET_OUT_GPIO              IMX_GPIO_NR(7, 12)
  53
  54 #ifdef CONFIG_MX6_TEMPERATURE_MIN
  55 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
  56 #else
  57 #define TEMPERATURE_MIN                 (-40)
  58 #endif
  59 #ifdef CONFIG_MX6_TEMPERATURE_HOT
  60 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
  61 #else
  62 #define TEMPERATURE_HOT                 80
  63 #endif
  64
  65 DECLARE_GLOBAL_DATA_PTR;
  66
  67 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  68
  69 enum {
  70         MX6_PAD_DECL(GARBAGE, 0, 0, 0, 0, 0, 0)
  71 };
  72
  73 static const iomux_v3_cfg_t const tx6qdl_pads[] = {
  74         /* RESET_OUT */
  75         MX6_PAD_GPIO_17__GPIO7_IO12,
  76
  77         /* UART pads */
  78 #if CONFIG_MXC_UART_BASE == UART1_BASE
  79         MX6_PAD_SD3_DAT7__UART1_TX_DATA,
  80         MX6_PAD_SD3_DAT6__UART1_RX_DATA,
  81         MX6_PAD_SD3_DAT1__UART1_RTS_B,
  82         MX6_PAD_SD3_DAT0__UART1_CTS_B,
  83 #endif
  84 #if CONFIG_MXC_UART_BASE == UART2_BASE
  85         MX6_PAD_SD4_DAT4__UART2_RX_DATA,
  86         MX6_PAD_SD4_DAT7__UART2_TX_DATA,
  87         MX6_PAD_SD4_DAT5__UART2_RTS_B,
  88         MX6_PAD_SD4_DAT6__UART2_CTS_B,
  89 #endif
  90 #if CONFIG_MXC_UART_BASE == UART3_BASE
  91         MX6_PAD_EIM_D24__UART3_TX_DATA,
  92         MX6_PAD_EIM_D25__UART3_RX_DATA,
  93         MX6_PAD_SD3_RST__UART3_RTS_B,
  94         MX6_PAD_SD3_DAT3__UART3_CTS_B,
  95 #endif
  96         /* internal I2C */
  97         MX6_PAD_EIM_D28__I2C1_SDA,
  98         MX6_PAD_EIM_D21__I2C1_SCL,
  99
 100         /* FEC PHY GPIO functions */
 101         MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION, /* PHY POWER */
 102         MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION, /* PHY RESET */
 103         MX6_PAD_SD3_DAT4__GPIO7_IO01, /* PHY INT */
 104 };
 105
 106 static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = {
 107         /* FEC functions */
 108         MX6_PAD_ENET_MDC__ENET_MDC,
 109         MX6_PAD_ENET_MDIO__ENET_MDIO,
 110         MX6_PAD_GPIO_16__ENET_REF_CLK,
 111         MX6_PAD_ENET_RX_ER__ENET_RX_ER,
 112         MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
 113         MX6_PAD_ENET_RXD1__ENET_RX_DATA1,
 114         MX6_PAD_ENET_RXD0__ENET_RX_DATA0,
 115         MX6_PAD_ENET_TX_EN__ENET_TX_EN,
 116         MX6_PAD_ENET_TXD1__ENET_TX_DATA1,
 117         MX6_PAD_ENET_TXD0__ENET_TX_DATA0,
 118 };
 119
 120 static const struct gpio const tx6qdl_gpios[] = {
 121         { TX6_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", },
 122         { TX6_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 123         { TX6_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 124         { TX6_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
 125 };
 126
 127 /*
 128  * Functions
 129  */
 130 /* placed in section '.data' to prevent overwriting relocation info
 131  * overlayed with bss
 132  */
 133 static u32 wrsr __attribute__((section(".data")));
 134
 135 #define WRSR_POR                        (1 << 4)
 136 #define WRSR_TOUT                       (1 << 1)
 137 #define WRSR_SFTW                       (1 << 0)
 138
 139 static void print_reset_cause(void)
 140 {
 141         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 142         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 143         u32 srsr;
 144         char *dlm = "";
 145
 146         printf("Reset cause: ");
 147
 148         srsr = readl(&src_regs->srsr);
 149         wrsr = readw(wdt_base + 4);
 150
 151         if (wrsr & WRSR_POR) {
 152                 printf("%sPOR", dlm);
 153                 dlm = " | ";
 154         }
 155         if (srsr & 0x00004) {
 156                 printf("%sCSU", dlm);
 157                 dlm = " | ";
 158         }
 159         if (srsr & 0x00008) {
 160                 printf("%sIPP USER", dlm);
 161                 dlm = " | ";
 162         }
 163         if (srsr & 0x00010) {
 164                 if (wrsr & WRSR_SFTW) {
 165                         printf("%sSOFT", dlm);
 166                         dlm = " | ";
 167                 }
 168                 if (wrsr & WRSR_TOUT) {
 169                         printf("%sWDOG", dlm);
 170                         dlm = " | ";
 171                 }
 172         }
 173         if (srsr & 0x00020) {
 174                 printf("%sJTAG HIGH-Z", dlm);
 175                 dlm = " | ";
 176         }
 177         if (srsr & 0x00040) {
 178                 printf("%sJTAG SW", dlm);
 179                 dlm = " | ";
 180         }
 181         if (srsr & 0x10000) {
 182                 printf("%sWARM BOOT", dlm);
 183                 dlm = " | ";
 184         }
 185         if (dlm[0] == '\0')
 186                 printf("unknown");
 187
 188         printf("\n");
 189 }
 190
 191 static const char __data *tx6_mod_suffix;
 192
 193 static void tx6qdl_print_cpuinfo(void)
 194 {
 195         u32 cpurev = get_cpu_rev();
 196         char *cpu_str = "?";
 197
 198         switch ((cpurev >> 12) & 0xff) {
 199         case MXC_CPU_MX6SL:
 200                 cpu_str = "SL";
 201                 tx6_mod_suffix = "?";
 202                 break;
 203         case MXC_CPU_MX6DL:
 204                 cpu_str = "DL";
 205                 tx6_mod_suffix = "U";
 206                 break;
 207         case MXC_CPU_MX6SOLO:
 208                 cpu_str = "SOLO";
 209                 tx6_mod_suffix = "S";
 210                 break;
 211         case MXC_CPU_MX6Q:
 212                 cpu_str = "Q";
 213                 tx6_mod_suffix = "Q";
 214                 break;
 215         }
 216
 217         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
 218                 cpu_str,
 219                 (cpurev & 0x000F0) >> 4,
 220                 (cpurev & 0x0000F) >> 0,
 221                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 222
 223         print_reset_cause();
 224 #ifdef CONFIG_MX6_TEMPERATURE_HOT
 225         check_cpu_temperature(1);
 226 #endif
 227 }
 228
 229 int board_early_init_f(void)
 230 {
 231         return 0;
 232 }
 233
 234 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 235 static bool tx6_temp_check_enabled = true;
 236 #else
 237 #define tx6_temp_check_enabled  0
 238 #endif
 239 static int pmic_addr __data;
 240
 241 int board_init(void)
 242 {
 243         int ret;
 244
 245         ret = gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
 246         if (ret < 0) {
 247                 printf("Failed to request tx6qdl_gpios: %d\n", ret);
 248         }
 249         imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
 250
 251         /* Address of boot parameters */
 252         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 253         gd->bd->bi_arch_number = -1;
 254
 255         if (ctrlc() || (wrsr & WRSR_TOUT)) {
 256                 if (wrsr & WRSR_TOUT)
 257                         printf("WDOG RESET detected; Skipping PMIC setup\n");
 258                 else
 259                         printf("<CTRL-C> detected; safeboot enabled\n");
 260 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 261                 tx6_temp_check_enabled = false;
 262 #endif
 263                 return 0;
 264         }
 265
 266         ret = tx6_pmic_init(pmic_addr);
 267         if (ret) {
 268                 printf("Failed to setup PMIC voltages: %d\n", ret);
 269                 hang();
 270         }
 271         return 0;
 272 }
 273
 274 int dram_init(void)
 275 {
 276         /* dram_init must store complete ramsize in gd->ram_size */
 277         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 278                                 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
 279         return 0;
 280 }
 281
 282 void dram_init_banksize(void)
 283 {
 284         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 285         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 286                         PHYS_SDRAM_1_SIZE);
 287 #if CONFIG_NR_DRAM_BANKS > 1
 288         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 289         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 290                         PHYS_SDRAM_2_SIZE);
 291 #endif
 292 }
 293
 294 #ifdef  CONFIG_FSL_ESDHC
 295 #define SD_PAD_CTRL (PAD_CTL_PUS_47K_UP |               \
 296         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |         \
 297         PAD_CTL_SRE_FAST)
 298
 299 static const iomux_v3_cfg_t mmc0_pads[] = {
 300         MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
 301         MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
 302         MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
 303         MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
 304         MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
 305         MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
 306         /* SD1 CD */
 307         MX6_PAD_SD3_CMD__GPIO7_IO02,
 308 };
 309
 310 static const iomux_v3_cfg_t mmc1_pads[] = {
 311         MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
 312         MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
 313         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
 314         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
 315         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
 316         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
 317         /* SD2 CD */
 318         MX6_PAD_SD3_CLK__GPIO7_IO03,
 319 };
 320
 321 #ifdef CONFIG_TX6_EMMC
 322 static const iomux_v3_cfg_t mmc3_pads[] = {
 323         MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
 324         MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
 325         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
 326         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
 327         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
 328         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
 329         /* eMMC RESET */
 330         MX6_PAD_NANDF_ALE__SD4_RESET | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
 331                                                 PAD_CTL_DSE_40ohm),
 332 };
 333 #endif
 334
 335 static struct tx6_esdhc_cfg {
 336         const iomux_v3_cfg_t *pads;
 337         int num_pads;
 338         enum mxc_clock clkid;
 339         struct fsl_esdhc_cfg cfg;
 340         int cd_gpio;
 341 } tx6qdl_esdhc_cfg[] = {
 342 #ifdef CONFIG_TX6_EMMC
 343         {
 344                 .pads = mmc3_pads,
 345                 .num_pads = ARRAY_SIZE(mmc3_pads),
 346                 .clkid = MXC_ESDHC4_CLK,
 347                 .cfg = {
 348                         .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
 349                         .max_bus_width = 4,
 350                 },
 351                 .cd_gpio = -EINVAL,
 352         },
 353 #endif
 354         {
 355                 .pads = mmc0_pads,
 356                 .num_pads = ARRAY_SIZE(mmc0_pads),
 357                 .clkid = MXC_ESDHC_CLK,
 358                 .cfg = {
 359                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
 360                         .max_bus_width = 4,
 361                 },
 362                 .cd_gpio = IMX_GPIO_NR(7, 2),
 363         },
 364         {
 365                 .pads = mmc1_pads,
 366                 .num_pads = ARRAY_SIZE(mmc1_pads),
 367                 .clkid = MXC_ESDHC2_CLK,
 368                 .cfg = {
 369                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
 370                         .max_bus_width = 4,
 371                 },
 372                 .cd_gpio = IMX_GPIO_NR(7, 3),
 373         },
 374 };
 375
 376 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 377 {
 378         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
 379 }
 380
 381 int board_mmc_getcd(struct mmc *mmc)
 382 {
 383         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
 384
 385         if (cfg->cd_gpio < 0)
 386                 return 1;
 387
 388         debug("SD card %d is %spresent (GPIO %d)\n",
 389                 cfg - tx6qdl_esdhc_cfg,
 390                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
 391                 cfg->cd_gpio);
 392         return !gpio_get_value(cfg->cd_gpio);
 393 }
 394
 395 int board_mmc_init(bd_t *bis)
 396 {
 397         int i;
 398
 399         for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
 400                 struct mmc *mmc;
 401                 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
 402                 int ret;
 403
 404                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
 405                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
 406
 407                 if (cfg->cd_gpio >= 0) {
 408                         ret = gpio_request_one(cfg->cd_gpio,
 409                                         GPIOFLAG_INPUT, "MMC CD");
 410                         if (ret) {
 411                                 printf("Error %d requesting GPIO%d_%d\n",
 412                                         ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 413                                 continue;
 414                         }
 415                 }
 416
 417                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 418                 fsl_esdhc_initialize(bis, &cfg->cfg);
 419
 420                 mmc = find_mmc_device(i);
 421                 if (mmc == NULL)
 422                         continue;
 423                 if (board_mmc_getcd(mmc))
 424                         mmc_init(mmc);
 425         }
 426         return 0;
 427 }
 428 #endif /* CONFIG_CMD_MMC */
 429
 430 #ifdef CONFIG_FEC_MXC
 431
 432 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
 433                         PAD_CTL_SRE_FAST)
 434 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
 435 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 436
 437 #ifndef ETH_ALEN
 438 #define ETH_ALEN 6
 439 #endif
 440
 441 int board_eth_init(bd_t *bis)
 442 {
 443         int ret;
 444
 445         /* delay at least 21ms for the PHY internal POR signal to deassert */
 446         udelay(22000);
 447
 448         imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads,
 449                                         ARRAY_SIZE(tx6qdl_fec_pads));
 450
 451         /* Deassert RESET to the external phy */
 452         gpio_set_value(TX6_FEC_RST_GPIO, 1);
 453
 454         ret = cpu_eth_init(bis);
 455         if (ret)
 456                 printf("cpu_eth_init() failed: %d\n", ret);
 457
 458         return ret;
 459 }
 460
 461 static void tx6_init_mac(void)
 462 {
 463         u8 mac[ETH_ALEN];
 464
 465         imx_get_mac_from_fuse(-1, mac);
 466         if (!is_valid_ether_addr(mac)) {
 467                 printf("No valid MAC address programmed\n");
 468                 return;
 469         }
 470
 471         printf("MAC addr from fuse: %pM\n", mac);
 472         eth_setenv_enetaddr("ethaddr", mac);
 473 }
 474 #else
 475 static inline void tx6_init_mac(void)
 476 {
 477 }
 478 #endif /* CONFIG_FEC_MXC */
 479
 480 enum {
 481         LED_STATE_INIT = -1,
 482         LED_STATE_OFF,
 483         LED_STATE_ON,
 484 };
 485
 486 static inline int calc_blink_rate(void)
 487 {
 488         if (!tx6_temp_check_enabled)
 489                 return CONFIG_SYS_HZ;
 490
 491         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
 492                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
 493                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
 494 }
 495
 496 void show_activity(int arg)
 497 {
 498         static int led_state = LED_STATE_INIT;
 499         static int blink_rate;
 500         static ulong last;
 501
 502         if (led_state == LED_STATE_INIT) {
 503                 last = get_timer(0);
 504                 gpio_set_value(TX6_LED_GPIO, 1);
 505                 led_state = LED_STATE_ON;
 506                 blink_rate = calc_blink_rate();
 507         } else {
 508                 if (get_timer(last) > blink_rate) {
 509                         blink_rate = calc_blink_rate();
 510                         last = get_timer_masked();
 511                         if (led_state == LED_STATE_ON) {
 512                                 gpio_set_value(TX6_LED_GPIO, 0);
 513                         } else {
 514                                 gpio_set_value(TX6_LED_GPIO, 1);
 515                         }
 516                         led_state = 1 - led_state;
 517                 }
 518         }
 519 }
 520
 521 static const iomux_v3_cfg_t stk5_pads[] = {
 522         /* SW controlled LED on STK5 baseboard */
 523         MX6_PAD_EIM_A18__GPIO2_IO20,
 524
 525         /* I2C bus on DIMM pins 40/41 */
 526         MX6_PAD_GPIO_6__I2C3_SDA,
 527         MX6_PAD_GPIO_3__I2C3_SCL,
 528
 529         /* TSC200x PEN IRQ */
 530         MX6_PAD_EIM_D26__GPIO3_IO26,
 531
 532         /* EDT-FT5x06 Polytouch panel */
 533         MX6_PAD_NANDF_CS2__GPIO6_IO15, /* IRQ */
 534         MX6_PAD_EIM_A16__GPIO2_IO22, /* RESET */
 535         MX6_PAD_EIM_A17__GPIO2_IO21, /* WAKE */
 536
 537         /* USBH1 */
 538         MX6_PAD_EIM_D31__GPIO3_IO31, /* VBUSEN */
 539         MX6_PAD_EIM_D30__GPIO3_IO30, /* OC */
 540         /* USBOTG */
 541         MX6_PAD_EIM_D23__GPIO3_IO23, /* USBOTG ID */
 542         MX6_PAD_GPIO_7__GPIO1_IO07, /* VBUSEN */
 543         MX6_PAD_GPIO_8__GPIO1_IO08, /* OC */
 544 };
 545
 546 static const struct gpio stk5_gpios[] = {
 547         { TX6_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 548
 549         { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
 550         { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
 551         { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 552         { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
 553         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 554 };
 555
 556 #ifdef CONFIG_LCD
 557 static u16 tx6_cmap[256];
 558 vidinfo_t panel_info = {
 559         /* set to max. size supported by SoC */
 560         .vl_col = 1920,
 561         .vl_row = 1080,
 562
 563         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 564         .cmap = tx6_cmap,
 565 };
 566
 567 static struct fb_videomode tx6_fb_modes[] = {
 568 #ifndef CONFIG_SYS_LVDS_IF
 569         {
 570                 /* Standard VGA timing */
 571                 .name           = "VGA",
 572                 .refresh        = 60,
 573                 .xres           = 640,
 574                 .yres           = 480,
 575                 .pixclock       = KHZ2PICOS(25175),
 576                 .left_margin    = 48,
 577                 .hsync_len      = 96,
 578                 .right_margin   = 16,
 579                 .upper_margin   = 31,
 580                 .vsync_len      = 2,
 581                 .lower_margin   = 12,
 582                 .sync           = FB_SYNC_CLK_LAT_FALL,
 583         },
 584         {
 585                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 586                  * DE high active, 115.2 mm x 86.4 mm display area
 587                  * VGA compatible timing
 588                  */
 589                 .name           = "ETV570",
 590                 .refresh        = 60,
 591                 .xres           = 640,
 592                 .yres           = 480,
 593                 .pixclock       = KHZ2PICOS(25175),
 594                 .left_margin    = 114,
 595                 .hsync_len      = 30,
 596                 .right_margin   = 16,
 597                 .upper_margin   = 32,
 598                 .vsync_len      = 3,
 599                 .lower_margin   = 10,
 600                 .sync           = FB_SYNC_CLK_LAT_FALL,
 601         },
 602         {
 603                 /* Emerging ET0350G0DH6 320 x 240 display.
 604                  * 70.08 mm x 52.56 mm display area.
 605                  */
 606                 .name           = "ET0350",
 607                 .refresh        = 60,
 608                 .xres           = 320,
 609                 .yres           = 240,
 610                 .pixclock       = KHZ2PICOS(6500),
 611                 .left_margin    = 68 - 34,
 612                 .hsync_len      = 34,
 613                 .right_margin   = 20,
 614                 .upper_margin   = 18 - 3,
 615                 .vsync_len      = 3,
 616                 .lower_margin   = 4,
 617                 .sync           = FB_SYNC_CLK_LAT_FALL,
 618         },
 619         {
 620                 /* Emerging ET0430G0DH6 480 x 272 display.
 621                  * 95.04 mm x 53.856 mm display area.
 622                  */
 623                 .name           = "ET0430",
 624                 .refresh        = 60,
 625                 .xres           = 480,
 626                 .yres           = 272,
 627                 .pixclock       = KHZ2PICOS(9000),
 628                 .left_margin    = 2,
 629                 .hsync_len      = 41,
 630                 .right_margin   = 2,
 631                 .upper_margin   = 2,
 632                 .vsync_len      = 10,
 633                 .lower_margin   = 2,
 634         },
 635         {
 636                 /* Emerging ET0500G0DH6 800 x 480 display.
 637                  * 109.6 mm x 66.4 mm display area.
 638                  */
 639                 .name           = "ET0500",
 640                 .refresh        = 60,
 641                 .xres           = 800,
 642                 .yres           = 480,
 643                 .pixclock       = KHZ2PICOS(33260),
 644                 .left_margin    = 216 - 128,
 645                 .hsync_len      = 128,
 646                 .right_margin   = 1056 - 800 - 216,
 647                 .upper_margin   = 35 - 2,
 648                 .vsync_len      = 2,
 649                 .lower_margin   = 525 - 480 - 35,
 650                 .sync           = FB_SYNC_CLK_LAT_FALL,
 651         },
 652         {
 653                 /* Emerging ETQ570G0DH6 320 x 240 display.
 654                  * 115.2 mm x 86.4 mm display area.
 655                  */
 656                 .name           = "ETQ570",
 657                 .refresh        = 60,
 658                 .xres           = 320,
 659                 .yres           = 240,
 660                 .pixclock       = KHZ2PICOS(6400),
 661                 .left_margin    = 38,
 662                 .hsync_len      = 30,
 663                 .right_margin   = 30,
 664                 .upper_margin   = 16, /* 15 according to datasheet */
 665                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 666                 .lower_margin   = 4, /* 4.5 according to datasheet */
 667                 .sync           = FB_SYNC_CLK_LAT_FALL,
 668         },
 669         {
 670                 /* Emerging ET0700G0DH6 800 x 480 display.
 671                  * 152.4 mm x 91.44 mm display area.
 672                  */
 673                 .name           = "ET0700",
 674                 .refresh        = 60,
 675                 .xres           = 800,
 676                 .yres           = 480,
 677                 .pixclock       = KHZ2PICOS(33260),
 678                 .left_margin    = 216 - 128,
 679                 .hsync_len      = 128,
 680                 .right_margin   = 1056 - 800 - 216,
 681                 .upper_margin   = 35 - 2,
 682                 .vsync_len      = 2,
 683                 .lower_margin   = 525 - 480 - 35,
 684                 .sync           = FB_SYNC_CLK_LAT_FALL,
 685         },
 686         {
 687                 /* Emerging ET070001DM6 800 x 480 display.
 688                  * 152.4 mm x 91.44 mm display area.
 689                  */
 690                 .name           = "ET070001DM6",
 691                 .refresh        = 60,
 692                 .xres           = 800,
 693                 .yres           = 480,
 694                 .pixclock       = KHZ2PICOS(33260),
 695                 .left_margin    = 216 - 128,
 696                 .hsync_len      = 128,
 697                 .right_margin   = 1056 - 800 - 216,
 698                 .upper_margin   = 35 - 2,
 699                 .vsync_len      = 2,
 700                 .lower_margin   = 525 - 480 - 35,
 701                 .sync           = 0,
 702         },
 703 #else
 704         {
 705                 /* HannStar HSD100PXN1
 706                  * 202.7m mm x 152.06 mm display area.
 707                  */
 708                 .name           = "HSD100PXN1",
 709                 .refresh        = 60,
 710                 .xres           = 1024,
 711                 .yres           = 768,
 712                 .pixclock       = KHZ2PICOS(65000),
 713                 .left_margin    = 0,
 714                 .hsync_len      = 0,
 715                 .right_margin   = 320,
 716                 .upper_margin   = 0,
 717                 .vsync_len      = 0,
 718                 .lower_margin   = 38,
 719                 .sync           = FB_SYNC_CLK_LAT_FALL,
 720         },
 721 #endif
 722         {
 723                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 724                 .refresh        = 60,
 725                 .left_margin    = 48,
 726                 .hsync_len      = 96,
 727                 .right_margin   = 16,
 728                 .upper_margin   = 31,
 729                 .vsync_len      = 2,
 730                 .lower_margin   = 12,
 731                 .sync           = FB_SYNC_CLK_LAT_FALL,
 732         },
 733 };
 734
 735 static int lcd_enabled = 1;
 736 static int lcd_bl_polarity;
 737
 738 static int lcd_backlight_polarity(void)
 739 {
 740         return lcd_bl_polarity;
 741 }
 742
 743 void lcd_enable(void)
 744 {
 745         /* HACK ALERT:
 746          * global variable from common/lcd.c
 747          * Set to 0 here to prevent messages from going to LCD
 748          * rather than serial console
 749          */
 750         lcd_is_enabled = 0;
 751
 752         if (lcd_enabled) {
 753                 karo_load_splashimage(1);
 754
 755                 debug("Switching LCD on\n");
 756                 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
 757                 udelay(100);
 758                 gpio_set_value(TX6_LCD_RST_GPIO, 1);
 759                 udelay(300000);
 760                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
 761                         lcd_backlight_polarity());
 762         }
 763 }
 764
 765 void lcd_disable(void)
 766 {
 767         if (lcd_enabled) {
 768                 printf("Disabling LCD\n");
 769                 ipuv3_fb_shutdown();
 770         }
 771 }
 772
 773 void lcd_panel_disable(void)
 774 {
 775         if (lcd_enabled) {
 776                 debug("Switching LCD off\n");
 777                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
 778                         !lcd_backlight_polarity());
 779                 gpio_set_value(TX6_LCD_RST_GPIO, 0);
 780                 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
 781         }
 782 }
 783
 784 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 785         /* LCD RESET */
 786         MX6_PAD_EIM_D29__GPIO3_IO29,
 787         /* LCD POWER_ENABLE */
 788         MX6_PAD_EIM_EB3__GPIO2_IO31,
 789         /* LCD Backlight (PWM) */
 790         MX6_PAD_GPIO_1__GPIO1_IO01,
 791
 792 #ifndef CONFIG_SYS_LVDS_IF
 793         /* Display */
 794         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
 795         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
 796         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
 797         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
 798         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
 799         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
 800         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
 801         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
 802         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
 803         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
 804         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
 805         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
 806         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
 807         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
 808         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
 809         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
 810         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
 811         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
 812         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
 813         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
 814         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
 815         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
 816         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
 817         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
 818         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSYNC */
 819         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSYNC */
 820         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
 821         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
 822 #endif
 823 };
 824
 825 static const struct gpio stk5_lcd_gpios[] = {
 826         { TX6_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
 827         { TX6_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
 828         { TX6_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 829 };
 830
 831 void lcd_ctrl_init(void *lcdbase)
 832 {
 833         int color_depth = 24;
 834         const char *video_mode = karo_get_vmode(getenv("video_mode"));
 835         const char *vm;
 836         unsigned long val;
 837         int refresh = 60;
 838         struct fb_videomode *p = &tx6_fb_modes[0];
 839         struct fb_videomode fb_mode;
 840         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 841         int pix_fmt;
 842         int lcd_bus_width;
 843         unsigned long di_clk_rate = 65000000;
 844
 845         if (!lcd_enabled) {
 846                 debug("LCD disabled\n");
 847                 return;
 848         }
 849
 850         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
 851                 debug("Disabling LCD\n");
 852                 lcd_enabled = 0;
 853                 setenv("splashimage", NULL);
 854                 return;
 855         }
 856
 857         karo_fdt_move_fdt();
 858         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
 859
 860         if (video_mode == NULL) {
 861                 debug("Disabling LCD\n");
 862                 lcd_enabled = 0;
 863                 return;
 864         }
 865         vm = video_mode;
 866         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
 867                 p = &fb_mode;
 868                 debug("Using video mode from FDT\n");
 869                 vm += strlen(vm);
 870                 if (fb_mode.xres > panel_info.vl_col ||
 871                         fb_mode.yres > panel_info.vl_row) {
 872                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
 873                                 fb_mode.xres, fb_mode.yres,
 874                                 panel_info.vl_col, panel_info.vl_row);
 875                         lcd_enabled = 0;
 876                         return;
 877                 }
 878         }
 879         if (p->name != NULL)
 880                 debug("Trying compiled-in video modes\n");
 881         while (p->name != NULL) {
 882                 if (strcmp(p->name, vm) == 0) {
 883                         debug("Using video mode: '%s'\n", p->name);
 884                         vm += strlen(vm);
 885                         break;
 886                 }
 887                 p++;
 888         }
 889         if (*vm != '\0')
 890                 debug("Trying to decode video_mode: '%s'\n", vm);
 891         while (*vm != '\0') {
 892                 if (*vm >= '0' && *vm <= '9') {
 893                         char *end;
 894
 895                         val = simple_strtoul(vm, &end, 0);
 896                         if (end > vm) {
 897                                 if (!xres_set) {
 898                                         if (val > panel_info.vl_col)
 899                                                 val = panel_info.vl_col;
 900                                         p->xres = val;
 901                                         panel_info.vl_col = val;
 902                                         xres_set = 1;
 903                                 } else if (!yres_set) {
 904                                         if (val > panel_info.vl_row)
 905                                                 val = panel_info.vl_row;
 906                                         p->yres = val;
 907                                         panel_info.vl_row = val;
 908                                         yres_set = 1;
 909                                 } else if (!bpp_set) {
 910                                         switch (val) {
 911                                         case 32:
 912                                         case 24:
 913                                                 if (is_lvds())
 914                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
 915                                                 /* fallthru */
 916                                         case 16:
 917                                         case 8:
 918                                                 color_depth = val;
 919                                                 break;
 920
 921                                         case 18:
 922                                                 if (is_lvds()) {
 923                                                         color_depth = val;
 924                                                         break;
 925                                                 }
 926                                                 /* fallthru */
 927                                         default:
 928                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
 929                                                         end - vm, vm, color_depth);
 930                                         }
 931                                         bpp_set = 1;
 932                                 } else if (!refresh_set) {
 933                                         refresh = val;
 934                                         refresh_set = 1;
 935                                 }
 936                         }
 937                         vm = end;
 938                 }
 939                 switch (*vm) {
 940                 case '@':
 941                         bpp_set = 1;
 942                         /* fallthru */
 943                 case '-':
 944                         yres_set = 1;
 945                         /* fallthru */
 946                 case 'x':
 947                         xres_set = 1;
 948                         /* fallthru */
 949                 case 'M':
 950                 case 'R':
 951                         vm++;
 952                         break;
 953
 954                 default:
 955                         if (*vm != '\0')
 956                                 vm++;
 957                 }
 958         }
 959         if (p->xres == 0 || p->yres == 0) {
 960                 printf("Invalid video mode: %s\n", getenv("video_mode"));
 961                 lcd_enabled = 0;
 962                 printf("Supported video modes are:");
 963                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
 964                         printf(" %s", p->name);
 965                 }
 966                 printf("\n");
 967                 return;
 968         }
 969         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
 970                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
 971                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
 972                 lcd_enabled = 0;
 973                 return;
 974         }
 975         panel_info.vl_col = p->xres;
 976         panel_info.vl_row = p->yres;
 977
 978         switch (color_depth) {
 979         case 8:
 980                 panel_info.vl_bpix = LCD_COLOR8;
 981                 break;
 982         case 16:
 983                 panel_info.vl_bpix = LCD_COLOR16;
 984                 break;
 985         default:
 986                 panel_info.vl_bpix = LCD_COLOR32;
 987         }
 988
 989         p->pixclock = KHZ2PICOS(refresh *
 990                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
 991                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
 992                                 1000);
 993         debug("Pixel clock set to %lu.%03lu MHz\n",
 994                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
 995
 996         if (p != &fb_mode) {
 997                 int ret;
 998
 999                 debug("Creating new display-timing node from '%s'\n",
1000                         video_mode);
1001                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1002                 if (ret)
1003                         printf("Failed to create new display-timing node from '%s': %d\n",
1004                                 video_mode, ret);
1005         }
1006
1007         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1008         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1009                                         ARRAY_SIZE(stk5_lcd_pads));
1010
1011         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1012         switch (lcd_bus_width) {
1013         case 24:
1014                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1015                 break;
1016
1017         case 18:
1018                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1019                 break;
1020
1021         case 16:
1022                 if (!is_lvds()) {
1023                         pix_fmt = IPU_PIX_FMT_RGB565;
1024                         break;
1025                 }
1026                 /* fallthru */
1027         default:
1028                 lcd_enabled = 0;
1029                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1030                         lcd_bus_width);
1031                 return;
1032         }
1033         if (is_lvds()) {
1034                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1035                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1036                 uint32_t gpr2;
1037                 uint32_t gpr3;
1038
1039                 if (lvds_chan_mask == 0) {
1040                         printf("No LVDS channel active\n");
1041                         lcd_enabled = 0;
1042                         return;
1043                 }
1044
1045                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1046                 if (lcd_bus_width == 24)
1047                         gpr2 |= (1 << 5) | (1 << 7);
1048                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1049                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1050                 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1051                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1052
1053                 gpr3 = readl(IOMUXC_BASE_ADDR + 0xc);
1054                 gpr3 &= ~((3 << 8) | (3 << 6));
1055                 writel(gpr3, IOMUXC_BASE_ADDR + 0xc);
1056         }
1057         if (karo_load_splashimage(0) == 0) {
1058                 int ret;
1059
1060                 debug("Initializing LCD controller\n");
1061                 ret = ipuv3_fb_init(p, 0, pix_fmt,
1062                                 is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
1063                                 di_clk_rate, -1);
1064                 if (ret) {
1065                         printf("Failed to initialize FB driver: %d\n", ret);
1066                         lcd_enabled = 0;
1067                 }
1068         } else {
1069                 debug("Skipping initialization of LCD controller\n");
1070         }
1071 }
1072 #else
1073 #define lcd_enabled 0
1074 #endif /* CONFIG_LCD */
1075
1076 static void stk5_board_init(void)
1077 {
1078         int ret;
1079
1080         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1081         if (ret < 0) {
1082                 printf("Failed to request stk5_gpios: %d\n", ret);
1083                 return;
1084         }
1085         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1086 }
1087
1088 static void stk5v3_board_init(void)
1089 {
1090         stk5_board_init();
1091 }
1092
1093 static void stk5v5_board_init(void)
1094 {
1095         int ret;
1096
1097         stk5_board_init();
1098
1099         ret = gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH,
1100                         "Flexcan Transceiver");
1101         if (ret) {
1102                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1103                 return;
1104         }
1105
1106         imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21);
1107 }
1108
1109 static void tx6qdl_set_cpu_clock(void)
1110 {
1111         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1112
1113         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1114                 return;
1115
1116         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1117                 printf("%s detected; skipping cpu clock change\n",
1118                         (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1119                 return;
1120         }
1121         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1122                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1123                 printf("CPU clock set to %lu.%03lu MHz\n",
1124                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1125         } else {
1126                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1127         }
1128 }
1129
1130 int board_late_init(void)
1131 {
1132         int ret = 0;
1133         const char *baseboard;
1134
1135         env_cleanup();
1136
1137         if (tx6_temp_check_enabled)
1138                 check_cpu_temperature(1);
1139
1140         tx6qdl_set_cpu_clock();
1141
1142         if (had_ctrlc())
1143                 setenv_ulong("safeboot", 1);
1144         else if (wrsr & WRSR_TOUT)
1145                 setenv_ulong("wdreset", 1);
1146         else
1147                 karo_fdt_move_fdt();
1148
1149         baseboard = getenv("baseboard");
1150         if (!baseboard)
1151                 goto exit;
1152
1153         printf("Baseboard: %s\n", baseboard);
1154
1155         if (strncmp(baseboard, "stk5", 4) == 0) {
1156                 if ((strlen(baseboard) == 4) ||
1157                         strcmp(baseboard, "stk5-v3") == 0) {
1158                         stk5v3_board_init();
1159                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1160                         const char *otg_mode = getenv("otg_mode");
1161
1162                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1163                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1164                                         otg_mode, baseboard);
1165                                 setenv("otg_mode", "none");
1166                         }
1167                         stk5v5_board_init();
1168                 } else {
1169                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1170                                 baseboard + 4);
1171                 }
1172         } else {
1173                 printf("WARNING: Unsupported baseboard: '%s'\n",
1174                         baseboard);
1175                 ret = -EINVAL;
1176         }
1177
1178 exit:
1179         tx6_init_mac();
1180
1181         gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1182         clear_ctrlc();
1183         return ret;
1184 }
1185
1186 #ifdef CONFIG_TX6_NAND
1187 #define TX6_FLASH_SZ    (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
1188 #else
1189 #ifdef CONFIG_MMC_BOOT_SIZE
1190 #define TX6_FLASH_SZ    (CONFIG_MMC_BOOT_SIZE / 4096 + 2)
1191 #else
1192 #define TX6_FLASH_SZ    2
1193 #endif
1194 #endif /* CONFIG_TX6_NAND */
1195
1196 #define TX6_DDR_SZ      (ffs(PHYS_SDRAM_1_WIDTH / 16) - 1)
1197
1198 static char tx6_mem_table[] = {
1199         '4', /* 256MiB SDRAM 16bit; 128MiB NAND */
1200         '1', /* 512MiB SDRAM 32bit; 128MiB NAND */
1201         '0', /* 1GiB SDRAM 64bit; 128MiB NAND */
1202         '?', /* 256MiB SDRAM 16bit; 256MiB NAND */
1203         '?', /* 512MiB SDRAM 32bit; 256MiB NAND */
1204         '2', /* 1GiB SDRAM 64bit; 256MiB NAND */
1205         '?', /* 256MiB SDRAM 16bit; 4GiB eMMC */
1206         '5', /* 512MiB SDRAM 32bit; 4GiB eMMC */
1207         '3', /* 1GiB SDRAM 64bit; 4GiB eMMC */
1208         '?', /* 256MiB SDRAM 16bit; 8GiB eMMC */
1209         '?', /* 512MiB SDRAM 32bit; 8GiB eMMC */
1210         '0', /* 1GiB SDRAM 64bit; 8GiB eMMC */
1211 };
1212
1213 static inline char tx6_mem_suffix(void)
1214 {
1215         size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
1216
1217         debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
1218                 TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
1219
1220         if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
1221                 return '?';
1222
1223         return tx6_mem_table[mem_idx];
1224 };
1225
1226 static struct {
1227         uchar addr;
1228         uchar rev;
1229 } tx6_mod_revs[] = {
1230         { 0x3c, 1, },
1231         { 0x32, 2, },
1232         { 0x33, 3, },
1233 };
1234
1235 static int tx6_get_mod_rev(unsigned int pmic_id)
1236 {
1237         if (pmic_id < ARRAY_SIZE(tx6_mod_revs))
1238                 return tx6_mod_revs[pmic_id].rev;
1239
1240         return 0;
1241 }
1242
1243 static int tx6_pmic_probe(void)
1244 {
1245         int i;
1246
1247         i2c_init_all();
1248
1249         for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) {
1250                 u8 i2c_addr = tx6_mod_revs[i].addr;
1251                 int ret = i2c_probe(i2c_addr);
1252
1253                 if (ret == 0) {
1254                         debug("I2C probe succeeded for addr 0x%02x\n", i2c_addr);
1255                         return i;
1256                 }
1257                 debug("I2C probe returned %d for addr 0x%02x\n", ret, i2c_addr);
1258         }
1259         return -EINVAL;
1260 }
1261
1262 int checkboard(void)
1263 {
1264         u32 cpurev = get_cpu_rev();
1265         int cpu_variant = (cpurev >> 12) & 0xff;
1266         int pmic_id;
1267
1268         tx6qdl_print_cpuinfo();
1269
1270         pmic_id = tx6_pmic_probe();
1271         if (pmic_id >= 0)
1272                 pmic_addr = tx6_mod_revs[pmic_id].addr;
1273
1274         printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
1275                 tx6_mod_suffix,
1276                 cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
1277                 is_lvds(), tx6_get_mod_rev(pmic_id),
1278                 tx6_mem_suffix());
1279
1280         return 0;
1281 }
1282
1283 #ifdef CONFIG_SERIAL_TAG
1284 void get_board_serial(struct tag_serialnr *serialnr)
1285 {
1286         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1287         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1288
1289         serialnr->low = readl(&fuse->cfg0);
1290         serialnr->high = readl(&fuse->cfg1);
1291 }
1292 #endif
1293
1294 #if defined(CONFIG_OF_BOARD_SETUP)
1295 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1296 #include <jffs2/jffs2.h>
1297 #include <mtd_node.h>
1298 static struct node_info nodes[] = {
1299         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1300 };
1301 #else
1302 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1303 #endif
1304
1305 static const char *tx6_touchpanels[] = {
1306         "ti,tsc2007",
1307         "edt,edt-ft5x06",
1308         "eeti,egalax_ts",
1309 };
1310
1311 int ft_board_setup(void *blob, bd_t *bd)
1312 {
1313         const char *baseboard = getenv("baseboard");
1314         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1315         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1316         int ret;
1317
1318         ret = fdt_increase_size(blob, 4096);
1319         if (ret) {
1320                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1321                 return ret;
1322         }
1323         if (stk5_v5)
1324                 karo_fdt_enable_node(blob, "stk5led", 0);
1325
1326         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1327         fdt_fixup_ethernet(blob);
1328
1329         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1330                                 ARRAY_SIZE(tx6_touchpanels));
1331         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1332         karo_fdt_fixup_flexcan(blob, stk5_v5);
1333
1334         karo_fdt_update_fb_mode(blob, video_mode);
1335
1336         return 0;
1337 }
1338 #endif /* CONFIG_OF_BOARD_SETUP */