board/karo/tx6/tx6qdl.c

   1 /*
   2  * Copyright (C) 2012,2013 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * version 2 as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <common.h>
  19 #include <errno.h>
  20 #include <libfdt.h>
  21 #include <fdt_support.h>
  22 #include <lcd.h>
  23 #include <netdev.h>
  24 #include <mmc.h>
  25 #include <fsl_esdhc.h>
  26 #include <video_fb.h>
  27 #include <ipu.h>
  28 #include <mxcfb.h>
  29 #include <i2c.h>
  30 #include <linux/fb.h>
  31 #include <asm/io.h>
  32 #include <asm/gpio.h>
  33 #include <asm/arch/mx6-pins.h>
  34 #include <asm/arch/clock.h>
  35 #include <asm/arch/imx-regs.h>
  36 #include <asm/arch/crm_regs.h>
  37 #include <asm/arch/sys_proto.h>
  38
  39 #include "../common/karo.h"
  40 #include "pmic.h"
  41
  42 #define TX6_FEC_RST_GPIO                IMX_GPIO_NR(7, 6)
  43 #define TX6_FEC_PWR_GPIO                IMX_GPIO_NR(3, 20)
  44 #define TX6_FEC_INT_GPIO                IMX_GPIO_NR(7, 1)
  45 #define TX6_LED_GPIO                    IMX_GPIO_NR(2, 20)
  46
  47 #define TX6_LCD_PWR_GPIO                IMX_GPIO_NR(2, 31)
  48 #define TX6_LCD_RST_GPIO                IMX_GPIO_NR(3, 29)
  49 #define TX6_LCD_BACKLIGHT_GPIO          IMX_GPIO_NR(1, 1)
  50
  51 #define TX6_RESET_OUT_GPIO              IMX_GPIO_NR(7, 12)
  52
  53 #ifdef CONFIG_MX6_TEMPERATURE_MIN
  54 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
  55 #else
  56 #define TEMPERATURE_MIN                 (-40)
  57 #endif
  58 #ifdef CONFIG_MX6_TEMPERATURE_HOT
  59 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
  60 #else
  61 #define TEMPERATURE_HOT                 80
  62 #endif
  63
  64 DECLARE_GLOBAL_DATA_PTR;
  65
  66 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  67
  68 static const iomux_v3_cfg_t tx6qdl_pads[] = {
  69 #ifndef CONFIG_NO_NAND
  70         /* NAND flash pads */
  71         MX6_PAD_NANDF_CLE__RAWNAND_CLE,
  72         MX6_PAD_NANDF_ALE__RAWNAND_ALE,
  73         MX6_PAD_NANDF_WP_B__RAWNAND_RESETN,
  74         MX6_PAD_NANDF_RB0__RAWNAND_READY0,
  75         MX6_PAD_NANDF_CS0__RAWNAND_CE0N,
  76         MX6_PAD_SD4_CMD__RAWNAND_RDN,
  77         MX6_PAD_SD4_CLK__RAWNAND_WRN,
  78         MX6_PAD_NANDF_D0__RAWNAND_D0,
  79         MX6_PAD_NANDF_D1__RAWNAND_D1,
  80         MX6_PAD_NANDF_D2__RAWNAND_D2,
  81         MX6_PAD_NANDF_D3__RAWNAND_D3,
  82         MX6_PAD_NANDF_D4__RAWNAND_D4,
  83         MX6_PAD_NANDF_D5__RAWNAND_D5,
  84         MX6_PAD_NANDF_D6__RAWNAND_D6,
  85         MX6_PAD_NANDF_D7__RAWNAND_D7,
  86 #endif
  87         /* RESET_OUT */
  88         MX6_PAD_GPIO_17__GPIO_7_12,
  89
  90         /* UART pads */
  91 #if CONFIG_MXC_UART_BASE == UART1_BASE
  92         MX6_PAD_SD3_DAT7__UART1_TXD,
  93         MX6_PAD_SD3_DAT6__UART1_RXD,
  94         MX6_PAD_SD3_DAT1__UART1_RTS,
  95         MX6_PAD_SD3_DAT0__UART1_CTS,
  96 #endif
  97 #if CONFIG_MXC_UART_BASE == UART2_BASE
  98         MX6_PAD_SD4_DAT4__UART2_RXD,
  99         MX6_PAD_SD4_DAT7__UART2_TXD,
 100         MX6_PAD_SD4_DAT5__UART2_RTS,
 101         MX6_PAD_SD4_DAT6__UART2_CTS,
 102 #endif
 103 #if CONFIG_MXC_UART_BASE == UART3_BASE
 104         MX6_PAD_EIM_D24__UART3_TXD,
 105         MX6_PAD_EIM_D25__UART3_RXD,
 106         MX6_PAD_SD3_RST__UART3_RTS,
 107         MX6_PAD_SD3_DAT3__UART3_CTS,
 108 #endif
 109         /* internal I2C */
 110         MX6_PAD_EIM_D28__I2C1_SDA,
 111         MX6_PAD_EIM_D21__I2C1_SCL,
 112
 113         /* FEC PHY GPIO functions */
 114         MX6_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */
 115         MX6_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */
 116         MX6_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */
 117 };
 118
 119 static const iomux_v3_cfg_t tx6qdl_fec_pads[] = {
 120         /* FEC functions */
 121         MX6_PAD_ENET_MDC__ENET_MDC,
 122         MX6_PAD_ENET_MDIO__ENET_MDIO,
 123         MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
 124         MX6_PAD_ENET_RX_ER__ENET_RX_ER,
 125         MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
 126         MX6_PAD_ENET_RXD1__ENET_RDATA_1,
 127         MX6_PAD_ENET_RXD0__ENET_RDATA_0,
 128         MX6_PAD_ENET_TX_EN__ENET_TX_EN,
 129         MX6_PAD_ENET_TXD1__ENET_TDATA_1,
 130         MX6_PAD_ENET_TXD0__ENET_TDATA_0,
 131 };
 132
 133 static const struct gpio tx6qdl_gpios[] = {
 134         { TX6_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
 135         { TX6_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 136         { TX6_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 137         { TX6_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
 138 };
 139
 140 /*
 141  * Functions
 142  */
 143 /* placed in section '.data' to prevent overwriting relocation info
 144  * overlayed with bss
 145  */
 146 static u32 wrsr __attribute__((section(".data")));
 147
 148 #define WRSR_POR                        (1 << 4)
 149 #define WRSR_TOUT                       (1 << 1)
 150 #define WRSR_SFTW                       (1 << 0)
 151
 152 static void print_reset_cause(void)
 153 {
 154         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 155         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 156         u32 srsr;
 157         char *dlm = "";
 158
 159         printf("Reset cause: ");
 160
 161         srsr = readl(&src_regs->srsr);
 162         wrsr = readw(wdt_base + 4);
 163
 164         if (wrsr & WRSR_POR) {
 165                 printf("%sPOR", dlm);
 166                 dlm = " | ";
 167         }
 168         if (srsr & 0x00004) {
 169                 printf("%sCSU", dlm);
 170                 dlm = " | ";
 171         }
 172         if (srsr & 0x00008) {
 173                 printf("%sIPP USER", dlm);
 174                 dlm = " | ";
 175         }
 176         if (srsr & 0x00010) {
 177                 if (wrsr & WRSR_SFTW) {
 178                         printf("%sSOFT", dlm);
 179                         dlm = " | ";
 180                 }
 181                 if (wrsr & WRSR_TOUT) {
 182                         printf("%sWDOG", dlm);
 183                         dlm = " | ";
 184                 }
 185         }
 186         if (srsr & 0x00020) {
 187                 printf("%sJTAG HIGH-Z", dlm);
 188                 dlm = " | ";
 189         }
 190         if (srsr & 0x00040) {
 191                 printf("%sJTAG SW", dlm);
 192                 dlm = " | ";
 193         }
 194         if (srsr & 0x10000) {
 195                 printf("%sWARM BOOT", dlm);
 196                 dlm = " | ";
 197         }
 198         if (dlm[0] == '\0')
 199                 printf("unknown");
 200
 201         printf("\n");
 202 }
 203
 204 static const char *tx6_mod_suffix;
 205
 206 static void tx6qdl_print_cpuinfo(void)
 207 {
 208         u32 cpurev = get_cpu_rev();
 209         char *cpu_str = "?";
 210
 211         switch ((cpurev >> 12) & 0xff) {
 212         case MXC_CPU_MX6SL:
 213                 cpu_str = "SL";
 214                 tx6_mod_suffix = "?";
 215                 break;
 216         case MXC_CPU_MX6DL:
 217                 cpu_str = "DL";
 218                 tx6_mod_suffix = "U";
 219                 break;
 220         case MXC_CPU_MX6SOLO:
 221                 cpu_str = "SOLO";
 222                 tx6_mod_suffix = "S";
 223                 break;
 224         case MXC_CPU_MX6Q:
 225                 cpu_str = "Q";
 226                 tx6_mod_suffix = "Q";
 227                 break;
 228         }
 229
 230         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
 231                 cpu_str,
 232                 (cpurev & 0x000F0) >> 4,
 233                 (cpurev & 0x0000F) >> 0,
 234                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 235
 236         print_reset_cause();
 237 #ifdef CONFIG_MX6_TEMPERATURE_HOT
 238         check_cpu_temperature(1);
 239 #endif
 240 }
 241
 242 int board_early_init_f(void)
 243 {
 244         gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
 245         imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
 246
 247         return 0;
 248 }
 249
 250 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 251 static bool tx6_temp_check_enabled = true;
 252 #else
 253 #define tx6_temp_check_enabled  0
 254 #endif
 255
 256 int board_init(void)
 257 {
 258         int ret;
 259
 260         /* Address of boot parameters */
 261         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 262         gd->bd->bi_arch_number = -1;
 263
 264         if (ctrlc()) {
 265 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 266                 tx6_temp_check_enabled = false;
 267 #endif
 268                 printf("CTRL-C detected; Skipping PMIC setup\n");
 269                 return 1;
 270         }
 271
 272         ret = setup_pmic_voltages();
 273         if (ret) {
 274                 printf("Failed to setup PMIC voltages\n");
 275                 hang();
 276         }
 277         return 0;
 278 }
 279
 280 int dram_init(void)
 281 {
 282         /* dram_init must store complete ramsize in gd->ram_size */
 283         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 284                                 PHYS_SDRAM_1_SIZE);
 285         return 0;
 286 }
 287
 288 void dram_init_banksize(void)
 289 {
 290         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 291         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 292                         PHYS_SDRAM_1_SIZE);
 293 #if CONFIG_NR_DRAM_BANKS > 1
 294         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 295         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 296                         PHYS_SDRAM_2_SIZE);
 297 #endif
 298 }
 299
 300 #ifdef  CONFIG_CMD_MMC
 301 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
 302         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
 303         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 304
 305 static const iomux_v3_cfg_t mmc0_pads[] = {
 306         MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 307         MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 308         MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 309         MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 310         MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 311         MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 312         /* SD1 CD */
 313         MX6_PAD_SD3_CMD__GPIO_7_2,
 314 };
 315
 316 static const iomux_v3_cfg_t mmc1_pads[] = {
 317         MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 318         MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 319         MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 320         MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 321         MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 322         MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 323         /* SD2 CD */
 324         MX6_PAD_SD3_CLK__GPIO_7_3,
 325 };
 326
 327 #ifdef CONFIG_MMC_BOOT_SIZE
 328 static const iomux_v3_cfg_t mmc3_pads[] = {
 329         MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 330         MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 331         MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 332         MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 333         MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 334         MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 335         /* eMMC RESET */
 336         MX6_PAD_NANDF_ALE__USDHC4_RST,
 337 };
 338 #endif
 339
 340 static struct tx6_esdhc_cfg {
 341         const iomux_v3_cfg_t *pads;
 342         int num_pads;
 343         enum mxc_clock clkid;
 344         struct fsl_esdhc_cfg cfg;
 345         int cd_gpio;
 346 } tx6qdl_esdhc_cfg[] = {
 347 #ifdef CONFIG_MMC_BOOT_SIZE
 348         {
 349                 .pads = mmc3_pads,
 350                 .num_pads = ARRAY_SIZE(mmc3_pads),
 351                 .clkid = MXC_ESDHC4_CLK,
 352                 .cfg = {
 353                         .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
 354                         .max_bus_width = 4,
 355                 },
 356                 .cd_gpio = -EINVAL,
 357         },
 358 #endif
 359         {
 360                 .pads = mmc0_pads,
 361                 .num_pads = ARRAY_SIZE(mmc0_pads),
 362                 .clkid = MXC_ESDHC_CLK,
 363                 .cfg = {
 364                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
 365                         .max_bus_width = 4,
 366                 },
 367                 .cd_gpio = IMX_GPIO_NR(7, 2),
 368         },
 369         {
 370                 .pads = mmc1_pads,
 371                 .num_pads = ARRAY_SIZE(mmc1_pads),
 372                 .clkid = MXC_ESDHC2_CLK,
 373                 .cfg = {
 374                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
 375                         .max_bus_width = 4,
 376                 },
 377                 .cd_gpio = IMX_GPIO_NR(7, 3),
 378         },
 379 };
 380
 381 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 382 {
 383         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
 384 }
 385
 386 int board_mmc_getcd(struct mmc *mmc)
 387 {
 388         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
 389
 390         if (cfg->cd_gpio < 0)
 391                 return 1;
 392
 393         debug("SD card %d is %spresent\n",
 394                 cfg - tx6qdl_esdhc_cfg,
 395                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
 396         return !gpio_get_value(cfg->cd_gpio);
 397 }
 398
 399 int board_mmc_init(bd_t *bis)
 400 {
 401         int i;
 402
 403         for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
 404                 struct mmc *mmc;
 405                 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
 406                 int ret;
 407
 408                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
 409                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
 410
 411                 if (cfg->cd_gpio >= 0) {
 412                         ret = gpio_request_one(cfg->cd_gpio,
 413                                         GPIOF_INPUT, "MMC CD");
 414                         if (ret) {
 415                                 printf("Error %d requesting GPIO%d_%d\n",
 416                                         ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 417                                 continue;
 418                         }
 419                 }
 420
 421                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 422                 fsl_esdhc_initialize(bis, &cfg->cfg);
 423
 424                 mmc = find_mmc_device(i);
 425                 if (mmc == NULL)
 426                         continue;
 427                 if (board_mmc_getcd(mmc))
 428                         mmc_init(mmc);
 429         }
 430         return 0;
 431 }
 432 #endif /* CONFIG_CMD_MMC */
 433
 434 #ifdef CONFIG_FEC_MXC
 435
 436 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
 437                         PAD_CTL_SRE_FAST)
 438 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
 439 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 440
 441 #ifndef ETH_ALEN
 442 #define ETH_ALEN 6
 443 #endif
 444
 445 int board_eth_init(bd_t *bis)
 446 {
 447         int ret;
 448
 449         /* delay at least 21ms for the PHY internal POR signal to deassert */
 450         udelay(22000);
 451
 452         imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads, ARRAY_SIZE(tx6qdl_fec_pads));
 453
 454         /* Deassert RESET to the external phy */
 455         gpio_set_value(TX6_FEC_RST_GPIO, 1);
 456
 457         ret = cpu_eth_init(bis);
 458         if (ret)
 459                 printf("cpu_eth_init() failed: %d\n", ret);
 460
 461         return ret;
 462 }
 463 #endif /* CONFIG_FEC_MXC */
 464
 465 enum {
 466         LED_STATE_INIT = -1,
 467         LED_STATE_OFF,
 468         LED_STATE_ON,
 469 };
 470
 471 static inline int calc_blink_rate(void)
 472 {
 473         if (!tx6_temp_check_enabled)
 474                 return CONFIG_SYS_HZ;
 475
 476         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
 477                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
 478                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
 479 }
 480
 481 void show_activity(int arg)
 482 {
 483         static int led_state = LED_STATE_INIT;
 484         static int blink_rate;
 485         static ulong last;
 486
 487         if (led_state == LED_STATE_INIT) {
 488                 last = get_timer(0);
 489                 gpio_set_value(TX6_LED_GPIO, 1);
 490                 led_state = LED_STATE_ON;
 491                 blink_rate = calc_blink_rate();
 492         } else {
 493                 if (get_timer(last) > blink_rate) {
 494                         blink_rate = calc_blink_rate();
 495                         last = get_timer_masked();
 496                         if (led_state == LED_STATE_ON) {
 497                                 gpio_set_value(TX6_LED_GPIO, 0);
 498                         } else {
 499                                 gpio_set_value(TX6_LED_GPIO, 1);
 500                         }
 501                         led_state = 1 - led_state;
 502                 }
 503         }
 504 }
 505
 506 static const iomux_v3_cfg_t stk5_pads[] = {
 507         /* SW controlled LED on STK5 baseboard */
 508         MX6_PAD_EIM_A18__GPIO_2_20,
 509
 510         /* I2C bus on DIMM pins 40/41 */
 511         MX6_PAD_GPIO_6__I2C3_SDA,
 512         MX6_PAD_GPIO_3__I2C3_SCL,
 513
 514         /* TSC200x PEN IRQ */
 515         MX6_PAD_EIM_D26__GPIO_3_26,
 516
 517         /* EDT-FT5x06 Polytouch panel */
 518         MX6_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */
 519         MX6_PAD_EIM_A16__GPIO_2_22, /* RESET */
 520         MX6_PAD_EIM_A17__GPIO_2_21, /* WAKE */
 521
 522         /* USBH1 */
 523         MX6_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */
 524         MX6_PAD_EIM_D30__GPIO_3_30, /* OC */
 525         /* USBOTG */
 526         MX6_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */
 527         MX6_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */
 528         MX6_PAD_GPIO_8__GPIO_1_8, /* OC */
 529 };
 530
 531 static const struct gpio stk5_gpios[] = {
 532         { TX6_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 533
 534         { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", },
 535         { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
 536         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 537         { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
 538         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 539 };
 540
 541 #ifdef CONFIG_LCD
 542 static u16 tx6_cmap[256];
 543 vidinfo_t panel_info = {
 544         /* set to max. size supported by SoC */
 545         .vl_col = 1920,
 546         .vl_row = 1080,
 547
 548         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 549         .cmap = tx6_cmap,
 550 };
 551
 552 static struct fb_videomode tx6_fb_modes[] = {
 553 #ifndef CONFIG_SYS_LVDS_IF
 554         {
 555                 /* Standard VGA timing */
 556                 .name           = "VGA",
 557                 .refresh        = 60,
 558                 .xres           = 640,
 559                 .yres           = 480,
 560                 .pixclock       = KHZ2PICOS(25175),
 561                 .left_margin    = 48,
 562                 .hsync_len      = 96,
 563                 .right_margin   = 16,
 564                 .upper_margin   = 31,
 565                 .vsync_len      = 2,
 566                 .lower_margin   = 12,
 567                 .sync           = FB_SYNC_CLK_LAT_FALL,
 568         },
 569         {
 570                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 571                  * DE high active, 115.2 mm x 86.4 mm display area
 572                  * VGA compatible timing
 573                  */
 574                 .name           = "ETV570",
 575                 .refresh        = 60,
 576                 .xres           = 640,
 577                 .yres           = 480,
 578                 .pixclock       = KHZ2PICOS(25175),
 579                 .left_margin    = 114,
 580                 .hsync_len      = 30,
 581                 .right_margin   = 16,
 582                 .upper_margin   = 32,
 583                 .vsync_len      = 3,
 584                 .lower_margin   = 10,
 585                 .sync           = FB_SYNC_CLK_LAT_FALL,
 586         },
 587         {
 588                 /* Emerging ET0350G0DH6 320 x 240 display.
 589                  * 70.08 mm x 52.56 mm display area.
 590                  */
 591                 .name           = "ET0350",
 592                 .refresh        = 60,
 593                 .xres           = 320,
 594                 .yres           = 240,
 595                 .pixclock       = KHZ2PICOS(6500),
 596                 .left_margin    = 68 - 34,
 597                 .hsync_len      = 34,
 598                 .right_margin   = 20,
 599                 .upper_margin   = 18 - 3,
 600                 .vsync_len      = 3,
 601                 .lower_margin   = 4,
 602                 .sync           = FB_SYNC_CLK_LAT_FALL,
 603         },
 604         {
 605                 /* Emerging ET0430G0DH6 480 x 272 display.
 606                  * 95.04 mm x 53.856 mm display area.
 607                  */
 608                 .name           = "ET0430",
 609                 .refresh        = 60,
 610                 .xres           = 480,
 611                 .yres           = 272,
 612                 .pixclock       = KHZ2PICOS(9000),
 613                 .left_margin    = 2,
 614                 .hsync_len      = 41,
 615                 .right_margin   = 2,
 616                 .upper_margin   = 2,
 617                 .vsync_len      = 10,
 618                 .lower_margin   = 2,
 619                 .sync           = FB_SYNC_CLK_LAT_FALL,
 620         },
 621         {
 622                 /* Emerging ET0500G0DH6 800 x 480 display.
 623                  * 109.6 mm x 66.4 mm display area.
 624                  */
 625                 .name           = "ET0500",
 626                 .refresh        = 60,
 627                 .xres           = 800,
 628                 .yres           = 480,
 629                 .pixclock       = KHZ2PICOS(33260),
 630                 .left_margin    = 216 - 128,
 631                 .hsync_len      = 128,
 632                 .right_margin   = 1056 - 800 - 216,
 633                 .upper_margin   = 35 - 2,
 634                 .vsync_len      = 2,
 635                 .lower_margin   = 525 - 480 - 35,
 636                 .sync           = FB_SYNC_CLK_LAT_FALL,
 637         },
 638         {
 639                 /* Emerging ETQ570G0DH6 320 x 240 display.
 640                  * 115.2 mm x 86.4 mm display area.
 641                  */
 642                 .name           = "ETQ570",
 643                 .refresh        = 60,
 644                 .xres           = 320,
 645                 .yres           = 240,
 646                 .pixclock       = KHZ2PICOS(6400),
 647                 .left_margin    = 38,
 648                 .hsync_len      = 30,
 649                 .right_margin   = 30,
 650                 .upper_margin   = 16, /* 15 according to datasheet */
 651                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 652                 .lower_margin   = 4, /* 4.5 according to datasheet */
 653                 .sync           = FB_SYNC_CLK_LAT_FALL,
 654         },
 655         {
 656                 /* Emerging ET0700G0DH6 800 x 480 display.
 657                  * 152.4 mm x 91.44 mm display area.
 658                  */
 659                 .name           = "ET0700",
 660                 .refresh        = 60,
 661                 .xres           = 800,
 662                 .yres           = 480,
 663                 .pixclock       = KHZ2PICOS(33260),
 664                 .left_margin    = 216 - 128,
 665                 .hsync_len      = 128,
 666                 .right_margin   = 1056 - 800 - 216,
 667                 .upper_margin   = 35 - 2,
 668                 .vsync_len      = 2,
 669                 .lower_margin   = 525 - 480 - 35,
 670                 .sync           = FB_SYNC_CLK_LAT_FALL,
 671         },
 672         {
 673                 /* Emerging ET070001DM6 800 x 480 display.
 674                  * 152.4 mm x 91.44 mm display area.
 675                  */
 676                 .name           = "ET070001DM6",
 677                 .refresh        = 60,
 678                 .xres           = 800,
 679                 .yres           = 480,
 680                 .pixclock       = KHZ2PICOS(33260),
 681                 .left_margin    = 216 - 128,
 682                 .hsync_len      = 128,
 683                 .right_margin   = 1056 - 800 - 216,
 684                 .upper_margin   = 35 - 2,
 685                 .vsync_len      = 2,
 686                 .lower_margin   = 525 - 480 - 35,
 687                 .sync           = 0,
 688         },
 689 #else
 690         {
 691                 /* HannStar HSD100PXN1
 692                  * 202.7m mm x 152.06 mm display area.
 693                  */
 694                 .name           = "HSD100PXN1",
 695                 .refresh        = 60,
 696                 .xres           = 1024,
 697                 .yres           = 768,
 698                 .pixclock       = KHZ2PICOS(65000),
 699                 .left_margin    = 0,
 700                 .hsync_len      = 0,
 701                 .right_margin   = 320,
 702                 .upper_margin   = 0,
 703                 .vsync_len      = 0,
 704                 .lower_margin   = 38,
 705                 .sync           = FB_SYNC_CLK_LAT_FALL,
 706         },
 707 #endif
 708         {
 709                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 710                 .refresh        = 60,
 711                 .left_margin    = 48,
 712                 .hsync_len      = 96,
 713                 .right_margin   = 16,
 714                 .upper_margin   = 31,
 715                 .vsync_len      = 2,
 716                 .lower_margin   = 12,
 717                 .sync           = FB_SYNC_CLK_LAT_FALL,
 718         },
 719 };
 720
 721 static int lcd_enabled = 1;
 722 static int lcd_bl_polarity;
 723
 724 static int lcd_backlight_polarity(void)
 725 {
 726         return lcd_bl_polarity;
 727 }
 728
 729 void lcd_enable(void)
 730 {
 731         /* HACK ALERT:
 732          * global variable from common/lcd.c
 733          * Set to 0 here to prevent messages from going to LCD
 734          * rather than serial console
 735          */
 736         lcd_is_enabled = 0;
 737
 738         karo_load_splashimage(1);
 739
 740         if (lcd_enabled) {
 741                 debug("Switching LCD on\n");
 742                 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
 743                 udelay(100);
 744                 gpio_set_value(TX6_LCD_RST_GPIO, 1);
 745                 udelay(300000);
 746                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
 747                         lcd_backlight_polarity());
 748         }
 749 }
 750
 751 void lcd_disable(void)
 752 {
 753         if (lcd_enabled) {
 754                 printf("Disabling LCD\n");
 755                 ipuv3_fb_shutdown();
 756         }
 757 }
 758
 759 void lcd_panel_disable(void)
 760 {
 761         if (lcd_enabled) {
 762                 debug("Switching LCD off\n");
 763                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
 764                         !lcd_backlight_polarity());
 765                 gpio_set_value(TX6_LCD_RST_GPIO, 0);
 766                 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
 767         }
 768 }
 769
 770 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 771         /* LCD RESET */
 772         MX6_PAD_EIM_D29__GPIO_3_29,
 773         /* LCD POWER_ENABLE */
 774         MX6_PAD_EIM_EB3__GPIO_2_31,
 775         /* LCD Backlight (PWM) */
 776         MX6_PAD_GPIO_1__GPIO_1_1,
 777
 778 #ifndef CONFIG_SYS_LVDS_IF
 779         /* Display */
 780         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
 781         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
 782         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
 783         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
 784         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
 785         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
 786         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
 787         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
 788         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
 789         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
 790         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
 791         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
 792         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
 793         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
 794         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
 795         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
 796         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
 797         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
 798         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
 799         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
 800         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
 801         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
 802         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
 803         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
 804         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */
 805         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */
 806         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
 807         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
 808 #endif
 809 };
 810
 811 static const struct gpio stk5_lcd_gpios[] = {
 812         { TX6_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
 813         { TX6_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
 814         { TX6_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 815 };
 816
 817 void lcd_ctrl_init(void *lcdbase)
 818 {
 819         int color_depth = 24;
 820         const char *video_mode = karo_get_vmode(getenv("video_mode"));
 821         const char *vm;
 822         unsigned long val;
 823         int refresh = 60;
 824         struct fb_videomode *p = &tx6_fb_modes[0];
 825         struct fb_videomode fb_mode;
 826         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 827         int pix_fmt;
 828         int lcd_bus_width;
 829         unsigned long di_clk_rate = 65000000;
 830
 831         if (!lcd_enabled) {
 832                 debug("LCD disabled\n");
 833                 return;
 834         }
 835
 836         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
 837                 debug("Disabling LCD\n");
 838                 lcd_enabled = 0;
 839                 setenv("splashimage", NULL);
 840                 return;
 841         }
 842
 843         karo_fdt_move_fdt();
 844         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
 845
 846         if (video_mode == NULL) {
 847                 debug("Disabling LCD\n");
 848                 lcd_enabled = 0;
 849                 return;
 850         }
 851         vm = video_mode;
 852         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
 853                 p = &fb_mode;
 854                 debug("Using video mode from FDT\n");
 855                 vm += strlen(vm);
 856                 if (fb_mode.xres > panel_info.vl_col ||
 857                         fb_mode.yres > panel_info.vl_row) {
 858                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
 859                                 fb_mode.xres, fb_mode.yres,
 860                                 panel_info.vl_col, panel_info.vl_row);
 861                         lcd_enabled = 0;
 862                         return;
 863                 }
 864         }
 865         if (p->name != NULL)
 866                 debug("Trying compiled-in video modes\n");
 867         while (p->name != NULL) {
 868                 if (strcmp(p->name, vm) == 0) {
 869                         debug("Using video mode: '%s'\n", p->name);
 870                         vm += strlen(vm);
 871                         break;
 872                 }
 873                 p++;
 874         }
 875         if (*vm != '\0')
 876                 debug("Trying to decode video_mode: '%s'\n", vm);
 877         while (*vm != '\0') {
 878                 if (*vm >= '0' && *vm <= '9') {
 879                         char *end;
 880
 881                         val = simple_strtoul(vm, &end, 0);
 882                         if (end > vm) {
 883                                 if (!xres_set) {
 884                                         if (val > panel_info.vl_col)
 885                                                 val = panel_info.vl_col;
 886                                         p->xres = val;
 887                                         panel_info.vl_col = val;
 888                                         xres_set = 1;
 889                                 } else if (!yres_set) {
 890                                         if (val > panel_info.vl_row)
 891                                                 val = panel_info.vl_row;
 892                                         p->yres = val;
 893                                         panel_info.vl_row = val;
 894                                         yres_set = 1;
 895                                 } else if (!bpp_set) {
 896                                         switch (val) {
 897                                         case 32:
 898                                         case 24:
 899                                                 if (is_lvds())
 900                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
 901                                                 /* fallthru */
 902                                         case 16:
 903                                         case 8:
 904                                                 color_depth = val;
 905                                                 break;
 906
 907                                         case 18:
 908                                                 if (is_lvds()) {
 909                                                         color_depth = val;
 910                                                         break;
 911                                                 }
 912                                                 /* fallthru */
 913                                         default:
 914                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
 915                                                         end - vm, vm, color_depth);
 916                                         }
 917                                         bpp_set = 1;
 918                                 } else if (!refresh_set) {
 919                                         refresh = val;
 920                                         refresh_set = 1;
 921                                 }
 922                         }
 923                         vm = end;
 924                 }
 925                 switch (*vm) {
 926                 case '@':
 927                         bpp_set = 1;
 928                         /* fallthru */
 929                 case '-':
 930                         yres_set = 1;
 931                         /* fallthru */
 932                 case 'x':
 933                         xres_set = 1;
 934                         /* fallthru */
 935                 case 'M':
 936                 case 'R':
 937                         vm++;
 938                         break;
 939
 940                 default:
 941                         if (*vm != '\0')
 942                                 vm++;
 943                 }
 944         }
 945         if (p->xres == 0 || p->yres == 0) {
 946                 printf("Invalid video mode: %s\n", getenv("video_mode"));
 947                 lcd_enabled = 0;
 948                 printf("Supported video modes are:");
 949                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
 950                         printf(" %s", p->name);
 951                 }
 952                 printf("\n");
 953                 return;
 954         }
 955         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
 956                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
 957                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
 958                 lcd_enabled = 0;
 959                 return;
 960         }
 961         panel_info.vl_col = p->xres;
 962         panel_info.vl_row = p->yres;
 963
 964         switch (color_depth) {
 965         case 8:
 966                 panel_info.vl_bpix = LCD_COLOR8;
 967                 break;
 968         case 16:
 969                 panel_info.vl_bpix = LCD_COLOR16;
 970                 break;
 971         default:
 972                 panel_info.vl_bpix = LCD_COLOR24;
 973         }
 974
 975         p->pixclock = KHZ2PICOS(refresh *
 976                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
 977                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
 978                                 1000);
 979         debug("Pixel clock set to %lu.%03lu MHz\n",
 980                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
 981
 982         if (p != &fb_mode) {
 983                 int ret;
 984
 985                 debug("Creating new display-timing node from '%s'\n",
 986                         video_mode);
 987                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
 988                 if (ret)
 989                         printf("Failed to create new display-timing node from '%s': %d\n",
 990                                 video_mode, ret);
 991         }
 992
 993         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
 994         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
 995                                         ARRAY_SIZE(stk5_lcd_pads));
 996
 997         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
 998         switch (lcd_bus_width) {
 999         case 24:
1000                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1001                 break;
1002
1003         case 18:
1004                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1005                 break;
1006
1007         case 16:
1008                 if (!is_lvds()) {
1009                         pix_fmt = IPU_PIX_FMT_RGB565;
1010                         break;
1011                 }
1012                 /* fallthru */
1013         default:
1014                 lcd_enabled = 0;
1015                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1016                         lcd_bus_width);
1017                 return;
1018         }
1019         if (is_lvds()) {
1020                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1021                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1022                 uint32_t gpr2;
1023
1024                 if (lvds_chan_mask == 0) {
1025                         printf("No LVDS channel active\n");
1026                         lcd_enabled = 0;
1027                         return;
1028                 }
1029
1030                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1031                 if (lcd_bus_width == 24)
1032                         gpr2 |= (1 << 5) | (1 << 7);
1033                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1034                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1035                 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1036                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1037         }
1038         if (karo_load_splashimage(0) == 0) {
1039                 int ret;
1040
1041                 debug("Initializing LCD controller\n");
1042                 ret = ipuv3_fb_init(p, 0, pix_fmt, DI_PCLK_PLL3, di_clk_rate, -1);
1043                 if (ret) {
1044                         printf("Failed to initialize FB driver: %d\n", ret);
1045                         lcd_enabled = 0;
1046                 }
1047         } else {
1048                 debug("Skipping initialization of LCD controller\n");
1049         }
1050 }
1051 #else
1052 #define lcd_enabled 0
1053 #endif /* CONFIG_LCD */
1054
1055 static void stk5_board_init(void)
1056 {
1057         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1058         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1059 }
1060
1061 static void stk5v3_board_init(void)
1062 {
1063         stk5_board_init();
1064 }
1065
1066 static void stk5v5_board_init(void)
1067 {
1068         stk5_board_init();
1069
1070         gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
1071                         "Flexcan Transceiver");
1072         imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO_4_21);
1073 }
1074
1075 static void tx6qdl_set_cpu_clock(void)
1076 {
1077         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1078
1079         if (had_ctrlc() || (wrsr & WRSR_TOUT))
1080                 return;
1081
1082         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1083                 return;
1084
1085         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1086                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1087                 printf("CPU clock set to %lu.%03lu MHz\n",
1088                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1089         } else {
1090                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1091         }
1092 }
1093
1094 static void tx6_init_mac(void)
1095 {
1096         u8 mac[ETH_ALEN];
1097
1098         imx_get_mac_from_fuse(-1, mac);
1099         if (!is_valid_ether_addr(mac)) {
1100                 printf("No valid MAC address programmed\n");
1101                 return;
1102         }
1103
1104         printf("MAC addr from fuse: %pM\n", mac);
1105         eth_setenv_enetaddr("ethaddr", mac);
1106 }
1107
1108 int board_late_init(void)
1109 {
1110         int ret = 0;
1111         const char *baseboard;
1112
1113         if (tx6_temp_check_enabled)
1114                 check_cpu_temperature(1);
1115
1116         tx6qdl_set_cpu_clock();
1117         if (!had_ctrlc())
1118                 karo_fdt_move_fdt();
1119
1120         baseboard = getenv("baseboard");
1121         if (!baseboard)
1122                 goto exit;
1123
1124         printf("Baseboard: %s\n", baseboard);
1125
1126         if (strncmp(baseboard, "stk5", 4) == 0) {
1127                 if ((strlen(baseboard) == 4) ||
1128                         strcmp(baseboard, "stk5-v3") == 0) {
1129                         stk5v3_board_init();
1130                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1131                         const char *otg_mode = getenv("otg_mode");
1132
1133                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1134                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1135                                         otg_mode, baseboard);
1136                                 setenv("otg_mode", "none");
1137                         }
1138                         stk5v5_board_init();
1139                 } else {
1140                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1141                                 baseboard + 4);
1142                 }
1143         } else {
1144                 printf("WARNING: Unsupported baseboard: '%s'\n",
1145                         baseboard);
1146                 ret = -EINVAL;
1147         }
1148
1149 exit:
1150         tx6_init_mac();
1151
1152         gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1153         clear_ctrlc();
1154         return ret;
1155 }
1156
1157 #ifdef CONFIG_NO_NAND
1158 #ifdef CONFIG_MMC_BOOT_SIZE
1159 #define TX6_FLASH_SZ    (CONFIG_MMC_BOOT_SIZE / 1024 - 1 + 2)
1160 #else
1161 #define TX6_FLASH_SZ    3
1162 #endif
1163 #else /* CONFIG_NO_NAND */
1164 #define TX6_FLASH_SZ    (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
1165 #endif /* CONFIG_NO_NAND */
1166
1167 #ifdef CONFIG_SYS_SDRAM_BUS_WIDTH
1168 #define TX6_DDR_SZ      (ffs(CONFIG_SYS_SDRAM_BUS_WIDTH / 16) - 1)
1169 #else
1170 #define TX6_DDR_SZ      2
1171 #endif
1172
1173 #if CONFIG_TX6_REV >= 0x3
1174 static char tx6_mem_table[] = {
1175         '4', /* 256MiB SDRAM; 128MiB NAND */
1176         '1', /* 512MiB SDRAM; 128MiB NAND */
1177         '0', /* 1GiB SDRAM; 128MiB NAND */
1178         '?', /* 256MiB SDRAM; 256MiB NAND */
1179         '?', /* 512MiB SDRAM; 256MiB NAND */
1180         '2', /* 1GiB SDRAM; 256MiB NAND */
1181         '?', /* 256MiB SDRAM; 4GiB eMMC */
1182         '5', /* 512MiB SDRAM; 4GiB eMMC */
1183         '3', /* 1GiB SDRAM; 4GiB eMMC */
1184         '?', /* 256MiB SDRAM; 8GiB eMMC */
1185         '?', /* 512MiB SDRAM; 8GiB eMMC */
1186         '?', /* 1GiB SDRAM; 8GiB eMMC */
1187 };
1188
1189 static inline char tx6_mem_suffix(void)
1190 {
1191         size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
1192
1193         debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
1194                 TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
1195
1196         if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
1197                 return '?';
1198
1199         return tx6_mem_table[mem_idx];
1200 };
1201 #else /* CONFIG_TX6_REV >= 0x3 */
1202 static inline char tx6_mem_suffix(void)
1203 {
1204 #ifdef CONFIG_SYS_SDRAM_BUS_WIDTH
1205         if (CONFIG_SYS_SDRAM_BUS_WIDTH == 32)
1206                 return '1';
1207 #endif
1208 #ifdef CONFIG_SYS_NAND_BLOCKS
1209         if (CONFIG_SYS_NAND_BLOCKS == 2048)
1210                 return '2';
1211 #endif
1212         return '0';
1213 }
1214 #endif /* CONFIG_TX6_REV >= 0x3 */
1215
1216 int checkboard(void)
1217 {
1218         u32 cpurev = get_cpu_rev();
1219         int cpu_variant = (cpurev >> 12) & 0xff;
1220
1221         tx6qdl_print_cpuinfo();
1222
1223         printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
1224                 tx6_mod_suffix,
1225                 cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
1226                 is_lvds(), CONFIG_TX6_REV,
1227                 tx6_mem_suffix());
1228
1229         return 0;
1230 }
1231
1232 #ifdef CONFIG_SERIAL_TAG
1233 void get_board_serial(struct tag_serialnr *serialnr)
1234 {
1235         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1236         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1237
1238         serialnr->low = readl(&fuse->cfg0);
1239         serialnr->high = readl(&fuse->cfg1);
1240 }
1241 #endif
1242
1243 #if defined(CONFIG_OF_BOARD_SETUP)
1244 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1245 #include <jffs2/jffs2.h>
1246 #include <mtd_node.h>
1247 static struct node_info nodes[] = {
1248         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1249 };
1250 #else
1251 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1252 #endif
1253
1254 static const char *tx6_touchpanels[] = {
1255         "ti,tsc2007",
1256         "edt,edt-ft5x06",
1257         "eeti,egalax_ts",
1258 };
1259
1260 void ft_board_setup(void *blob, bd_t *bd)
1261 {
1262         const char *baseboard = getenv("baseboard");
1263         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1264         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1265         int ret;
1266
1267         ret = fdt_increase_size(blob, 4096);
1268         if (ret)
1269                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1270
1271         if (stk5_v5)
1272                 karo_fdt_enable_node(blob, "stk5led", 0);
1273
1274         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1275         fdt_fixup_ethernet(blob);
1276
1277         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1278                                 ARRAY_SIZE(tx6_touchpanels));
1279         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1280         karo_fdt_fixup_flexcan(blob, stk5_v5);
1281
1282         karo_fdt_update_fb_mode(blob, video_mode);
1283 }
1284 #endif /* CONFIG_OF_BOARD_SETUP */