karo: tx6: changed module suffix from -.xx. to -.x1. for distinction of future eMMC...
[karo-tx-uboot.git] / board / karo / tx6 / tx6qdl.c
1 /*
2  * Copyright (C) 2012,2013 Lothar WaƟmann <LW@KARO-electronics.de>
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License
9  * version 2 as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17
18 #include <common.h>
19 #include <errno.h>
20 #include <libfdt.h>
21 #include <fdt_support.h>
22 #include <lcd.h>
23 #include <netdev.h>
24 #include <mmc.h>
25 #include <fsl_esdhc.h>
26 #include <video_fb.h>
27 #include <ipu.h>
28 #include <mxcfb.h>
29 #include <i2c.h>
30 #include <linux/fb.h>
31 #include <asm/io.h>
32 #include <asm/gpio.h>
33 #include <asm/arch/mx6-pins.h>
34 #include <asm/arch/clock.h>
35 #include <asm/arch/imx-regs.h>
36 #include <asm/arch/crm_regs.h>
37 #include <asm/arch/sys_proto.h>
38
39 #include "../common/karo.h"
40
41 #define TX6_FEC_RST_GPIO                IMX_GPIO_NR(7, 6)
42 #define TX6_FEC_PWR_GPIO                IMX_GPIO_NR(3, 20)
43 #define TX6_FEC_INT_GPIO                IMX_GPIO_NR(2, 4)
44 #define TX6_LED_GPIO                    IMX_GPIO_NR(2, 20)
45
46 #define TX6_LCD_PWR_GPIO                IMX_GPIO_NR(2, 31)
47 #define TX6_LCD_RST_GPIO                IMX_GPIO_NR(3, 29)
48 #define TX6_LCD_BACKLIGHT_GPIO          IMX_GPIO_NR(1, 1)
49
50 #define TX6_RESET_OUT_GPIO              IMX_GPIO_NR(7, 12)
51
52 #define TEMPERATURE_MIN                 -40
53 #define TEMPERATURE_HOT                 80
54 #define TEMPERATURE_MAX                 125
55
56 DECLARE_GLOBAL_DATA_PTR;
57
58 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
59
60 static const iomux_v3_cfg_t tx6qdl_pads[] = {
61         /* NAND flash pads */
62         MX6_PAD_NANDF_CLE__RAWNAND_CLE,
63         MX6_PAD_NANDF_ALE__RAWNAND_ALE,
64         MX6_PAD_NANDF_WP_B__RAWNAND_RESETN,
65         MX6_PAD_NANDF_RB0__RAWNAND_READY0,
66         MX6_PAD_NANDF_CS0__RAWNAND_CE0N,
67         MX6_PAD_SD4_CMD__RAWNAND_RDN,
68         MX6_PAD_SD4_CLK__RAWNAND_WRN,
69         MX6_PAD_NANDF_D0__RAWNAND_D0,
70         MX6_PAD_NANDF_D1__RAWNAND_D1,
71         MX6_PAD_NANDF_D2__RAWNAND_D2,
72         MX6_PAD_NANDF_D3__RAWNAND_D3,
73         MX6_PAD_NANDF_D4__RAWNAND_D4,
74         MX6_PAD_NANDF_D5__RAWNAND_D5,
75         MX6_PAD_NANDF_D6__RAWNAND_D6,
76         MX6_PAD_NANDF_D7__RAWNAND_D7,
77
78         /* RESET_OUT */
79         MX6_PAD_GPIO_17__GPIO_7_12,
80
81         /* UART pads */
82 #if CONFIG_MXC_UART_BASE == UART1_BASE
83         MX6_PAD_SD3_DAT7__UART1_TXD,
84         MX6_PAD_SD3_DAT6__UART1_RXD,
85         MX6_PAD_SD3_DAT1__UART1_RTS,
86         MX6_PAD_SD3_DAT0__UART1_CTS,
87 #endif
88 #if CONFIG_MXC_UART_BASE == UART2_BASE
89         MX6_PAD_SD4_DAT4__UART2_RXD,
90         MX6_PAD_SD4_DAT7__UART2_TXD,
91         MX6_PAD_SD4_DAT5__UART2_RTS,
92         MX6_PAD_SD4_DAT6__UART2_CTS,
93 #endif
94 #if CONFIG_MXC_UART_BASE == UART3_BASE
95         MX6_PAD_EIM_D24__UART3_TXD,
96         MX6_PAD_EIM_D25__UART3_RXD,
97         MX6_PAD_SD3_RST__UART3_RTS,
98         MX6_PAD_SD3_DAT3__UART3_CTS,
99 #endif
100         /* internal I2C */
101         MX6_PAD_EIM_D28__I2C1_SDA,
102         MX6_PAD_EIM_D21__I2C1_SCL,
103
104         /* FEC PHY GPIO functions */
105         MX6_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */
106         MX6_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */
107         MX6_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */
108 };
109
110 static const iomux_v3_cfg_t tx6qdl_fec_pads[] = {
111         /* FEC functions */
112         MX6_PAD_ENET_MDC__ENET_MDC,
113         MX6_PAD_ENET_MDIO__ENET_MDIO,
114         MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
115         MX6_PAD_ENET_RX_ER__ENET_RX_ER,
116         MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
117         MX6_PAD_ENET_RXD1__ENET_RDATA_1,
118         MX6_PAD_ENET_RXD0__ENET_RDATA_0,
119         MX6_PAD_ENET_TX_EN__ENET_TX_EN,
120         MX6_PAD_ENET_TXD1__ENET_TDATA_1,
121         MX6_PAD_ENET_TXD0__ENET_TDATA_0,
122 };
123
124 static const struct gpio tx6qdl_gpios[] = {
125         { TX6_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
126         { TX6_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
127         { TX6_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
128         { TX6_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
129 };
130
131 /*
132  * Functions
133  */
134 /* placed in section '.data' to prevent overwriting relocation info
135  * overlayed with bss
136  */
137 static u32 wrsr __attribute__((section(".data")));
138
139 #define WRSR_POR                        (1 << 4)
140 #define WRSR_TOUT                       (1 << 1)
141 #define WRSR_SFTW                       (1 << 0)
142
143 static void print_reset_cause(void)
144 {
145         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
146         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
147         u32 srsr;
148         char *dlm = "";
149
150         printf("Reset cause: ");
151
152         srsr = readl(&src_regs->srsr);
153         wrsr = readw(wdt_base + 4);
154
155         if (wrsr & WRSR_POR) {
156                 printf("%sPOR", dlm);
157                 dlm = " | ";
158         }
159         if (srsr & 0x00004) {
160                 printf("%sCSU", dlm);
161                 dlm = " | ";
162         }
163         if (srsr & 0x00008) {
164                 printf("%sIPP USER", dlm);
165                 dlm = " | ";
166         }
167         if (srsr & 0x00010) {
168                 if (wrsr & WRSR_SFTW) {
169                         printf("%sSOFT", dlm);
170                         dlm = " | ";
171                 }
172                 if (wrsr & WRSR_TOUT) {
173                         printf("%sWDOG", dlm);
174                         dlm = " | ";
175                 }
176         }
177         if (srsr & 0x00020) {
178                 printf("%sJTAG HIGH-Z", dlm);
179                 dlm = " | ";
180         }
181         if (srsr & 0x00040) {
182                 printf("%sJTAG SW", dlm);
183                 dlm = " | ";
184         }
185         if (srsr & 0x10000) {
186                 printf("%sWARM BOOT", dlm);
187                 dlm = " | ";
188         }
189         if (dlm[0] == '\0')
190                 printf("unknown");
191
192         printf("\n");
193 }
194
195 int read_cpu_temperature(void);
196 int check_cpu_temperature(int boot);
197
198 static void tx6qdl_print_cpuinfo(void)
199 {
200         u32 cpurev = get_cpu_rev();
201         char *cpu_str = "?";
202
203         switch ((cpurev >> 12) & 0xff) {
204         case MXC_CPU_MX6SL:
205                 cpu_str = "SL";
206                 break;
207         case MXC_CPU_MX6DL:
208                 cpu_str = "DL";
209                 break;
210         case MXC_CPU_MX6SOLO:
211                 cpu_str = "SOLO";
212                 break;
213         case MXC_CPU_MX6Q:
214                 cpu_str = "Q";
215                 break;
216         }
217
218         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
219                 cpu_str,
220                 (cpurev & 0x000F0) >> 4,
221                 (cpurev & 0x0000F) >> 0,
222                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
223
224         print_reset_cause();
225         check_cpu_temperature(1);
226 }
227
228 #define LTC3676_BUCK1           0x01
229 #define LTC3676_BUCK2           0x02
230 #define LTC3676_BUCK3           0x03
231 #define LTC3676_BUCK4           0x04
232 #define LTC3676_DVB2A           0x0C
233 #define LTC3676_DVB2B           0x0D
234 #define LTC3676_DVB4A           0x10
235 #define LTC3676_DVB4B           0x11
236 #define LTC3676_CLIRQ           0x1f
237
238 #define VDD_SOC_mV              (1375 + 50)
239 #define VDD_CORE_mV             (1375 + 50)
240
241 #define LTC3676_BUCK_DVDT_FAST  (1 << 0)
242 #define LTC3676_BUCK_KEEP_ALIVE (1 << 1)
243 #define LTC3676_BUCK_CLK_RATE_LOW       (1 << 2)
244 #define LTC3676_BUCK_PHASE_SEL  (1 << 3)
245 #define LTC3676_BUCK_ENABLE_300 (1 << 4)
246 #define LTC3676_BUCK_PULSE_SKIP (0 << 5)
247 #define LTC3676_BUCK_BURST_MODE (1 << 5)
248 #define LTC3676_BUCK_CONTINUOUS (2 << 5)
249 #define LTC3676_BUCK_ENABLE     (1 << 7)
250
251 #define LTC3676_PGOOD_MASK      (1 << 5)
252
253 #define mV_to_regval(mV)        (((mV) * 360 / 330 - 825 + 1) / 25)
254 #define regval_to_mV(v)         (((v) * 25 + 825) * 330 / 360)
255
256 static struct pmic_regs {
257         u8 addr;
258         u8 val;
259 } ltc3676_regs[] = {
260         { LTC3676_DVB2B, mV_to_regval(900) | LTC3676_PGOOD_MASK, },
261         { LTC3676_DVB4B, mV_to_regval(900) | LTC3676_PGOOD_MASK, },
262         { LTC3676_DVB2A, mV_to_regval(VDD_SOC_mV), },
263         { LTC3676_DVB4A, mV_to_regval(VDD_CORE_mV), },
264         { LTC3676_BUCK1, LTC3676_BUCK_BURST_MODE | LTC3676_BUCK_CLK_RATE_LOW, },
265         { LTC3676_BUCK2, LTC3676_BUCK_BURST_MODE | LTC3676_BUCK_CLK_RATE_LOW, },
266         { LTC3676_BUCK3, LTC3676_BUCK_BURST_MODE | LTC3676_BUCK_CLK_RATE_LOW, },
267         { LTC3676_BUCK4, LTC3676_BUCK_BURST_MODE | LTC3676_BUCK_CLK_RATE_LOW, },
268         { LTC3676_CLIRQ, 0, }, /* clear interrupt status */
269 };
270
271 static int setup_pmic_voltages(void)
272 {
273         int ret;
274         unsigned char value;
275         int i;
276
277         ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
278         if (ret != 0) {
279                 printf("Failed to initialize I2C\n");
280                 return ret;
281         }
282
283         ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
284         if (ret) {
285                 printf("%s: i2c_read error: %d\n", __func__, ret);
286                 return ret;
287         }
288
289         for (i = 0; i < ARRAY_SIZE(ltc3676_regs); i++) {
290                 ret = i2c_write(CONFIG_SYS_I2C_SLAVE, ltc3676_regs[i].addr, 1,
291                                 &ltc3676_regs[i].val, 1);
292                 if (ret) {
293                         printf("%s: failed to write PMIC register %02x: %d\n",
294                                 __func__, ltc3676_regs[i].addr, ret);
295                         return ret;
296                 }
297         }
298         printf("VDDCORE set to %dmV\n", VDD_CORE_mV);
299         printf("VDDSOC  set to %dmV\n", VDD_SOC_mV);
300         return 0;
301 }
302
303 int board_early_init_f(void)
304 {
305         gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
306         imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
307
308         return 0;
309 }
310
311 int board_init(void)
312 {
313         int ret;
314
315         /* Address of boot parameters */
316         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
317 #ifdef CONFIG_OF_LIBFDT
318         gd->bd->bi_arch_number = -1;
319 #else
320         gd->bd->bi_arch_number = 4429;
321 #endif
322         ret = setup_pmic_voltages();
323         if (ret) {
324                 printf("Failed to setup PMIC voltages\n");
325                 hang();
326         }
327         return 0;
328 }
329
330 int dram_init(void)
331 {
332         /* dram_init must store complete ramsize in gd->ram_size */
333         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
334                                 PHYS_SDRAM_1_SIZE);
335         return 0;
336 }
337
338 void dram_init_banksize(void)
339 {
340         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
341         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
342                         PHYS_SDRAM_1_SIZE);
343 #if CONFIG_NR_DRAM_BANKS > 1
344         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
345         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
346                         PHYS_SDRAM_2_SIZE);
347 #endif
348 }
349
350 #ifdef  CONFIG_CMD_MMC
351 static const iomux_v3_cfg_t mmc0_pads[] = {
352         MX6_PAD_SD1_CMD__USDHC1_CMD,
353         MX6_PAD_SD1_CLK__USDHC1_CLK,
354         MX6_PAD_SD1_DAT0__USDHC1_DAT0,
355         MX6_PAD_SD1_DAT1__USDHC1_DAT1,
356         MX6_PAD_SD1_DAT2__USDHC1_DAT2,
357         MX6_PAD_SD1_DAT3__USDHC1_DAT3,
358         /* SD1 CD */
359         MX6_PAD_SD3_CMD__GPIO_7_2,
360 };
361
362 static const iomux_v3_cfg_t mmc1_pads[] = {
363         MX6_PAD_SD2_CMD__USDHC2_CMD,
364         MX6_PAD_SD2_CLK__USDHC2_CLK,
365         MX6_PAD_SD2_DAT0__USDHC2_DAT0,
366         MX6_PAD_SD2_DAT1__USDHC2_DAT1,
367         MX6_PAD_SD2_DAT2__USDHC2_DAT2,
368         MX6_PAD_SD2_DAT3__USDHC2_DAT3,
369         /* SD2 CD */
370         MX6_PAD_SD3_CLK__GPIO_7_3,
371 };
372
373 static struct tx6_esdhc_cfg {
374         const iomux_v3_cfg_t *pads;
375         int num_pads;
376         enum mxc_clock clkid;
377         struct fsl_esdhc_cfg cfg;
378         int cd_gpio;
379 } tx6qdl_esdhc_cfg[] = {
380         {
381                 .pads = mmc0_pads,
382                 .num_pads = ARRAY_SIZE(mmc0_pads),
383                 .clkid = MXC_ESDHC_CLK,
384                 .cfg = {
385                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
386                         .max_bus_width = 4,
387                 },
388                 .cd_gpio = IMX_GPIO_NR(7, 2),
389         },
390         {
391                 .pads = mmc1_pads,
392                 .num_pads = ARRAY_SIZE(mmc1_pads),
393                 .clkid = MXC_ESDHC2_CLK,
394                 .cfg = {
395                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
396                         .max_bus_width = 4,
397                 },
398                 .cd_gpio = IMX_GPIO_NR(7, 3),
399         },
400 };
401
402 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
403 {
404         void *p = cfg;
405
406         return p - offsetof(struct tx6_esdhc_cfg, cfg);
407 }
408
409 int board_mmc_getcd(struct mmc *mmc)
410 {
411         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
412
413         if (cfg->cd_gpio < 0)
414                 return cfg->cd_gpio;
415
416         debug("SD card %d is %spresent\n",
417                 cfg - tx6qdl_esdhc_cfg,
418                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
419         return !gpio_get_value(cfg->cd_gpio);
420 }
421
422 int board_mmc_init(bd_t *bis)
423 {
424         int i;
425
426         for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
427                 struct mmc *mmc;
428                 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
429                 int ret;
430
431                 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
432                         break;
433
434                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
435                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
436
437                 ret = gpio_request_one(cfg->cd_gpio,
438                                 GPIOF_INPUT, "MMC CD");
439                 if (ret) {
440                         printf("Error %d requesting GPIO%d_%d\n",
441                                 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
442                         continue;
443                 }
444
445                 debug("%s: Initializing MMC slot %d\n", __func__, i);
446                 fsl_esdhc_initialize(bis, &cfg->cfg);
447
448                 mmc = find_mmc_device(i);
449                 if (mmc == NULL)
450                         continue;
451                 if (board_mmc_getcd(mmc) > 0)
452                         mmc_init(mmc);
453         }
454         return 0;
455 }
456 #endif /* CONFIG_CMD_MMC */
457
458 #ifdef CONFIG_FEC_MXC
459
460 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
461                         PAD_CTL_SRE_FAST)
462 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
463 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
464
465 #ifndef ETH_ALEN
466 #define ETH_ALEN 6
467 #endif
468
469 int board_eth_init(bd_t *bis)
470 {
471         int ret;
472
473         /* delay at least 21ms for the PHY internal POR signal to deassert */
474         udelay(22000);
475
476         imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads, ARRAY_SIZE(tx6qdl_fec_pads));
477
478         /* Deassert RESET to the external phy */
479         gpio_set_value(TX6_FEC_RST_GPIO, 1);
480
481         ret = cpu_eth_init(bis);
482         if (ret)
483                 printf("cpu_eth_init() failed: %d\n", ret);
484
485         return ret;
486 }
487 #endif /* CONFIG_FEC_MXC */
488
489 enum {
490         LED_STATE_INIT = -1,
491         LED_STATE_OFF,
492         LED_STATE_ON,
493 };
494
495 static inline int calc_blink_rate(int tmp)
496 {
497         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
498                 (tmp - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
499                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
500 }
501
502 void show_activity(int arg)
503 {
504         static int led_state = LED_STATE_INIT;
505         static int blink_rate;
506         static ulong last;
507
508         if (led_state == LED_STATE_INIT) {
509                 last = get_timer(0);
510                 gpio_set_value(TX6_LED_GPIO, 1);
511                 led_state = LED_STATE_ON;
512                 blink_rate = calc_blink_rate(check_cpu_temperature(0));
513         } else {
514                 if (get_timer(last) > blink_rate) {
515                         blink_rate = calc_blink_rate(check_cpu_temperature(0));
516                         last = get_timer_masked();
517                         if (led_state == LED_STATE_ON) {
518                                 gpio_set_value(TX6_LED_GPIO, 0);
519                         } else {
520                                 gpio_set_value(TX6_LED_GPIO, 1);
521                         }
522                         led_state = 1 - led_state;
523                 }
524         }
525 }
526
527 static const iomux_v3_cfg_t stk5_pads[] = {
528         /* SW controlled LED on STK5 baseboard */
529         MX6_PAD_EIM_A18__GPIO_2_20,
530
531         /* LCD data pins */
532         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
533         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
534         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
535         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
536         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
537         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
538         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
539         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
540         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
541         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
542         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
543         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
544         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
545         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
546         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
547         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
548         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
549         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
550         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
551         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
552         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
553         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
554         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
555         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
556         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */
557         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */
558         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
559         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
560
561         /* I2C bus on DIMM pins 40/41 */
562         MX6_PAD_GPIO_6__I2C3_SDA,
563         MX6_PAD_GPIO_3__I2C3_SCL,
564
565         /* TSC200x PEN IRQ */
566         MX6_PAD_EIM_D26__GPIO_3_26,
567
568         /* EDT-FT5x06 Polytouch panel */
569         MX6_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */
570         MX6_PAD_EIM_A16__GPIO_2_22, /* RESET */
571         MX6_PAD_EIM_A17__GPIO_2_21, /* WAKE */
572
573         /* USBH1 */
574         MX6_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */
575         MX6_PAD_EIM_D30__GPIO_3_30, /* OC */
576         /* USBOTG */
577         MX6_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */
578         MX6_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */
579         MX6_PAD_GPIO_8__GPIO_1_8, /* OC */
580 };
581
582 static const struct gpio stk5_gpios[] = {
583         { TX6_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
584
585         { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", },
586         { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
587         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
588         { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
589         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
590 };
591
592 #ifdef CONFIG_LCD
593 vidinfo_t panel_info = {
594         /* set to max. size supported by SoC */
595         .vl_col = 1920,
596         .vl_row = 1080,
597
598         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
599 };
600
601 static struct fb_videomode tx6_fb_modes[] = {
602         {
603                 /* Standard VGA timing */
604                 .name           = "VGA",
605                 .refresh        = 60,
606                 .xres           = 640,
607                 .yres           = 480,
608                 .pixclock       = KHZ2PICOS(25175),
609                 .left_margin    = 48,
610                 .hsync_len      = 96,
611                 .right_margin   = 16,
612                 .upper_margin   = 31,
613                 .vsync_len      = 2,
614                 .lower_margin   = 12,
615                 .sync           = FB_SYNC_CLK_LAT_FALL,
616         },
617         {
618                 /* Emerging ETV570 640 x 480 display. Syncs low active,
619                  * DE high active, 115.2 mm x 86.4 mm display area
620                  * VGA compatible timing
621                  */
622                 .name           = "ETV570",
623                 .refresh        = 60,
624                 .xres           = 640,
625                 .yres           = 480,
626                 .pixclock       = KHZ2PICOS(25175),
627                 .left_margin    = 114,
628                 .hsync_len      = 30,
629                 .right_margin   = 16,
630                 .upper_margin   = 32,
631                 .vsync_len      = 3,
632                 .lower_margin   = 10,
633                 .sync           = FB_SYNC_CLK_LAT_FALL,
634         },
635         {
636                 /* Emerging ET0350G0DH6 320 x 240 display.
637                  * 70.08 mm x 52.56 mm display area.
638                  */
639                 .name           = "ET0350",
640                 .refresh        = 60,
641                 .xres           = 320,
642                 .yres           = 240,
643                 .pixclock       = KHZ2PICOS(6500),
644                 .left_margin    = 68 - 34,
645                 .hsync_len      = 34,
646                 .right_margin   = 20,
647                 .upper_margin   = 18 - 3,
648                 .vsync_len      = 3,
649                 .lower_margin   = 4,
650                 .sync           = FB_SYNC_CLK_LAT_FALL,
651         },
652         {
653                 /* Emerging ET0430G0DH6 480 x 272 display.
654                  * 95.04 mm x 53.856 mm display area.
655                  */
656                 .name           = "ET0430",
657                 .refresh        = 60,
658                 .xres           = 480,
659                 .yres           = 272,
660                 .pixclock       = KHZ2PICOS(9000),
661                 .left_margin    = 2,
662                 .hsync_len      = 41,
663                 .right_margin   = 2,
664                 .upper_margin   = 2,
665                 .vsync_len      = 10,
666                 .lower_margin   = 2,
667                 .sync           = FB_SYNC_CLK_LAT_FALL,
668         },
669         {
670                 /* Emerging ET0500G0DH6 800 x 480 display.
671                  * 109.6 mm x 66.4 mm display area.
672                  */
673                 .name           = "ET0500",
674                 .refresh        = 60,
675                 .xres           = 800,
676                 .yres           = 480,
677                 .pixclock       = KHZ2PICOS(33260),
678                 .left_margin    = 216 - 128,
679                 .hsync_len      = 128,
680                 .right_margin   = 1056 - 800 - 216,
681                 .upper_margin   = 35 - 2,
682                 .vsync_len      = 2,
683                 .lower_margin   = 525 - 480 - 35,
684                 .sync           = FB_SYNC_CLK_LAT_FALL,
685         },
686         {
687                 /* Emerging ETQ570G0DH6 320 x 240 display.
688                  * 115.2 mm x 86.4 mm display area.
689                  */
690                 .name           = "ETQ570",
691                 .refresh        = 60,
692                 .xres           = 320,
693                 .yres           = 240,
694                 .pixclock       = KHZ2PICOS(6400),
695                 .left_margin    = 38,
696                 .hsync_len      = 30,
697                 .right_margin   = 30,
698                 .upper_margin   = 16, /* 15 according to datasheet */
699                 .vsync_len      = 3, /* TVP -> 1>x>5 */
700                 .lower_margin   = 4, /* 4.5 according to datasheet */
701                 .sync           = FB_SYNC_CLK_LAT_FALL,
702         },
703         {
704                 /* Emerging ET0700G0DH6 800 x 480 display.
705                  * 152.4 mm x 91.44 mm display area.
706                  */
707                 .name           = "ET0700",
708                 .refresh        = 60,
709                 .xres           = 800,
710                 .yres           = 480,
711                 .pixclock       = KHZ2PICOS(33260),
712                 .left_margin    = 216 - 128,
713                 .hsync_len      = 128,
714                 .right_margin   = 1056 - 800 - 216,
715                 .upper_margin   = 35 - 2,
716                 .vsync_len      = 2,
717                 .lower_margin   = 525 - 480 - 35,
718                 .sync           = FB_SYNC_CLK_LAT_FALL,
719         },
720         {
721                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
722                 .refresh        = 60,
723                 .left_margin    = 48,
724                 .hsync_len      = 96,
725                 .right_margin   = 16,
726                 .upper_margin   = 31,
727                 .vsync_len      = 2,
728                 .lower_margin   = 12,
729                 .sync           = FB_SYNC_CLK_LAT_FALL,
730         },
731 };
732
733 static int lcd_enabled = 1;
734
735 void lcd_enable(void)
736 {
737         /* HACK ALERT:
738          * global variable from common/lcd.c
739          * Set to 0 here to prevent messages from going to LCD
740          * rather than serial console
741          */
742         lcd_is_enabled = 0;
743
744         karo_load_splashimage(1);
745
746         if (lcd_enabled) {
747                 debug("Switching LCD on\n");
748                 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
749                 udelay(100);
750                 gpio_set_value(TX6_LCD_RST_GPIO, 1);
751                 udelay(300000);
752                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, 0);
753         }
754 }
755
756 void lcd_disable(void)
757 {
758         if (lcd_enabled) {
759                 printf("Disabling LCD\n");
760                 ipuv3_fb_shutdown();
761         }
762 }
763
764 void lcd_panel_disable(void)
765 {
766         if (lcd_enabled) {
767                 debug("Switching LCD off\n");
768                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, 1);
769                 gpio_set_value(TX6_LCD_RST_GPIO, 0);
770                 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
771         }
772 }
773
774 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
775         /* LCD RESET */
776         MX6_PAD_EIM_D29__GPIO_3_29,
777         /* LCD POWER_ENABLE */
778         MX6_PAD_EIM_EB3__GPIO_2_31,
779         /* LCD Backlight (PWM) */
780         MX6_PAD_GPIO_1__GPIO_1_1,
781
782         /* Display */
783         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
784         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
785         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
786         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
787         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
788         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
789         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
790         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
791         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
792         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
793         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
794         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
795         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
796         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
797         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
798         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
799         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
800         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
801         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
802         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
803         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
804         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
805         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
806         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
807         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
808         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
809         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
810         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
811 };
812
813 static const struct gpio stk5_lcd_gpios[] = {
814         { TX6_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
815         { TX6_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
816         { TX6_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
817 };
818
819 void lcd_ctrl_init(void *lcdbase)
820 {
821         int color_depth = 24;
822         const char *video_mode = getenv("video_mode");
823         const char *vm;
824         unsigned long val;
825         int refresh = 60;
826         struct fb_videomode *p = &tx6_fb_modes[0];
827         struct fb_videomode fb_mode;
828         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
829         int pix_fmt = 0;
830         ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
831         unsigned long di_clk_rate = 65000000;
832
833         if (!lcd_enabled) {
834                 debug("LCD disabled\n");
835                 return;
836         }
837
838         if (tstc() || (wrsr & WRSR_TOUT)) {
839                 debug("Disabling LCD\n");
840                 lcd_enabled = 0;
841                 setenv("splashimage", NULL);
842                 return;
843         }
844
845         karo_fdt_move_fdt();
846
847         vm = karo_fdt_set_display(video_mode, "", "/soc/aips-bus/ldb");
848         if (vm == NULL) {
849                 debug("Disabling LCD\n");
850                 lcd_enabled = 0;
851                 return;
852         }
853         video_mode = vm;
854         if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
855                 p = &fb_mode;
856                 debug("Using video mode from FDT\n");
857                 vm += strlen(vm);
858                 if (fb_mode.xres > panel_info.vl_col ||
859                         fb_mode.yres > panel_info.vl_row) {
860                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
861                                 fb_mode.xres, fb_mode.yres,
862                                 panel_info.vl_col, panel_info.vl_row);
863                         lcd_enabled = 0;
864                         return;
865                 }
866         }
867         if (p->name != NULL)
868                 debug("Trying compiled-in video modes\n");
869         while (p->name != NULL) {
870                 if (strcmp(p->name, vm) == 0) {
871                         debug("Using video mode: '%s'\n", p->name);
872                         vm += strlen(vm);
873                         break;
874                 }
875                 p++;
876         }
877         if (*vm != '\0')
878                 debug("Trying to decode video_mode: '%s'\n", vm);
879         while (*vm != '\0') {
880                 if (*vm >= '0' && *vm <= '9') {
881                         char *end;
882
883                         val = simple_strtoul(vm, &end, 0);
884                         if (end > vm) {
885                                 if (!xres_set) {
886                                         if (val > panel_info.vl_col)
887                                                 val = panel_info.vl_col;
888                                         p->xres = val;
889                                         panel_info.vl_col = val;
890                                         xres_set = 1;
891                                 } else if (!yres_set) {
892                                         if (val > panel_info.vl_row)
893                                                 val = panel_info.vl_row;
894                                         p->yres = val;
895                                         panel_info.vl_row = val;
896                                         yres_set = 1;
897                                 } else if (!bpp_set) {
898                                         switch (val) {
899                                         case 32:
900                                         case 24:
901                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666)
902                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
903                                                 /* fallthru */
904                                         case 16:
905                                         case 8:
906                                                 color_depth = val;
907                                                 break;
908
909                                         case 18:
910                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666) {
911                                                         color_depth = val;
912                                                         break;
913                                                 }
914                                                 /* fallthru */
915                                         default:
916                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
917                                                         end - vm, vm, color_depth);
918                                         }
919                                         bpp_set = 1;
920                                 } else if (!refresh_set) {
921                                         refresh = val;
922                                         refresh_set = 1;
923                                 }
924                         }
925                         vm = end;
926                 }
927                 switch (*vm) {
928                 case '@':
929                         bpp_set = 1;
930                         /* fallthru */
931                 case '-':
932                         yres_set = 1;
933                         /* fallthru */
934                 case 'x':
935                         xres_set = 1;
936                         /* fallthru */
937                 case 'M':
938                 case 'R':
939                         vm++;
940                         break;
941
942                 default:
943                         if (!pix_fmt) {
944                                 char *tmp;
945
946                                 if (strncmp(vm, "LVDS", 4) == 0) {
947                                         pix_fmt = IPU_PIX_FMT_LVDS666;
948                                         di_clk_parent = DI_PCLK_LDB;
949                                 } else {
950                                         pix_fmt = IPU_PIX_FMT_RGB24;
951                                 }
952                                 tmp = strchr(vm, ':');
953                                 if (tmp)
954                                         vm = tmp;
955                         }
956                         if (*vm != '\0')
957                                 vm++;
958                 }
959         }
960         if (p->xres == 0 || p->yres == 0) {
961                 printf("Invalid video mode: %s\n", getenv("video_mode"));
962                 lcd_enabled = 0;
963                 printf("Supported video modes are:");
964                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
965                         printf(" %s", p->name);
966                 }
967                 printf("\n");
968                 return;
969         }
970         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
971                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
972                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
973                 lcd_enabled = 0;
974                 return;
975         }
976         panel_info.vl_col = p->xres;
977         panel_info.vl_row = p->yres;
978
979         switch (color_depth) {
980         case 8:
981                 panel_info.vl_bpix = LCD_COLOR8;
982                 break;
983         case 16:
984                 panel_info.vl_bpix = LCD_COLOR16;
985                 break;
986         default:
987                 panel_info.vl_bpix = LCD_COLOR24;
988         }
989
990         p->pixclock = KHZ2PICOS(refresh *
991                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
992                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
993                 / 1000);
994         debug("Pixel clock set to %lu.%03lu MHz\n",
995                 PICOS2KHZ(p->pixclock) / 1000,
996                 PICOS2KHZ(p->pixclock) % 1000);
997
998         if (p != &fb_mode) {
999                 int ret;
1000
1001                 debug("Creating new display-timing node from '%s'\n",
1002                         video_mode);
1003                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1004                 if (ret)
1005                         printf("Failed to create new display-timing node from '%s': %d\n",
1006                                 video_mode, ret);
1007         }
1008
1009         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1010         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1011                                         ARRAY_SIZE(stk5_lcd_pads));
1012
1013         debug("Initializing FB driver\n");
1014         if (!pix_fmt)
1015                 pix_fmt = IPU_PIX_FMT_RGB24;
1016         else if (pix_fmt == IPU_PIX_FMT_LVDS666) {
1017                 writel(0x01, IOMUXC_BASE_ADDR + 8);
1018         } else if (pix_fmt == IPU_PIX_FMT_LVDS888) {
1019                 writel(0x21, IOMUXC_BASE_ADDR + 8);
1020         }
1021         if (pix_fmt != IPU_PIX_FMT_RGB24) {
1022                 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1023                 /* enable LDB & DI0 clock */
1024                 writel(readl(&ccm_regs->CCGR3) | MXC_CCM_CCGR3_LDB_DI0_MASK |
1025                         MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK,
1026                         &ccm_regs->CCGR3);
1027         }
1028
1029         if (karo_load_splashimage(0) == 0) {
1030                 debug("Initializing LCD controller\n");
1031                 ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
1032         } else {
1033                 debug("Skipping initialization of LCD controller\n");
1034         }
1035 }
1036 #else
1037 #define lcd_enabled 0
1038 #endif /* CONFIG_LCD */
1039
1040 static void stk5_board_init(void)
1041 {
1042         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1043         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1044 }
1045
1046 static void stk5v3_board_init(void)
1047 {
1048         stk5_board_init();
1049 }
1050
1051 static void stk5v5_board_init(void)
1052 {
1053         stk5_board_init();
1054
1055         gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
1056                         "Flexcan Transceiver");
1057         imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO_4_21);
1058 }
1059
1060 static void tx6qdl_set_cpu_clock(void)
1061 {
1062         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1063
1064         if (tstc() || (wrsr & WRSR_TOUT))
1065                 return;
1066
1067         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1068                 return;
1069
1070         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1071                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1072                 printf("CPU clock set to %lu.%03lu MHz\n",
1073                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1074         } else {
1075                 printf("Failed to set CPU clock to %lu MHz\n", cpu_clk);
1076         }
1077 }
1078
1079 static void tx6_init_mac(void)
1080 {
1081         u8 mac[ETH_ALEN];
1082
1083         imx_get_mac_from_fuse(-1, mac);
1084         if (!is_valid_ether_addr(mac)) {
1085                 printf("No valid MAC address programmed\n");
1086                 return;
1087         }
1088
1089         eth_setenv_enetaddr("ethaddr", mac);
1090         printf("MAC addr from fuse: %pM\n", mac);
1091 }
1092
1093 int board_late_init(void)
1094 {
1095         int ret = 0;
1096         const char *baseboard;
1097
1098         tx6qdl_set_cpu_clock();
1099         karo_fdt_move_fdt();
1100
1101         baseboard = getenv("baseboard");
1102         if (!baseboard)
1103                 goto exit;
1104
1105         printf("Baseboard: %s\n", baseboard);
1106
1107         if (strncmp(baseboard, "stk5", 4) == 0) {
1108                 if ((strlen(baseboard) == 4) ||
1109                         strcmp(baseboard, "stk5-v3") == 0) {
1110                         stk5v3_board_init();
1111                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1112                         const char *otg_mode = getenv("otg_mode");
1113
1114                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1115                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1116                                         otg_mode, baseboard);
1117                                 setenv("otg_mode", "none");
1118                         }
1119                         stk5v5_board_init();
1120                 } else {
1121                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1122                                 baseboard + 4);
1123                 }
1124         } else {
1125                 printf("WARNING: Unsupported baseboard: '%s'\n",
1126                         baseboard);
1127                 ret = -EINVAL;
1128         }
1129
1130 exit:
1131         tx6_init_mac();
1132
1133         gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1134         return ret;
1135 }
1136
1137 int checkboard(void)
1138 {
1139         u32 cpurev = get_cpu_rev();
1140         int cpu_variant = (cpurev >> 12) & 0xff;
1141
1142         tx6qdl_print_cpuinfo();
1143
1144         printf("Board: Ka-Ro TX6%c-%dx1%d\n",
1145                 cpu_variant == MXC_CPU_MX6Q ? 'Q' : 'U',
1146                 cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
1147                 1 - PHYS_SDRAM_1_WIDTH / 64);
1148
1149         return 0;
1150 }
1151
1152 #ifdef CONFIG_SERIAL_TAG
1153 void get_board_serial(struct tag_serialnr *serialnr)
1154 {
1155         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1156         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1157
1158         serialnr->low = readl(&fuse->cfg0);
1159         serialnr->high = readl(&fuse->cfg1);
1160 }
1161 #endif
1162
1163 #if defined(CONFIG_OF_BOARD_SETUP)
1164 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1165 #include <jffs2/jffs2.h>
1166 #include <mtd_node.h>
1167 struct node_info nodes[] = {
1168         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1169 };
1170
1171 #else
1172 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1173 #endif
1174
1175 void ft_board_setup(void *blob, bd_t *bd)
1176 {
1177         const char *baseboard = getenv("baseboard");
1178         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1179         const char *video_mode = getenv("video_mode");
1180
1181         karo_fdt_enable_node(blob, "stk5led", !stk5_v5);
1182
1183         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1184         fdt_fixup_ethernet(blob);
1185
1186         karo_fdt_fixup_touchpanel(blob);
1187         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy");
1188         karo_fdt_fixup_flexcan(blob, stk5_v5);
1189
1190         video_mode = karo_fdt_set_display(video_mode, "", "/soc/aips-bus/ldb");
1191         karo_fdt_update_fb_mode(blob, video_mode);
1192 }
1193 #endif /* CONFIG_OF_BOARD_SETUP */