karo: tx6ul: reorder functions to better follow which ones are called with the defaul...
[karo-tx-uboot.git] / board / karo / tx6 / tx6ul.c
1 /*
2  * Copyright (C) 2015 Lothar WaƟmann <LW@KARO-electronics.de>
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  *
6  */
7 #include <common.h>
8 #include <errno.h>
9 #include <libfdt.h>
10 #include <fdt_support.h>
11 #include <lcd.h>
12 #include <netdev.h>
13 #include <mmc.h>
14 #include <fsl_esdhc.h>
15 #include <video_fb.h>
16 #include <ipu.h>
17 #include <mxcfb.h>
18 #include <i2c.h>
19 #include <linux/fb.h>
20 #include <asm/io.h>
21 #include <asm/gpio.h>
22 #include <asm/arch/mx6-pins.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/hab.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/crm_regs.h>
27 #include <asm/arch/sys_proto.h>
28
29 #include "../common/karo.h"
30 #include "pmic.h"
31
32 #define __data __attribute__((section(".data")))
33
34 #define TX6UL_FEC_RST_GPIO              IMX_GPIO_NR(5, 6)
35 #define TX6UL_FEC_PWR_GPIO              IMX_GPIO_NR(5, 7)
36 #define TX6UL_FEC_INT_GPIO              IMX_GPIO_NR(5, 5)
37 #define TX6UL_LED_GPIO                  IMX_GPIO_NR(5, 9)
38
39 #define TX6UL_LCD_PWR_GPIO              IMX_GPIO_NR(5, 4)
40 #define TX6UL_LCD_RST_GPIO              IMX_GPIO_NR(3, 4)
41 #define TX6UL_LCD_BACKLIGHT_GPIO        IMX_GPIO_NR(4, 16)
42
43 #define TX6UL_I2C1_SCL_GPIO             CONFIG_SOFT_I2C_GPIO_SCL
44 #define TX6UL_I2C1_SDA_GPIO             CONFIG_SOFT_I2C_GPIO_SDA
45
46 #define TX6UL_SD1_CD_GPIO               IMX_GPIO_NR(4, 14)
47
48 #ifdef CONFIG_MX6_TEMPERATURE_MIN
49 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
50 #else
51 #define TEMPERATURE_MIN                 (-40)
52 #endif
53 #ifdef CONFIG_MX6_TEMPERATURE_HOT
54 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
55 #else
56 #define TEMPERATURE_HOT                 80
57 #endif
58
59 DECLARE_GLOBAL_DATA_PTR;
60
61 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
62
63 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
64 #ifdef CONFIG_SECURE_BOOT
65 char __csf_data[0] __attribute__((section(".__csf_data")));
66 #endif
67
68 static const iomux_v3_cfg_t const tx6ul_pads[] = {
69         /* UART pads */
70 #if CONFIG_MXC_UART_BASE == UART1_BASE
71         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX,
72         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX,
73         MX6_PAD_UART1_RTS_B__UART1_DCE_RTS,
74         MX6_PAD_UART1_CTS_B__UART1_DCE_CTS,
75 #endif
76 #if CONFIG_MXC_UART_BASE == UART2_BASE
77         MX6_PAD_UART2_TX_DATA__UART2_DCE_TX,
78         MX6_PAD_UART2_RX_DATA__UART2_DCE_RX,
79         MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS,
80         MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS,
81 #endif
82 #if CONFIG_MXC_UART_BASE == UART5_BASE
83         MX6_PAD_GPIO1_IO04__UART5_DCE_TX,
84         MX6_PAD_GPIO1_IO05__UART5_DCE_RX,
85         MX6_PAD_GPIO1_IO08__UART5_DCE_RTS,
86         MX6_PAD_GPIO1_IO09__UART5_DCE_CTS,
87 #endif
88         /* internal I2C */
89         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
90                         MUX_PAD_CTRL(PAD_CTL_DSE_240ohm), /* I2C SCL */
91         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
92                         MUX_PAD_CTRL(PAD_CTL_DSE_240ohm | PAD_CTL_HYS |
93                         PAD_CTL_ODE), /* I2C SDA */
94
95         /* FEC PHY GPIO functions */
96         MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_CFG_SION, /* PHY POWER */
97         MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | MUX_CFG_SION, /* PHY RESET */
98         MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
99                                                         PAD_CTL_DSE_40ohm), /* PHY INT */
100 };
101
102 #define TX6_ENET_PAD_CTRL       (PAD_CTL_SPEED_HIGH |   \
103                                 PAD_CTL_DSE_48ohm |     \
104                                 PAD_CTL_PUS_100K_UP |   \
105                                 PAD_CTL_SRE_FAST)
106 #define TX6_GPIO_OUT_PAD_CTRL   (PAD_CTL_SPEED_LOW |    \
107                                 PAD_CTL_DSE_60ohm |     \
108                                 PAD_CTL_SRE_SLOW)
109 #define TX6_GPIO_IN_PAD_CTRL    (PAD_CTL_SPEED_LOW |    \
110                                 PAD_CTL_PUS_47K_UP)
111
112 static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = {
113         /* FEC functions */
114         MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_48ohm |
115                                 PAD_CTL_SPEED_MED),
116         MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
117                                 PAD_CTL_DSE_48ohm |
118                                 PAD_CTL_SPEED_MED),
119         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_CFG_SION |
120                                 MUX_PAD_CTRL(PAD_CTL_SPEED_MED |
121                                 PAD_CTL_DSE_40ohm |
122                                 PAD_CTL_SRE_FAST),
123         MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
124         MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
125         MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
126         MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
127         MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
128         MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
129         MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
130
131         MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_CFG_SION |
132                                 MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |
133                                 PAD_CTL_DSE_48ohm |
134                                 PAD_CTL_SRE_FAST),
135         MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
136         MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
137         MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
138         MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
139         MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
140         MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
141         MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
142 };
143
144 #define TX6_I2C_PAD_CTRL        (PAD_CTL_PUS_22K_UP |   \
145                                 PAD_CTL_SPEED_MED |     \
146                                 PAD_CTL_DSE_34ohm |     \
147                                 PAD_CTL_SRE_FAST)
148
149 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
150         /* internal I2C */
151         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
152                         MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
153         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
154                         MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
155 };
156
157 static const struct gpio const tx6ul_gpios[] = {
158         /* These two entries are used to forcefully reinitialize the I2C bus */
159         { TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
160         { TX6UL_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
161
162         { TX6UL_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
163         { TX6UL_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
164         { TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
165 };
166
167 #define GPIO_DR 0
168 #define GPIO_DIR 4
169 #define GPIO_PSR 8
170
171 /* run with default environment */
172 static void tx6_i2c_recover(void)
173 {
174         int i;
175         int bad = 0;
176 #define SCL_BIT         (1 << (TX6UL_I2C1_SCL_GPIO % 32))
177 #define SDA_BIT         (1 << (TX6UL_I2C1_SDA_GPIO % 32))
178 #define I2C_GPIO_BASE   (GPIO1_BASE_ADDR + TX6UL_I2C1_SCL_GPIO / 32 * 0x4000)
179
180         if ((readl(I2C_GPIO_BASE + GPIO_PSR) &
181                         (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
182                 return;
183
184         debug("Clearing I2C bus\n");
185         if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SCL_BIT)) {
186                 printf("I2C SCL stuck LOW\n");
187                 bad++;
188
189                 writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
190                         I2C_GPIO_BASE + GPIO_DR);
191                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
192                         I2C_GPIO_BASE + GPIO_DIR);
193         }
194         if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)) {
195                 printf("I2C SDA stuck LOW\n");
196                 bad++;
197
198                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) & ~SDA_BIT,
199                         I2C_GPIO_BASE + GPIO_DIR);
200                 writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
201                         I2C_GPIO_BASE + GPIO_DR);
202                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
203                         I2C_GPIO_BASE + GPIO_DIR);
204
205                 imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
206                                                 ARRAY_SIZE(tx6_i2c_gpio_pads));
207                 udelay(10);
208
209                 for (i = 0; i < 18; i++) {
210                         u32 reg = readl(I2C_GPIO_BASE + GPIO_DR) ^ SCL_BIT;
211
212                         debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
213                         writel(reg, I2C_GPIO_BASE + GPIO_DR);
214                         udelay(10);
215                         if (reg & SCL_BIT &&
216                                 readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)
217                                 break;
218                 }
219         }
220         if (bad) {
221                 u32 reg = readl(I2C_GPIO_BASE + GPIO_PSR);
222
223                 if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
224                         printf("I2C bus recovery succeeded\n");
225                 } else {
226                         printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
227                                 SCL_BIT | SDA_BIT);
228                 }
229         }
230 }
231
232 /* placed in section '.data' to prevent overwriting relocation info
233  * overlayed with bss
234  */
235 static u32 wrsr __data;
236
237 #define WRSR_POR                        (1 << 4)
238 #define WRSR_TOUT                       (1 << 1)
239 #define WRSR_SFTW                       (1 << 0)
240
241 static void print_reset_cause(void)
242 {
243         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
244         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
245         u32 srsr;
246         char *dlm = "";
247
248         printf("Reset cause: ");
249
250         srsr = readl(&src_regs->srsr);
251         wrsr = readw(wdt_base + 4);
252
253         if (wrsr & WRSR_POR) {
254                 printf("%sPOR", dlm);
255                 dlm = " | ";
256         }
257         if (srsr & 0x00004) {
258                 printf("%sCSU", dlm);
259                 dlm = " | ";
260         }
261         if (srsr & 0x00008) {
262                 printf("%sIPP USER", dlm);
263                 dlm = " | ";
264         }
265         if (srsr & 0x00010) {
266                 if (wrsr & WRSR_SFTW) {
267                         printf("%sSOFT", dlm);
268                         dlm = " | ";
269                 }
270                 if (wrsr & WRSR_TOUT) {
271                         printf("%sWDOG", dlm);
272                         dlm = " | ";
273                 }
274         }
275         if (srsr & 0x00020) {
276                 printf("%sJTAG HIGH-Z", dlm);
277                 dlm = " | ";
278         }
279         if (srsr & 0x00040) {
280                 printf("%sJTAG SW", dlm);
281                 dlm = " | ";
282         }
283         if (srsr & 0x10000) {
284                 printf("%sWARM BOOT", dlm);
285                 dlm = " | ";
286         }
287         if (dlm[0] == '\0')
288                 printf("unknown");
289
290         printf("\n");
291 }
292
293 #ifdef CONFIG_IMX6_THERMAL
294 #include <thermal.h>
295 #include <imx_thermal.h>
296 #include <fuse.h>
297
298 static void print_temperature(void)
299 {
300         struct udevice *thermal_dev;
301         int cpu_tmp, minc, maxc, ret;
302         char const *grade_str;
303         static u32 __data thermal_calib;
304
305         puts("Temperature: ");
306         switch (get_cpu_temp_grade(&minc, &maxc)) {
307         case TEMP_AUTOMOTIVE:
308                 grade_str = "Automotive";
309                 break;
310         case TEMP_INDUSTRIAL:
311                 grade_str = "Industrial";
312                 break;
313         case TEMP_EXTCOMMERCIAL:
314                 grade_str = "Extended Commercial";
315                 break;
316         default:
317                 grade_str = "Commercial";
318         }
319         printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
320         ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
321         if (ret == 0) {
322                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
323
324                 if (ret == 0)
325                         printf(" at %dC", cpu_tmp);
326                 else
327                         puts(" - failed to read sensor data");
328         } else {
329                 puts(" - no sensor device found");
330         }
331
332         if (fuse_read(1, 6, &thermal_calib) == 0) {
333                 printf(" - calibration data 0x%08x\n", thermal_calib);
334         } else {
335                 puts(" - Failed to read thermal calib fuse\n");
336         }
337 }
338 #else
339 static inline void print_temperature(void)
340 {
341 }
342 #endif
343
344 int checkboard(void)
345 {
346         u32 cpurev = get_cpu_rev();
347         char *cpu_str = "?";
348
349         switch ((cpurev >> 12) & 0xff) {
350         case MXC_CPU_MX6SL:
351                 cpu_str = "SL";
352                 break;
353         case MXC_CPU_MX6DL:
354                 cpu_str = "DL";
355                 break;
356         case MXC_CPU_MX6SOLO:
357                 cpu_str = "SOLO";
358                 break;
359         case MXC_CPU_MX6Q:
360                 cpu_str = "Q";
361                 break;
362         case MXC_CPU_MX6UL:
363                 cpu_str = "UL";
364                 break;
365         }
366
367         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
368                 cpu_str,
369                 (cpurev & 0x000F0) >> 4,
370                 (cpurev & 0x0000F) >> 0,
371                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
372
373         print_temperature();
374         print_reset_cause();
375 #ifdef CONFIG_MX6_TEMPERATURE_HOT
376         check_cpu_temperature(1);
377 #endif
378         tx6_i2c_recover();
379         return 0;
380 }
381
382 /* serial port not initialized at this point */
383 int board_early_init_f(void)
384 {
385         return 0;
386 }
387
388 #ifndef CONFIG_MX6_TEMPERATURE_HOT
389 static bool tx6_temp_check_enabled = true;
390 #else
391 #define tx6_temp_check_enabled  0
392 #endif
393
394 static inline u8 tx6ul_mem_suffix(void)
395 {
396 #ifdef CONFIG_TX6_NAND
397         return '0';
398 #else
399         return '1';
400 #endif
401 }
402
403 /* PMIC settings */
404 #define VDD_RTC_VAL             rn5t_mV_to_regval_rtc(3000)
405 #define VDD_CORE_VAL            rn5t_mV_to_regval(1300)         /* DCDC1 */
406 #define VDD_CORE_VAL_LP         rn5t_mV_to_regval(900)
407 #define VDD_DDR_VAL             rn5t_mV_to_regval(1350)         /* DCDC3 */
408 #define VDD_DDR_VAL_LP          rn5t_mV_to_regval(1350)
409 #define VDD_HIGH_VAL            rn5t_mV_to_regval(3300)         /* DCDC4 */
410 #define VDD_HIGH_VAL_LP         rn5t_mV_to_regval(3300)
411 #define VDD_CSI_VAL             rn5t_mV_to_regval2(3300)        /* LDO4 */
412 #define VDD_CSI_VAL_LP          rn5t_mV_to_regval2(3300)
413
414 static struct pmic_regs rn5t567_regs[] = {
415         { RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, },
416         { RN5T567_DC2CTL, DC2_DC2DIS, },
417         { RN5T567_DC1DAC, VDD_CORE_VAL, },
418         { RN5T567_DC3DAC, VDD_DDR_VAL, },
419         { RN5T567_DC4DAC, VDD_HIGH_VAL, },
420         { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
421         { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
422         { RN5T567_DC4DAC_SLP, VDD_HIGH_VAL_LP, },
423         { RN5T567_LDOEN1, 0x01f, ~0x1f, },
424         { RN5T567_LDOEN2, 0x10, ~0x30, },
425         { RN5T567_LDODIS, 0x00, },
426         { RN5T567_LDO4DAC, VDD_CSI_VAL, },
427         { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
428         { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
429 };
430
431 static int pmic_addr __maybe_unused = 0x33;
432
433 int board_init(void)
434 {
435         int ret;
436
437         debug("%s@%d: \n", __func__, __LINE__);
438
439         printf("Board: Ka-Ro TXUL-001%c\n",
440                 tx6ul_mem_suffix());
441
442         get_hab_status();
443
444         ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios));
445         if (ret < 0) {
446                 printf("Failed to request tx6ul_gpios: %d\n", ret);
447         }
448         imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads));
449
450         /* Address of boot parameters */
451         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
452         gd->bd->bi_arch_number = -1;
453
454         if (ctrlc() || (wrsr & WRSR_TOUT)) {
455                 if (wrsr & WRSR_TOUT)
456                         printf("WDOG RESET detected; Skipping PMIC setup\n");
457                 else
458                         printf("<CTRL-C> detected; safeboot enabled\n");
459 #ifndef CONFIG_MX6_TEMPERATURE_HOT
460                 tx6_temp_check_enabled = false;
461 #endif
462                 return 0;
463         }
464
465         ret = tx6_pmic_init(pmic_addr, rn5t567_regs, ARRAY_SIZE(rn5t567_regs));
466         if (ret) {
467                 printf("Failed to setup PMIC voltages: %d\n", ret);
468                 hang();
469         }
470         return 0;
471 }
472
473 int dram_init(void)
474 {
475         debug("%s@%d: \n", __func__, __LINE__);
476
477         /* dram_init must store complete ramsize in gd->ram_size */
478         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
479                                 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
480         return 0;
481 }
482
483 void dram_init_banksize(void)
484 {
485         debug("%s@%d: \n", __func__, __LINE__);
486
487         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
488         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
489                         PHYS_SDRAM_1_SIZE);
490 #if CONFIG_NR_DRAM_BANKS > 1
491         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
492         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
493                         PHYS_SDRAM_2_SIZE);
494 #endif
495 }
496
497 #ifdef  CONFIG_FSL_ESDHC
498 #define TX6_SD_PAD_CTRL         (PAD_CTL_PUS_47K_UP |   \
499                                 PAD_CTL_SPEED_MED |     \
500                                 PAD_CTL_DSE_40ohm |     \
501                                 PAD_CTL_SRE_FAST)
502
503 static const iomux_v3_cfg_t mmc0_pads[] = {
504         MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
505         MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
506         MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
507         MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
508         MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
509         MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
510         /* SD1 CD */
511         MX6_PAD_NAND_CE1_B__GPIO4_IO14 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
512 };
513
514 #ifdef CONFIG_TX6_EMMC
515 static const iomux_v3_cfg_t mmc1_pads[] = {
516         MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
517         MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
518         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
519         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
520         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
521         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
522         /* eMMC RESET */
523         MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
524                                                 PAD_CTL_DSE_40ohm),
525 };
526 #endif
527
528 static struct tx6_esdhc_cfg {
529         const iomux_v3_cfg_t *pads;
530         int num_pads;
531         enum mxc_clock clkid;
532         struct fsl_esdhc_cfg cfg;
533         int cd_gpio;
534 } tx6ul_esdhc_cfg[] = {
535 #ifdef CONFIG_TX6_EMMC
536         {
537                 .pads = mmc1_pads,
538                 .num_pads = ARRAY_SIZE(mmc1_pads),
539                 .clkid = MXC_ESDHC2_CLK,
540                 .cfg = {
541                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
542                         .max_bus_width = 4,
543                 },
544                 .cd_gpio = -EINVAL,
545         },
546 #endif
547         {
548                 .pads = mmc0_pads,
549                 .num_pads = ARRAY_SIZE(mmc0_pads),
550                 .clkid = MXC_ESDHC_CLK,
551                 .cfg = {
552                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
553                         .max_bus_width = 4,
554                 },
555                 .cd_gpio = TX6UL_SD1_CD_GPIO,
556         },
557 };
558
559 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
560 {
561         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
562 }
563
564 int board_mmc_getcd(struct mmc *mmc)
565 {
566         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
567
568         if (cfg->cd_gpio < 0)
569                 return 1;
570
571         debug("SD card %d is %spresent (GPIO %d)\n",
572                 cfg - tx6ul_esdhc_cfg,
573                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
574                 cfg->cd_gpio);
575         return !gpio_get_value(cfg->cd_gpio);
576 }
577
578 int board_mmc_init(bd_t *bis)
579 {
580         int i;
581
582         debug("%s@%d: \n", __func__, __LINE__);
583
584         for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) {
585                 struct mmc *mmc;
586                 struct tx6_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
587                 int ret;
588
589                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
590                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
591
592                 if (cfg->cd_gpio >= 0) {
593                         ret = gpio_request_one(cfg->cd_gpio,
594                                         GPIOFLAG_INPUT, "MMC CD");
595                         if (ret) {
596                                 printf("Error %d requesting GPIO%d_%d\n",
597                                         ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
598                                 continue;
599                         }
600                 }
601
602                 debug("%s: Initializing MMC slot %d\n", __func__, i);
603                 fsl_esdhc_initialize(bis, &cfg->cfg);
604
605                 mmc = find_mmc_device(i);
606                 if (mmc == NULL)
607                         continue;
608                 if (board_mmc_getcd(mmc))
609                         mmc_init(mmc);
610         }
611         return 0;
612 }
613 #endif /* CONFIG_CMD_MMC */
614
615 #ifdef CONFIG_FEC_MXC
616
617 #ifndef ETH_ALEN
618 #define ETH_ALEN 6
619 #endif
620
621 int board_eth_init(bd_t *bis)
622 {
623         int ret;
624
625         debug("%s@%d: \n", __func__, __LINE__);
626
627         /* delay at least 21ms for the PHY internal POR signal to deassert */
628         udelay(22000);
629
630         imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads,
631                                         ARRAY_SIZE(tx6ul_enet1_pads));
632
633         /* Deassert RESET to the external phy */
634         gpio_set_value(TX6UL_FEC_RST_GPIO, 1);
635
636         if (getenv("ethaddr")) {
637                 ret = fecmxc_initialize_multi(bis, 0, -1, ENET_BASE_ADDR);
638                 if (ret) {
639                         printf("failed to initialize FEC0: %d\n", ret);
640                         return ret;
641                 }
642         }
643         if (getenv("eth1addr")) {
644                 ret = fecmxc_initialize_multi(bis, 1, -1, ENET2_BASE_ADDR);
645                 if (ret) {
646                         printf("failed to initialize FEC1: %d\n", ret);
647                         return ret;
648                 }
649         }
650         return 0;
651 }
652
653 static void tx6_init_mac(void)
654 {
655         u8 mac[ETH_ALEN];
656
657         imx_get_mac_from_fuse(0, mac);
658         if (!is_valid_ethaddr(mac)) {
659                 printf("No valid MAC address programmed\n");
660                 return;
661         }
662
663         printf("MAC addr from fuse: %pM\n", mac);
664         eth_setenv_enetaddr("ethaddr", mac);
665
666         imx_get_mac_from_fuse(1, mac);
667         eth_setenv_enetaddr("eth1addr", mac);
668 }
669 #else
670 static inline void tx6_init_mac(void)
671 {
672 }
673 #endif /* CONFIG_FEC_MXC */
674
675 enum {
676         LED_STATE_INIT = -1,
677         LED_STATE_OFF,
678         LED_STATE_ON,
679         LED_STATE_ERR,
680 };
681
682 static inline int calc_blink_rate(void)
683 {
684         if (!tx6_temp_check_enabled)
685                 return CONFIG_SYS_HZ;
686
687         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
688                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
689                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
690 }
691
692 void show_activity(int arg)
693 {
694         static int led_state = LED_STATE_INIT;
695         static int blink_rate;
696         static ulong last;
697         int ret;
698
699         switch (led_state) {
700         case LED_STATE_ERR:
701                 return;
702
703         case LED_STATE_INIT:
704                 last = get_timer(0);
705                 ret = gpio_set_value(TX6UL_LED_GPIO, 1);
706                 if (ret)
707                         led_state = LED_STATE_ERR;
708                 else
709                         led_state = LED_STATE_ON;
710                 blink_rate = calc_blink_rate();
711                 break;
712
713         case LED_STATE_ON:
714         case LED_STATE_OFF:
715                 if (get_timer(last) > blink_rate) {
716                         blink_rate = calc_blink_rate();
717                         last = get_timer_masked();
718                         if (led_state == LED_STATE_ON) {
719                                 gpio_set_value(TX6UL_LED_GPIO, 0);
720                         } else {
721                                 gpio_set_value(TX6UL_LED_GPIO, 1);
722                         }
723                         led_state = 1 - led_state;
724                 }
725                 break;
726         }
727 }
728
729 static const iomux_v3_cfg_t stk5_pads[] = {
730         /* SW controlled LED on STK5 baseboard */
731         MX6_PAD_SNVS_TAMPER9__GPIO5_IO09,
732
733         /* I2C bus on DIMM pins 40/41 */
734         MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
735         MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
736
737         /* TSC200x PEN IRQ */
738         MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL),
739 #if 0
740         /* EDT-FT5x06 Polytouch panel */
741         MX6_PAD_NAND_CS2__GPIO6_IO15 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* IRQ */
742         MX6_PAD_EIM_A16__GPIO2_IO22 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* RESET */
743         MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* WAKE */
744
745         /* USBH1 */
746         MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
747         MX6_PAD_EIM_D30__GPIO3_IO30 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
748         /* USBOTG */
749         MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* USBOTG ID */
750         MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
751         MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
752 #endif
753 };
754
755 static const struct gpio stk5_gpios[] = {
756         { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
757
758         { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
759         { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
760         { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
761         { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
762         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
763 };
764
765 #ifdef CONFIG_LCD
766 static u16 tx6_cmap[256];
767 vidinfo_t panel_info = {
768         /* set to max. size supported by SoC */
769         .vl_col = 4096,
770         .vl_row = 1024,
771
772         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
773         .cmap = tx6_cmap,
774 };
775
776 static struct fb_videomode tx6_fb_modes[] = {
777 #ifndef CONFIG_SYS_LVDS_IF
778         {
779                 /* Standard VGA timing */
780                 .name           = "VGA",
781                 .refresh        = 60,
782                 .xres           = 640,
783                 .yres           = 480,
784                 .pixclock       = KHZ2PICOS(25175),
785                 .left_margin    = 48,
786                 .hsync_len      = 96,
787                 .right_margin   = 16,
788                 .upper_margin   = 31,
789                 .vsync_len      = 2,
790                 .lower_margin   = 12,
791                 .sync           = FB_SYNC_CLK_LAT_FALL,
792         },
793         {
794                 /* Emerging ETV570 640 x 480 display. Syncs low active,
795                  * DE high active, 115.2 mm x 86.4 mm display area
796                  * VGA compatible timing
797                  */
798                 .name           = "ETV570",
799                 .refresh        = 60,
800                 .xres           = 640,
801                 .yres           = 480,
802                 .pixclock       = KHZ2PICOS(25175),
803                 .left_margin    = 114,
804                 .hsync_len      = 30,
805                 .right_margin   = 16,
806                 .upper_margin   = 32,
807                 .vsync_len      = 3,
808                 .lower_margin   = 10,
809                 .sync           = FB_SYNC_CLK_LAT_FALL,
810         },
811         {
812                 /* Emerging ET0350G0DH6 320 x 240 display.
813                  * 70.08 mm x 52.56 mm display area.
814                  */
815                 .name           = "ET0350",
816                 .refresh        = 60,
817                 .xres           = 320,
818                 .yres           = 240,
819                 .pixclock       = KHZ2PICOS(6500),
820                 .left_margin    = 68 - 34,
821                 .hsync_len      = 34,
822                 .right_margin   = 20,
823                 .upper_margin   = 18 - 3,
824                 .vsync_len      = 3,
825                 .lower_margin   = 4,
826                 .sync           = FB_SYNC_CLK_LAT_FALL,
827         },
828         {
829                 /* Emerging ET0430G0DH6 480 x 272 display.
830                  * 95.04 mm x 53.856 mm display area.
831                  */
832                 .name           = "ET0430",
833                 .refresh        = 60,
834                 .xres           = 480,
835                 .yres           = 272,
836                 .pixclock       = KHZ2PICOS(9000),
837                 .left_margin    = 2,
838                 .hsync_len      = 41,
839                 .right_margin   = 2,
840                 .upper_margin   = 2,
841                 .vsync_len      = 10,
842                 .lower_margin   = 2,
843         },
844         {
845                 /* Emerging ET0500G0DH6 800 x 480 display.
846                  * 109.6 mm x 66.4 mm display area.
847                  */
848                 .name           = "ET0500",
849                 .refresh        = 60,
850                 .xres           = 800,
851                 .yres           = 480,
852                 .pixclock       = KHZ2PICOS(33260),
853                 .left_margin    = 216 - 128,
854                 .hsync_len      = 128,
855                 .right_margin   = 1056 - 800 - 216,
856                 .upper_margin   = 35 - 2,
857                 .vsync_len      = 2,
858                 .lower_margin   = 525 - 480 - 35,
859                 .sync           = FB_SYNC_CLK_LAT_FALL,
860         },
861         {
862                 /* Emerging ETQ570G0DH6 320 x 240 display.
863                  * 115.2 mm x 86.4 mm display area.
864                  */
865                 .name           = "ETQ570",
866                 .refresh        = 60,
867                 .xres           = 320,
868                 .yres           = 240,
869                 .pixclock       = KHZ2PICOS(6400),
870                 .left_margin    = 38,
871                 .hsync_len      = 30,
872                 .right_margin   = 30,
873                 .upper_margin   = 16, /* 15 according to datasheet */
874                 .vsync_len      = 3, /* TVP -> 1>x>5 */
875                 .lower_margin   = 4, /* 4.5 according to datasheet */
876                 .sync           = FB_SYNC_CLK_LAT_FALL,
877         },
878         {
879                 /* Emerging ET0700G0DH6 800 x 480 display.
880                  * 152.4 mm x 91.44 mm display area.
881                  */
882                 .name           = "ET0700",
883                 .refresh        = 60,
884                 .xres           = 800,
885                 .yres           = 480,
886                 .pixclock       = KHZ2PICOS(33260),
887                 .left_margin    = 216 - 128,
888                 .hsync_len      = 128,
889                 .right_margin   = 1056 - 800 - 216,
890                 .upper_margin   = 35 - 2,
891                 .vsync_len      = 2,
892                 .lower_margin   = 525 - 480 - 35,
893                 .sync           = FB_SYNC_CLK_LAT_FALL,
894         },
895         {
896                 /* Emerging ET070001DM6 800 x 480 display.
897                  * 152.4 mm x 91.44 mm display area.
898                  */
899                 .name           = "ET070001DM6",
900                 .refresh        = 60,
901                 .xres           = 800,
902                 .yres           = 480,
903                 .pixclock       = KHZ2PICOS(33260),
904                 .left_margin    = 216 - 128,
905                 .hsync_len      = 128,
906                 .right_margin   = 1056 - 800 - 216,
907                 .upper_margin   = 35 - 2,
908                 .vsync_len      = 2,
909                 .lower_margin   = 525 - 480 - 35,
910                 .sync           = 0,
911         },
912 #else
913         {
914                 /* HannStar HSD100PXN1
915                  * 202.7m mm x 152.06 mm display area.
916                  */
917                 .name           = "HSD100PXN1",
918                 .refresh        = 60,
919                 .xres           = 1024,
920                 .yres           = 768,
921                 .pixclock       = KHZ2PICOS(65000),
922                 .left_margin    = 0,
923                 .hsync_len      = 0,
924                 .right_margin   = 320,
925                 .upper_margin   = 0,
926                 .vsync_len      = 0,
927                 .lower_margin   = 38,
928                 .sync           = FB_SYNC_CLK_LAT_FALL,
929         },
930 #endif
931         {
932                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
933                 .refresh        = 60,
934                 .left_margin    = 48,
935                 .hsync_len      = 96,
936                 .right_margin   = 16,
937                 .upper_margin   = 31,
938                 .vsync_len      = 2,
939                 .lower_margin   = 12,
940                 .sync           = FB_SYNC_CLK_LAT_FALL,
941         },
942 };
943
944 static int lcd_enabled = 1;
945 static int lcd_bl_polarity;
946
947 static int lcd_backlight_polarity(void)
948 {
949         return lcd_bl_polarity;
950 }
951
952 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
953 #ifdef CONFIG_LCD
954         /* LCD RESET */
955         MX6_PAD_LCD_RESET__GPIO3_IO04 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
956         /* LCD POWER_ENABLE */
957         MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
958         /* LCD Backlight (PWM) */
959         MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
960         /* Display */
961         MX6_PAD_LCD_DATA00__LCDIF_DATA00,
962         MX6_PAD_LCD_DATA01__LCDIF_DATA01,
963         MX6_PAD_LCD_DATA02__LCDIF_DATA02,
964         MX6_PAD_LCD_DATA03__LCDIF_DATA03,
965         MX6_PAD_LCD_DATA04__LCDIF_DATA04,
966         MX6_PAD_LCD_DATA05__LCDIF_DATA05,
967         MX6_PAD_LCD_DATA06__LCDIF_DATA06,
968         MX6_PAD_LCD_DATA07__LCDIF_DATA07,
969         MX6_PAD_LCD_DATA08__LCDIF_DATA08,
970         MX6_PAD_LCD_DATA09__LCDIF_DATA09,
971         MX6_PAD_LCD_DATA10__LCDIF_DATA10,
972         MX6_PAD_LCD_DATA11__LCDIF_DATA11,
973         MX6_PAD_LCD_DATA12__LCDIF_DATA12,
974         MX6_PAD_LCD_DATA13__LCDIF_DATA13,
975         MX6_PAD_LCD_DATA14__LCDIF_DATA14,
976         MX6_PAD_LCD_DATA15__LCDIF_DATA15,
977         MX6_PAD_LCD_DATA16__LCDIF_DATA16,
978         MX6_PAD_LCD_DATA17__LCDIF_DATA17,
979         MX6_PAD_LCD_DATA18__LCDIF_DATA18,
980         MX6_PAD_LCD_DATA19__LCDIF_DATA19,
981         MX6_PAD_LCD_DATA20__LCDIF_DATA20,
982         MX6_PAD_LCD_DATA21__LCDIF_DATA21,
983         MX6_PAD_LCD_DATA22__LCDIF_DATA22,
984         MX6_PAD_LCD_DATA23__LCDIF_DATA23,
985         MX6_PAD_LCD_HSYNC__LCDIF_HSYNC, /* HSYNC */
986         MX6_PAD_LCD_VSYNC__LCDIF_VSYNC, /* VSYNC */
987         MX6_PAD_LCD_ENABLE__LCDIF_ENABLE, /* OE_ACD */
988         MX6_PAD_LCD_CLK__LCDIF_CLK, /* LSCLK */
989 #endif
990 };
991
992 static const struct gpio stk5_lcd_gpios[] = {
993         { TX6UL_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
994         { TX6UL_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
995         { TX6UL_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
996 };
997
998 /* run with valid env from NAND/eMMC */
999 void lcd_enable(void)
1000 {
1001         /* HACK ALERT:
1002          * global variable from common/lcd.c
1003          * Set to 0 here to prevent messages from going to LCD
1004          * rather than serial console
1005          */
1006         lcd_is_enabled = 0;
1007
1008         if (lcd_enabled) {
1009                 karo_load_splashimage(1);
1010
1011                 debug("Switching LCD on\n");
1012                 gpio_set_value(TX6UL_LCD_PWR_GPIO, 1);
1013                 udelay(100);
1014                 gpio_set_value(TX6UL_LCD_RST_GPIO, 1);
1015                 udelay(300000);
1016                 gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
1017                         lcd_backlight_polarity());
1018         }
1019 }
1020
1021 static void lcd_disable(void)
1022 {
1023         if (lcd_enabled) {
1024                 printf("Disabling LCD\n");
1025                 panel_info.vl_row = 0;
1026                 lcd_enabled = 0;
1027         }
1028 }
1029
1030 void lcd_ctrl_init(void *lcdbase)
1031 {
1032         int color_depth = 24;
1033         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1034         const char *vm;
1035         unsigned long val;
1036         int refresh = 60;
1037         struct fb_videomode *p = &tx6_fb_modes[0];
1038         struct fb_videomode fb_mode;
1039         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1040
1041         if (!lcd_enabled) {
1042                 debug("LCD disabled\n");
1043                 return;
1044         }
1045
1046         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1047                 lcd_disable();
1048                 setenv("splashimage", NULL);
1049                 return;
1050         }
1051
1052         karo_fdt_move_fdt();
1053         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1054
1055         if (video_mode == NULL) {
1056                 lcd_disable();
1057                 return;
1058         }
1059         vm = video_mode;
1060         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1061                 p = &fb_mode;
1062                 debug("Using video mode from FDT\n");
1063                 vm += strlen(vm);
1064                 if (fb_mode.xres > panel_info.vl_col ||
1065                         fb_mode.yres > panel_info.vl_row) {
1066                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1067                                 fb_mode.xres, fb_mode.yres,
1068                                 panel_info.vl_col, panel_info.vl_row);
1069                         lcd_enabled = 0;
1070                         return;
1071                 }
1072         }
1073         if (p->name != NULL)
1074                 debug("Trying compiled-in video modes\n");
1075         while (p->name != NULL) {
1076                 if (strcmp(p->name, vm) == 0) {
1077                         debug("Using video mode: '%s'\n", p->name);
1078                         vm += strlen(vm);
1079                         break;
1080                 }
1081                 p++;
1082         }
1083         if (*vm != '\0')
1084                 debug("Trying to decode video_mode: '%s'\n", vm);
1085         while (*vm != '\0') {
1086                 if (*vm >= '0' && *vm <= '9') {
1087                         char *end;
1088
1089                         val = simple_strtoul(vm, &end, 0);
1090                         if (end > vm) {
1091                                 if (!xres_set) {
1092                                         if (val > panel_info.vl_col)
1093                                                 val = panel_info.vl_col;
1094                                         p->xres = val;
1095                                         panel_info.vl_col = val;
1096                                         xres_set = 1;
1097                                 } else if (!yres_set) {
1098                                         if (val > panel_info.vl_row)
1099                                                 val = panel_info.vl_row;
1100                                         p->yres = val;
1101                                         panel_info.vl_row = val;
1102                                         yres_set = 1;
1103                                 } else if (!bpp_set) {
1104                                         switch (val) {
1105                                         case 8:
1106                                         case 16:
1107                                         case 18:
1108                                         case 24:
1109                                         case 32:
1110                                                 color_depth = val;
1111                                                 break;
1112
1113                                         default:
1114                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1115                                                         end - vm, vm, color_depth);
1116                                         }
1117                                         bpp_set = 1;
1118                                 } else if (!refresh_set) {
1119                                         refresh = val;
1120                                         refresh_set = 1;
1121                                 }
1122                         }
1123                         vm = end;
1124                 }
1125                 switch (*vm) {
1126                 case '@':
1127                         bpp_set = 1;
1128                         /* fallthru */
1129                 case '-':
1130                         yres_set = 1;
1131                         /* fallthru */
1132                 case 'x':
1133                         xres_set = 1;
1134                         /* fallthru */
1135                 case 'M':
1136                 case 'R':
1137                         vm++;
1138                         break;
1139
1140                 default:
1141                         if (*vm != '\0')
1142                                 vm++;
1143                 }
1144         }
1145         if (p->xres == 0 || p->yres == 0) {
1146                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1147                 lcd_enabled = 0;
1148                 printf("Supported video modes are:");
1149                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1150                         printf(" %s", p->name);
1151                 }
1152                 printf("\n");
1153                 return;
1154         }
1155         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1156                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1157                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1158                 lcd_enabled = 0;
1159                 return;
1160         }
1161         panel_info.vl_col = p->xres;
1162         panel_info.vl_row = p->yres;
1163
1164         switch (color_depth) {
1165         case 8:
1166                 panel_info.vl_bpix = LCD_COLOR8;
1167                 break;
1168         case 16:
1169                 panel_info.vl_bpix = LCD_COLOR16;
1170                 break;
1171         default:
1172                 panel_info.vl_bpix = LCD_COLOR32;
1173         }
1174
1175         p->pixclock = KHZ2PICOS(refresh *
1176                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1177                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1178                                 1000);
1179         debug("Pixel clock set to %lu.%03lu MHz\n",
1180                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1181
1182         if (p != &fb_mode) {
1183                 int ret;
1184
1185                 debug("Creating new display-timing node from '%s'\n",
1186                         video_mode);
1187                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1188                 if (ret)
1189                         printf("Failed to create new display-timing node from '%s': %d\n",
1190                                 video_mode, ret);
1191         }
1192
1193         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1194         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1195                                         ARRAY_SIZE(stk5_lcd_pads));
1196
1197         debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
1198                 color_depth, refresh);
1199
1200         if (karo_load_splashimage(0) == 0) {
1201                 char vmode[128];
1202
1203                 /* setup env variable for mxsfb display driver */
1204                 snprintf(vmode, sizeof(vmode),
1205                         "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
1206                         p->xres, p->yres, p->left_margin, p->right_margin,
1207                         p->upper_margin, p->lower_margin, p->hsync_len,
1208                         p->vsync_len, p->sync, p->pixclock, color_depth);
1209                 setenv("videomode", vmode);
1210
1211                 debug("Initializing LCD controller\n");
1212                 lcdif_clk_enable();
1213                 video_hw_init();
1214                 setenv("videomode", NULL);
1215         } else {
1216                 debug("Skipping initialization of LCD controller\n");
1217         }
1218 }
1219 #else
1220 #define lcd_enabled 0
1221 #endif /* CONFIG_LCD */
1222
1223 static void stk5_board_init(void)
1224 {
1225         int ret;
1226
1227         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1228         if (ret < 0) {
1229                 printf("Failed to request stk5_gpios: %d\n", ret);
1230                 return;
1231         }
1232         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1233         debug("%s@%d: \n", __func__, __LINE__);
1234 }
1235
1236 static void stk5v3_board_init(void)
1237 {
1238         debug("%s@%d: \n", __func__, __LINE__);
1239         stk5_board_init();
1240         debug("%s@%d: \n", __func__, __LINE__);
1241 }
1242
1243 static void stk5v5_board_init(void)
1244 {
1245         int ret;
1246
1247         stk5_board_init();
1248
1249         ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
1250                         "Flexcan Transceiver");
1251         if (ret) {
1252                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1253                 return;
1254         }
1255
1256         imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 |
1257                         MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL));
1258 }
1259
1260 static void tx6ul_set_cpu_clock(void)
1261 {
1262         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1263
1264         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1265                 return;
1266
1267         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1268                 printf("%s detected; skipping cpu clock change\n",
1269                         (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1270                 return;
1271         }
1272         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1273                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1274                 printf("CPU clock set to %lu.%03lu MHz\n",
1275                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1276         } else {
1277                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1278         }
1279 }
1280
1281 int board_late_init(void)
1282 {
1283         const char *baseboard;
1284
1285         debug("%s@%d: \n", __func__, __LINE__);
1286
1287         env_cleanup();
1288
1289         if (tx6_temp_check_enabled)
1290                 check_cpu_temperature(1);
1291
1292         tx6ul_set_cpu_clock();
1293
1294         if (had_ctrlc())
1295                 setenv_ulong("safeboot", 1);
1296         else if (wrsr & WRSR_TOUT)
1297                 setenv_ulong("wdreset", 1);
1298         else
1299                 karo_fdt_move_fdt();
1300
1301         baseboard = getenv("baseboard");
1302         if (!baseboard)
1303                 goto exit;
1304
1305         printf("Baseboard: %s\n", baseboard);
1306
1307         if (strncmp(baseboard, "stk5", 4) == 0) {
1308                 if ((strlen(baseboard) == 4) ||
1309                         strcmp(baseboard, "stk5-v3") == 0) {
1310                         stk5v3_board_init();
1311                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1312                         const char *otg_mode = getenv("otg_mode");
1313
1314                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1315                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1316                                         otg_mode, baseboard);
1317                                 setenv("otg_mode", "none");
1318                         }
1319                         stk5v5_board_init();
1320                 } else {
1321                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1322                                 baseboard + 4);
1323                 }
1324         } else {
1325                 printf("WARNING: Unsupported baseboard: '%s'\n",
1326                         baseboard);
1327                 if (!had_ctrlc())
1328                         return -EINVAL;
1329         }
1330
1331 exit:
1332         debug("%s@%d: \n", __func__, __LINE__);
1333         tx6_init_mac();
1334         debug("%s@%d: \n", __func__, __LINE__);
1335
1336         clear_ctrlc();
1337         return 0;
1338 }
1339
1340 #ifdef CONFIG_SERIAL_TAG
1341 void get_board_serial(struct tag_serialnr *serialnr)
1342 {
1343         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1344         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1345
1346         serialnr->low = readl(&fuse->cfg0);
1347         serialnr->high = readl(&fuse->cfg1);
1348 }
1349 #endif
1350
1351 #if defined(CONFIG_OF_BOARD_SETUP)
1352 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1353 #include <jffs2/jffs2.h>
1354 #include <mtd_node.h>
1355 static struct node_info nodes[] = {
1356         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1357 };
1358 #else
1359 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1360 #endif
1361
1362 static const char *tx6_touchpanels[] = {
1363         "ti,tsc2007",
1364         "edt,edt-ft5x06",
1365         "eeti,egalax_ts",
1366 };
1367
1368 int ft_board_setup(void *blob, bd_t *bd)
1369 {
1370         const char *baseboard = getenv("baseboard");
1371         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1372         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1373         int ret;
1374
1375         ret = fdt_increase_size(blob, 4096);
1376         if (ret) {
1377                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1378                 return ret;
1379         }
1380         if (stk5_v5)
1381                 karo_fdt_enable_node(blob, "stk5led", 0);
1382
1383         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1384
1385         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1386                                 ARRAY_SIZE(tx6_touchpanels));
1387         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1388         karo_fdt_fixup_flexcan(blob, stk5_v5);
1389
1390         karo_fdt_update_fb_mode(blob, video_mode);
1391
1392         return 0;
1393 }
1394 #endif /* CONFIG_OF_BOARD_SETUP */