board/karo/tx6/tx6ul.c

   1 /*
   2  * Copyright (C) 2015 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  *
   6  */
   7 #include <common.h>
   8 #include <errno.h>
   9 #include <libfdt.h>
  10 #include <fdt_support.h>
  11 #include <lcd.h>
  12 #include <netdev.h>
  13 #include <mmc.h>
  14 #include <fsl_esdhc.h>
  15 #include <video_fb.h>
  16 #include <ipu.h>
  17 #include <mxcfb.h>
  18 #include <i2c.h>
  19 #include <linux/fb.h>
  20 #include <asm/io.h>
  21 #include <asm/gpio.h>
  22 #include <asm/arch/mx6-pins.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/hab.h>
  25 #include <asm/arch/imx-regs.h>
  26 #include <asm/arch/crm_regs.h>
  27 #include <asm/arch/sys_proto.h>
  28
  29 #include "../common/karo.h"
  30 #include "pmic.h"
  31
  32 #define __data __attribute__((section(".data")))
  33
  34 #define TX6UL_FEC_RST_GPIO              IMX_GPIO_NR(5, 6)
  35 #define TX6UL_FEC_PWR_GPIO              IMX_GPIO_NR(5, 7)
  36 #define TX6UL_FEC_INT_GPIO              IMX_GPIO_NR(5, 5)
  37
  38 #define TX6UL_FEC2_RST_GPIO             IMX_GPIO_NR(4, 28)
  39 #define TX6UL_FEC2_INT_GPIO             IMX_GPIO_NR(4, 27)
  40
  41 #define TX6UL_LED_GPIO                  IMX_GPIO_NR(5, 9)
  42
  43 #define TX6UL_LCD_PWR_GPIO              IMX_GPIO_NR(5, 4)
  44 #define TX6UL_LCD_RST_GPIO              IMX_GPIO_NR(3, 4)
  45 #define TX6UL_LCD_BACKLIGHT_GPIO        IMX_GPIO_NR(4, 16)
  46
  47 #ifdef CONFIG_SYS_I2C_SOFT
  48 #define TX6UL_I2C1_SCL_GPIO             CONFIG_SOFT_I2C_GPIO_SCL
  49 #define TX6UL_I2C1_SDA_GPIO             CONFIG_SOFT_I2C_GPIO_SDA
  50 #endif
  51
  52 #define TX6UL_SD1_CD_GPIO               IMX_GPIO_NR(4, 14)
  53
  54 #ifdef CONFIG_MX6_TEMPERATURE_MIN
  55 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
  56 #else
  57 #define TEMPERATURE_MIN                 (-40)
  58 #endif
  59 #ifdef CONFIG_MX6_TEMPERATURE_HOT
  60 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
  61 #else
  62 #define TEMPERATURE_HOT                 80
  63 #endif
  64
  65 DECLARE_GLOBAL_DATA_PTR;
  66
  67 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  68
  69 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
  70 #ifdef CONFIG_SECURE_BOOT
  71 char __csf_data[0] __attribute__((section(".__csf_data")));
  72 #endif
  73
  74 static const iomux_v3_cfg_t const tx6ul_pads[] = {
  75         /* UART pads */
  76 #if CONFIG_MXC_UART_BASE == UART1_BASE
  77         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX,
  78         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX,
  79         MX6_PAD_UART1_RTS_B__UART1_DCE_RTS,
  80         MX6_PAD_UART1_CTS_B__UART1_DCE_CTS,
  81 #endif
  82 #if CONFIG_MXC_UART_BASE == UART2_BASE
  83         MX6_PAD_UART2_TX_DATA__UART2_DCE_TX,
  84         MX6_PAD_UART2_RX_DATA__UART2_DCE_RX,
  85         MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS,
  86         MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS,
  87 #endif
  88 #if CONFIG_MXC_UART_BASE == UART5_BASE
  89         MX6_PAD_GPIO1_IO04__UART5_DCE_TX,
  90         MX6_PAD_GPIO1_IO05__UART5_DCE_RX,
  91         MX6_PAD_GPIO1_IO08__UART5_DCE_RTS,
  92         MX6_PAD_GPIO1_IO09__UART5_DCE_CTS,
  93 #endif
  94         /* internal I2C */
  95         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
  96                         MUX_PAD_CTRL(PAD_CTL_DSE_240ohm), /* I2C SCL */
  97         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
  98                         MUX_PAD_CTRL(PAD_CTL_DSE_240ohm | PAD_CTL_HYS |
  99                         PAD_CTL_ODE), /* I2C SDA */
 100
 101         /* FEC PHY GPIO functions */
 102         MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_CFG_SION, /* PHY POWER */
 103         MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | MUX_CFG_SION, /* PHY RESET */
 104         MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
 105                                                         PAD_CTL_DSE_40ohm), /* PHY INT */
 106 };
 107
 108 #define TX6_ENET_PAD_CTRL       (PAD_CTL_SPEED_HIGH |   \
 109                                 PAD_CTL_DSE_48ohm |     \
 110                                 PAD_CTL_PUS_100K_UP |   \
 111                                 PAD_CTL_SRE_FAST)
 112 #define TX6_GPIO_OUT_PAD_CTRL   (PAD_CTL_SPEED_LOW |    \
 113                                 PAD_CTL_DSE_60ohm |     \
 114                                 PAD_CTL_SRE_SLOW)
 115 #define TX6_GPIO_IN_PAD_CTRL    (PAD_CTL_SPEED_LOW |    \
 116                                 PAD_CTL_PUS_47K_UP)
 117
 118 static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = {
 119         /* FEC functions */
 120         MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_48ohm |
 121                                 PAD_CTL_SPEED_MED),
 122         MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
 123                                 PAD_CTL_DSE_48ohm |
 124                                 PAD_CTL_SPEED_MED),
 125         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_CFG_SION |
 126                                 MUX_PAD_CTRL(PAD_CTL_SPEED_MED |
 127                                 PAD_CTL_DSE_40ohm |
 128                                 PAD_CTL_SRE_FAST),
 129         MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 130         MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 131         MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 132         MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 133         MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 134         MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 135         MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 136 };
 137
 138 static const iomux_v3_cfg_t const tx6ul_enet2_pads[] = {
 139         MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_CFG_SION |
 140                                 MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |
 141                                 PAD_CTL_DSE_48ohm |
 142                                 PAD_CTL_SRE_FAST),
 143         MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 144         MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 145         MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 146         MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 147         MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 148         MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 149         MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 150 };
 151
 152 #define TX6_I2C_PAD_CTRL        (PAD_CTL_PUS_22K_UP |   \
 153                                 PAD_CTL_SPEED_MED |     \
 154                                 PAD_CTL_DSE_34ohm |     \
 155                                 PAD_CTL_SRE_FAST)
 156
 157 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
 158         /* internal I2C */
 159         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
 160                         MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
 161         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
 162                         MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
 163 };
 164
 165 static const struct gpio const tx6ul_gpios[] = {
 166 #ifdef CONFIG_SYS_I2C_SOFT
 167         /* These two entries are used to forcefully reinitialize the I2C bus */
 168         { TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
 169         { TX6UL_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
 170 #endif
 171         { TX6UL_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 172         { TX6UL_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 173         { TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
 174 };
 175
 176 static const struct gpio const tx6ul_fec2_gpios[] = {
 177         { TX6UL_FEC2_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC2 PHY RESET", },
 178         { TX6UL_FEC2_INT_GPIO, GPIOFLAG_INPUT, "FEC2 PHY INT", },
 179 };
 180
 181 #define GPIO_DR 0
 182 #define GPIO_DIR 4
 183 #define GPIO_PSR 8
 184
 185 /* run with default environment */
 186 #if defined(TX6UL_I2C1_SCL_GPIO) && defined(TX6UL_I2C1_SDA_GPIO)
 187 static void tx6_i2c_recover(void)
 188 {
 189         int i;
 190         int bad = 0;
 191 #define SCL_BIT         (1 << (TX6UL_I2C1_SCL_GPIO % 32))
 192 #define SDA_BIT         (1 << (TX6UL_I2C1_SDA_GPIO % 32))
 193 #define I2C_GPIO_BASE   (GPIO1_BASE_ADDR + TX6UL_I2C1_SCL_GPIO / 32 * 0x4000)
 194
 195         if ((readl(I2C_GPIO_BASE + GPIO_PSR) &
 196                         (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
 197                 return;
 198
 199         debug("Clearing I2C bus\n");
 200         if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SCL_BIT)) {
 201                 printf("I2C SCL stuck LOW\n");
 202                 bad++;
 203
 204                 writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
 205                         I2C_GPIO_BASE + GPIO_DR);
 206                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
 207                         I2C_GPIO_BASE + GPIO_DIR);
 208         }
 209         if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)) {
 210                 printf("I2C SDA stuck LOW\n");
 211                 bad++;
 212
 213                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) & ~SDA_BIT,
 214                         I2C_GPIO_BASE + GPIO_DIR);
 215                 writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
 216                         I2C_GPIO_BASE + GPIO_DR);
 217                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
 218                         I2C_GPIO_BASE + GPIO_DIR);
 219
 220                 imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
 221                                                 ARRAY_SIZE(tx6_i2c_gpio_pads));
 222                 udelay(10);
 223
 224                 for (i = 0; i < 18; i++) {
 225                         u32 reg = readl(I2C_GPIO_BASE + GPIO_DR) ^ SCL_BIT;
 226
 227                         debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
 228                         writel(reg, I2C_GPIO_BASE + GPIO_DR);
 229                         udelay(10);
 230                         if (reg & SCL_BIT &&
 231                                 readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)
 232                                 break;
 233                 }
 234         }
 235         if (bad) {
 236                 u32 reg = readl(I2C_GPIO_BASE + GPIO_PSR);
 237
 238                 if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
 239                         printf("I2C bus recovery succeeded\n");
 240                 } else {
 241                         printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
 242                                 SCL_BIT | SDA_BIT);
 243                 }
 244         }
 245 }
 246 #else
 247 static inline void tx6_i2c_recover(void)
 248 {
 249 }
 250 #endif
 251
 252 /* placed in section '.data' to prevent overwriting relocation info
 253  * overlayed with bss
 254  */
 255 static u32 wrsr __data;
 256
 257 #define WRSR_POR                        (1 << 4)
 258 #define WRSR_TOUT                       (1 << 1)
 259 #define WRSR_SFTW                       (1 << 0)
 260
 261 static void print_reset_cause(void)
 262 {
 263         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 264         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 265         u32 srsr;
 266         char *dlm = "";
 267
 268         printf("Reset cause: ");
 269
 270         srsr = readl(&src_regs->srsr);
 271         wrsr = readw(wdt_base + 4);
 272
 273         if (wrsr & WRSR_POR) {
 274                 printf("%sPOR", dlm);
 275                 dlm = " | ";
 276         }
 277         if (srsr & 0x00004) {
 278                 printf("%sCSU", dlm);
 279                 dlm = " | ";
 280         }
 281         if (srsr & 0x00008) {
 282                 printf("%sIPP USER", dlm);
 283                 dlm = " | ";
 284         }
 285         if (srsr & 0x00010) {
 286                 if (wrsr & WRSR_SFTW) {
 287                         printf("%sSOFT", dlm);
 288                         dlm = " | ";
 289                 }
 290                 if (wrsr & WRSR_TOUT) {
 291                         printf("%sWDOG", dlm);
 292                         dlm = " | ";
 293                 }
 294         }
 295         if (srsr & 0x00020) {
 296                 printf("%sJTAG HIGH-Z", dlm);
 297                 dlm = " | ";
 298         }
 299         if (srsr & 0x00040) {
 300                 printf("%sJTAG SW", dlm);
 301                 dlm = " | ";
 302         }
 303         if (srsr & 0x10000) {
 304                 printf("%sWARM BOOT", dlm);
 305                 dlm = " | ";
 306         }
 307         if (dlm[0] == '\0')
 308                 printf("unknown");
 309
 310         printf("\n");
 311 }
 312
 313 #ifdef CONFIG_IMX6_THERMAL
 314 #include <thermal.h>
 315 #include <imx_thermal.h>
 316 #include <fuse.h>
 317
 318 static void print_temperature(void)
 319 {
 320         struct udevice *thermal_dev;
 321         int cpu_tmp, minc, maxc, ret;
 322         char const *grade_str;
 323         static u32 __data thermal_calib;
 324
 325         puts("Temperature: ");
 326         switch (get_cpu_temp_grade(&minc, &maxc)) {
 327         case TEMP_AUTOMOTIVE:
 328                 grade_str = "Automotive";
 329                 break;
 330         case TEMP_INDUSTRIAL:
 331                 grade_str = "Industrial";
 332                 break;
 333         case TEMP_EXTCOMMERCIAL:
 334                 grade_str = "Extended Commercial";
 335                 break;
 336         default:
 337                 grade_str = "Commercial";
 338         }
 339         printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
 340         ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
 341         if (ret == 0) {
 342                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
 343
 344                 if (ret == 0)
 345                         printf(" at %dC", cpu_tmp);
 346                 else
 347                         puts(" - failed to read sensor data");
 348         } else {
 349                 puts(" - no sensor device found");
 350         }
 351
 352         if (fuse_read(1, 6, &thermal_calib) == 0) {
 353                 printf(" - calibration data 0x%08x\n", thermal_calib);
 354         } else {
 355                 puts(" - Failed to read thermal calib fuse\n");
 356         }
 357 }
 358 #else
 359 static inline void print_temperature(void)
 360 {
 361 }
 362 #endif
 363
 364 int checkboard(void)
 365 {
 366         u32 cpurev = get_cpu_rev();
 367         char *cpu_str = "?";
 368
 369         if (is_cpu_type(MXC_CPU_MX6SL))
 370                 cpu_str = "SL";
 371         else if (is_cpu_type(MXC_CPU_MX6DL))
 372                 cpu_str = "DL";
 373         else if (is_cpu_type(MXC_CPU_MX6SOLO))
 374                 cpu_str = "SOLO";
 375         else if (is_cpu_type(MXC_CPU_MX6Q))
 376                 cpu_str = "Q";
 377         else if (is_cpu_type(MXC_CPU_MX6UL))
 378                 cpu_str = "UL";
 379
 380         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
 381                 cpu_str,
 382                 (cpurev & 0x000F0) >> 4,
 383                 (cpurev & 0x0000F) >> 0,
 384                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 385
 386         print_temperature();
 387         print_reset_cause();
 388 #ifdef CONFIG_MX6_TEMPERATURE_HOT
 389         check_cpu_temperature(1);
 390 #endif
 391         tx6_i2c_recover();
 392         return 0;
 393 }
 394
 395 /* serial port not initialized at this point */
 396 int board_early_init_f(void)
 397 {
 398         return 0;
 399 }
 400
 401 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 402 static bool tx6_temp_check_enabled = true;
 403 #else
 404 #define tx6_temp_check_enabled  0
 405 #endif
 406
 407 static inline u8 tx6ul_mem_suffix(void)
 408 {
 409 #ifdef CONFIG_TX6_NAND
 410         return '0';
 411 #else
 412         return '1';
 413 #endif
 414 }
 415
 416 #ifdef CONFIG_RN5T567
 417 /* PMIC settings */
 418 #define VDD_RTC_VAL             rn5t_mV_to_regval_rtc(3000)
 419 #define VDD_CORE_VAL            rn5t_mV_to_regval(1300)         /* DCDC1 */
 420 #define VDD_CORE_VAL_LP         rn5t_mV_to_regval(900)
 421 #define VDD_DDR_VAL             rn5t_mV_to_regval(1350)         /* DCDC3 */
 422 #define VDD_DDR_VAL_LP          rn5t_mV_to_regval(1350)
 423 #define VDD_HIGH_VAL            rn5t_mV_to_regval(3300)         /* DCDC4 */
 424 #define VDD_HIGH_VAL_LP         rn5t_mV_to_regval(3300)
 425 #define VDD_CSI_VAL             rn5t_mV_to_regval2(3300)        /* LDO4 */
 426 #define VDD_CSI_VAL_LP          rn5t_mV_to_regval2(3300)
 427
 428 static struct pmic_regs rn5t567_regs[] = {
 429         { RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, },
 430         { RN5T567_DC2CTL, DC2_DC2DIS, },
 431         { RN5T567_DC1DAC, VDD_CORE_VAL, },
 432         { RN5T567_DC3DAC, VDD_DDR_VAL, },
 433         { RN5T567_DC4DAC, VDD_HIGH_VAL, },
 434         { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
 435         { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
 436         { RN5T567_DC4DAC_SLP, VDD_HIGH_VAL_LP, },
 437         { RN5T567_LDOEN1, 0x01f, ~0x1f, },
 438         { RN5T567_LDOEN2, 0x10, ~0x30, },
 439         { RN5T567_LDODIS, 0x00, },
 440         { RN5T567_LDO4DAC, VDD_CSI_VAL, },
 441         { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
 442         { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
 443 };
 444
 445 static int pmic_addr __maybe_unused = 0x33;
 446 #endif
 447
 448 int board_init(void)
 449 {
 450         int ret;
 451         u32 cpurev = get_cpu_rev();
 452
 453         debug("%s@%d: \n", __func__, __LINE__);
 454
 455         printf("Board: Ka-Ro TXUL-%c01%c\n",
 456                 ((cpurev &0xff) > 0x10) ? '5' : '0',
 457                 tx6ul_mem_suffix());
 458
 459         get_hab_status();
 460
 461         ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios));
 462         if (ret < 0) {
 463                 printf("Failed to request tx6ul_gpios: %d\n", ret);
 464         }
 465         imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads));
 466
 467         /* Address of boot parameters */
 468         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 469         gd->bd->bi_arch_number = -1;
 470
 471         if (ctrlc() || (wrsr & WRSR_TOUT)) {
 472                 if (wrsr & WRSR_TOUT)
 473                         printf("WDOG RESET detected; Skipping PMIC setup\n");
 474                 else
 475                         printf("<CTRL-C> detected; safeboot enabled\n");
 476 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 477                 tx6_temp_check_enabled = false;
 478 #endif
 479                 return 0;
 480         }
 481
 482         ret = tx6_pmic_init(pmic_addr, rn5t567_regs, ARRAY_SIZE(rn5t567_regs));
 483         if (ret) {
 484                 printf("Failed to setup PMIC voltages: %d\n", ret);
 485                 hang();
 486         }
 487         return 0;
 488 }
 489
 490 int dram_init(void)
 491 {
 492         debug("%s@%d: \n", __func__, __LINE__);
 493
 494         /* dram_init must store complete ramsize in gd->ram_size */
 495         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 496                                 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
 497         return 0;
 498 }
 499
 500 void dram_init_banksize(void)
 501 {
 502         debug("%s@%d: \n", __func__, __LINE__);
 503
 504         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 505         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 506                         PHYS_SDRAM_1_SIZE);
 507 #if CONFIG_NR_DRAM_BANKS > 1
 508         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 509         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 510                         PHYS_SDRAM_2_SIZE);
 511 #endif
 512 }
 513
 514 #ifdef  CONFIG_FSL_ESDHC
 515 #define TX6_SD_PAD_CTRL         (PAD_CTL_PUS_47K_UP |   \
 516                                 PAD_CTL_SPEED_MED |     \
 517                                 PAD_CTL_DSE_40ohm |     \
 518                                 PAD_CTL_SRE_FAST)
 519
 520 static const iomux_v3_cfg_t mmc0_pads[] = {
 521         MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 522         MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 523         MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 524         MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 525         MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 526         MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 527         /* SD1 CD */
 528         MX6_PAD_NAND_CE1_B__GPIO4_IO14 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 529 };
 530
 531 #ifdef CONFIG_TX6_EMMC
 532 static const iomux_v3_cfg_t mmc1_pads[] = {
 533         MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 534         MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 535         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 536         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 537         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 538         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 539         /* eMMC RESET */
 540         MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
 541                                                 PAD_CTL_DSE_40ohm),
 542 };
 543 #endif
 544
 545 static struct tx6_esdhc_cfg {
 546         const iomux_v3_cfg_t *pads;
 547         int num_pads;
 548         enum mxc_clock clkid;
 549         struct fsl_esdhc_cfg cfg;
 550         int cd_gpio;
 551 } tx6ul_esdhc_cfg[] = {
 552 #ifdef CONFIG_TX6_EMMC
 553         {
 554                 .pads = mmc1_pads,
 555                 .num_pads = ARRAY_SIZE(mmc1_pads),
 556                 .clkid = MXC_ESDHC2_CLK,
 557                 .cfg = {
 558                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
 559                         .max_bus_width = 4,
 560                 },
 561                 .cd_gpio = -EINVAL,
 562         },
 563 #endif
 564         {
 565                 .pads = mmc0_pads,
 566                 .num_pads = ARRAY_SIZE(mmc0_pads),
 567                 .clkid = MXC_ESDHC_CLK,
 568                 .cfg = {
 569                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
 570                         .max_bus_width = 4,
 571                 },
 572                 .cd_gpio = TX6UL_SD1_CD_GPIO,
 573         },
 574 };
 575
 576 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 577 {
 578         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
 579 }
 580
 581 int board_mmc_getcd(struct mmc *mmc)
 582 {
 583         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
 584
 585         if (cfg->cd_gpio < 0)
 586                 return 1;
 587
 588         debug("SD card %d is %spresent (GPIO %d)\n",
 589                 cfg - tx6ul_esdhc_cfg,
 590                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
 591                 cfg->cd_gpio);
 592         return !gpio_get_value(cfg->cd_gpio);
 593 }
 594
 595 int board_mmc_init(bd_t *bis)
 596 {
 597         int i;
 598
 599         debug("%s@%d: \n", __func__, __LINE__);
 600
 601 #ifndef CONFIG_ENV_IS_IN_MMC
 602         if (!(gd->flags & GD_FLG_ENV_READY)) {
 603                 printf("deferred ...");
 604                 return 0;
 605         }
 606 #endif
 607         for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) {
 608                 struct mmc *mmc;
 609                 struct tx6_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
 610                 int ret;
 611
 612                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
 613                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
 614
 615                 if (cfg->cd_gpio >= 0) {
 616                         ret = gpio_request_one(cfg->cd_gpio,
 617                                         GPIOFLAG_INPUT, "MMC CD");
 618                         if (ret) {
 619                                 printf("Error %d requesting GPIO%d_%d\n",
 620                                         ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 621                                 continue;
 622                         }
 623                 }
 624
 625                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 626                 fsl_esdhc_initialize(bis, &cfg->cfg);
 627
 628                 mmc = find_mmc_device(i);
 629                 if (mmc == NULL)
 630                         continue;
 631                 if (board_mmc_getcd(mmc))
 632                         mmc_init(mmc);
 633         }
 634         return 0;
 635 }
 636 #endif /* CONFIG_FSL_ESDHC */
 637
 638 enum {
 639         LED_STATE_INIT = -1,
 640         LED_STATE_OFF,
 641         LED_STATE_ON,
 642         LED_STATE_ERR,
 643 };
 644
 645 static inline int calc_blink_rate(void)
 646 {
 647         if (!tx6_temp_check_enabled)
 648                 return CONFIG_SYS_HZ;
 649
 650         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
 651                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
 652                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
 653 }
 654
 655 void show_activity(int arg)
 656 {
 657         static int led_state = LED_STATE_INIT;
 658         static int blink_rate;
 659         static ulong last;
 660         int ret;
 661
 662         switch (led_state) {
 663         case LED_STATE_ERR:
 664                 return;
 665
 666         case LED_STATE_INIT:
 667                 last = get_timer(0);
 668                 ret = gpio_set_value(TX6UL_LED_GPIO, 1);
 669                 if (ret)
 670                         led_state = LED_STATE_ERR;
 671                 else
 672                         led_state = LED_STATE_ON;
 673                 blink_rate = calc_blink_rate();
 674                 break;
 675
 676         case LED_STATE_ON:
 677         case LED_STATE_OFF:
 678                 if (get_timer(last) > blink_rate) {
 679                         blink_rate = calc_blink_rate();
 680                         last = get_timer_masked();
 681                         if (led_state == LED_STATE_ON) {
 682                                 gpio_set_value(TX6UL_LED_GPIO, 0);
 683                         } else {
 684                                 gpio_set_value(TX6UL_LED_GPIO, 1);
 685                         }
 686                         led_state = 1 - led_state;
 687                 }
 688                 break;
 689         }
 690 }
 691
 692 static const iomux_v3_cfg_t stk5_pads[] = {
 693         /* SW controlled LED on STK5 baseboard */
 694         MX6_PAD_SNVS_TAMPER9__GPIO5_IO09,
 695
 696         /* I2C bus on DIMM pins 40/41 */
 697         MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
 698         MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
 699
 700         /* TSC200x PEN IRQ */
 701         MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL),
 702
 703         /* EDT-FT5x06 Polytouch panel */
 704         MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* IRQ */
 705         MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* RESET */
 706         MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* WAKE */
 707
 708         /* USBH1 */
 709         MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
 710         MX6_PAD_GPIO1_IO03__USB_OTG2_OC | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
 711
 712         /* USBOTG */
 713         MX6_PAD_UART3_CTS_B__GPIO1_IO26 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
 714         MX6_PAD_UART3_RTS_B__GPIO1_IO27 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
 715 };
 716
 717 static const struct gpio stk5_gpios[] = {
 718         { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 719
 720         { IMX_GPIO_NR(1, 27), GPIOFLAG_INPUT, "USBOTG OC", },
 721         { IMX_GPIO_NR(1, 26), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 722 };
 723
 724 #ifdef CONFIG_LCD
 725 vidinfo_t panel_info = {
 726         /* set to max. size supported by SoC */
 727         .vl_col = 4096,
 728         .vl_row = 1024,
 729
 730         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 731 };
 732
 733 static struct fb_videomode tx6_fb_modes[] = {
 734 #ifndef CONFIG_SYS_LVDS_IF
 735         {
 736                 /* Standard VGA timing */
 737                 .name           = "VGA",
 738                 .refresh        = 60,
 739                 .xres           = 640,
 740                 .yres           = 480,
 741                 .pixclock       = KHZ2PICOS(25175),
 742                 .left_margin    = 48,
 743                 .hsync_len      = 96,
 744                 .right_margin   = 16,
 745                 .upper_margin   = 31,
 746                 .vsync_len      = 2,
 747                 .lower_margin   = 12,
 748                 .sync           = FB_SYNC_CLK_LAT_FALL,
 749         },
 750         {
 751                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 752                  * DE high active, 115.2 mm x 86.4 mm display area
 753                  * VGA compatible timing
 754                  */
 755                 .name           = "ETV570",
 756                 .refresh        = 60,
 757                 .xres           = 640,
 758                 .yres           = 480,
 759                 .pixclock       = KHZ2PICOS(25175),
 760                 .left_margin    = 114,
 761                 .hsync_len      = 30,
 762                 .right_margin   = 16,
 763                 .upper_margin   = 32,
 764                 .vsync_len      = 3,
 765                 .lower_margin   = 10,
 766                 .sync           = FB_SYNC_CLK_LAT_FALL,
 767         },
 768         {
 769                 /* Emerging ET0350G0DH6 320 x 240 display.
 770                  * 70.08 mm x 52.56 mm display area.
 771                  */
 772                 .name           = "ET0350",
 773                 .refresh        = 60,
 774                 .xres           = 320,
 775                 .yres           = 240,
 776                 .pixclock       = KHZ2PICOS(6500),
 777                 .left_margin    = 68 - 34,
 778                 .hsync_len      = 34,
 779                 .right_margin   = 20,
 780                 .upper_margin   = 18 - 3,
 781                 .vsync_len      = 3,
 782                 .lower_margin   = 4,
 783                 .sync           = FB_SYNC_CLK_LAT_FALL,
 784         },
 785         {
 786                 /* Emerging ET0430G0DH6 480 x 272 display.
 787                  * 95.04 mm x 53.856 mm display area.
 788                  */
 789                 .name           = "ET0430",
 790                 .refresh        = 60,
 791                 .xres           = 480,
 792                 .yres           = 272,
 793                 .pixclock       = KHZ2PICOS(9000),
 794                 .left_margin    = 2,
 795                 .hsync_len      = 41,
 796                 .right_margin   = 2,
 797                 .upper_margin   = 2,
 798                 .vsync_len      = 10,
 799                 .lower_margin   = 2,
 800         },
 801         {
 802                 /* Emerging ET0500G0DH6 800 x 480 display.
 803                  * 109.6 mm x 66.4 mm display area.
 804                  */
 805                 .name           = "ET0500",
 806                 .refresh        = 60,
 807                 .xres           = 800,
 808                 .yres           = 480,
 809                 .pixclock       = KHZ2PICOS(33260),
 810                 .left_margin    = 216 - 128,
 811                 .hsync_len      = 128,
 812                 .right_margin   = 1056 - 800 - 216,
 813                 .upper_margin   = 35 - 2,
 814                 .vsync_len      = 2,
 815                 .lower_margin   = 525 - 480 - 35,
 816                 .sync           = FB_SYNC_CLK_LAT_FALL,
 817         },
 818         {
 819                 /* Emerging ETQ570G0DH6 320 x 240 display.
 820                  * 115.2 mm x 86.4 mm display area.
 821                  */
 822                 .name           = "ETQ570",
 823                 .refresh        = 60,
 824                 .xres           = 320,
 825                 .yres           = 240,
 826                 .pixclock       = KHZ2PICOS(6400),
 827                 .left_margin    = 38,
 828                 .hsync_len      = 30,
 829                 .right_margin   = 30,
 830                 .upper_margin   = 16, /* 15 according to datasheet */
 831                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 832                 .lower_margin   = 4, /* 4.5 according to datasheet */
 833                 .sync           = FB_SYNC_CLK_LAT_FALL,
 834         },
 835         {
 836                 /* Emerging ET0700G0DH6 800 x 480 display.
 837                  * 152.4 mm x 91.44 mm display area.
 838                  */
 839                 .name           = "ET0700",
 840                 .refresh        = 60,
 841                 .xres           = 800,
 842                 .yres           = 480,
 843                 .pixclock       = KHZ2PICOS(33260),
 844                 .left_margin    = 216 - 128,
 845                 .hsync_len      = 128,
 846                 .right_margin   = 1056 - 800 - 216,
 847                 .upper_margin   = 35 - 2,
 848                 .vsync_len      = 2,
 849                 .lower_margin   = 525 - 480 - 35,
 850                 .sync           = FB_SYNC_CLK_LAT_FALL,
 851         },
 852         {
 853                 /* Emerging ET070001DM6 800 x 480 display.
 854                  * 152.4 mm x 91.44 mm display area.
 855                  */
 856                 .name           = "ET070001DM6",
 857                 .refresh        = 60,
 858                 .xres           = 800,
 859                 .yres           = 480,
 860                 .pixclock       = KHZ2PICOS(33260),
 861                 .left_margin    = 216 - 128,
 862                 .hsync_len      = 128,
 863                 .right_margin   = 1056 - 800 - 216,
 864                 .upper_margin   = 35 - 2,
 865                 .vsync_len      = 2,
 866                 .lower_margin   = 525 - 480 - 35,
 867                 .sync           = 0,
 868         },
 869 #else
 870         {
 871                 /* HannStar HSD100PXN1
 872                  * 202.7m mm x 152.06 mm display area.
 873                  */
 874                 .name           = "HSD100PXN1",
 875                 .refresh        = 60,
 876                 .xres           = 1024,
 877                 .yres           = 768,
 878                 .pixclock       = KHZ2PICOS(65000),
 879                 .left_margin    = 0,
 880                 .hsync_len      = 0,
 881                 .right_margin   = 320,
 882                 .upper_margin   = 0,
 883                 .vsync_len      = 0,
 884                 .lower_margin   = 38,
 885                 .sync           = FB_SYNC_CLK_LAT_FALL,
 886         },
 887 #endif
 888         {
 889                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 890                 .refresh        = 60,
 891                 .left_margin    = 48,
 892                 .hsync_len      = 96,
 893                 .right_margin   = 16,
 894                 .upper_margin   = 31,
 895                 .vsync_len      = 2,
 896                 .lower_margin   = 12,
 897                 .sync           = FB_SYNC_CLK_LAT_FALL,
 898         },
 899 };
 900
 901 static int lcd_enabled = 1;
 902 static int lcd_bl_polarity;
 903
 904 static int lcd_backlight_polarity(void)
 905 {
 906         return lcd_bl_polarity;
 907 }
 908
 909 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 910 #ifdef CONFIG_LCD
 911         /* LCD RESET */
 912         MX6_PAD_LCD_RESET__GPIO3_IO04 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
 913         /* LCD POWER_ENABLE */
 914         MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
 915         /* LCD Backlight (PWM) */
 916         MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
 917         /* Display */
 918         MX6_PAD_LCD_DATA00__LCDIF_DATA00,
 919         MX6_PAD_LCD_DATA01__LCDIF_DATA01,
 920         MX6_PAD_LCD_DATA02__LCDIF_DATA02,
 921         MX6_PAD_LCD_DATA03__LCDIF_DATA03,
 922         MX6_PAD_LCD_DATA04__LCDIF_DATA04,
 923         MX6_PAD_LCD_DATA05__LCDIF_DATA05,
 924         MX6_PAD_LCD_DATA06__LCDIF_DATA06,
 925         MX6_PAD_LCD_DATA07__LCDIF_DATA07,
 926         MX6_PAD_LCD_DATA08__LCDIF_DATA08,
 927         MX6_PAD_LCD_DATA09__LCDIF_DATA09,
 928         MX6_PAD_LCD_DATA10__LCDIF_DATA10,
 929         MX6_PAD_LCD_DATA11__LCDIF_DATA11,
 930         MX6_PAD_LCD_DATA12__LCDIF_DATA12,
 931         MX6_PAD_LCD_DATA13__LCDIF_DATA13,
 932         MX6_PAD_LCD_DATA14__LCDIF_DATA14,
 933         MX6_PAD_LCD_DATA15__LCDIF_DATA15,
 934         MX6_PAD_LCD_DATA16__LCDIF_DATA16,
 935         MX6_PAD_LCD_DATA17__LCDIF_DATA17,
 936         MX6_PAD_LCD_DATA18__LCDIF_DATA18,
 937         MX6_PAD_LCD_DATA19__LCDIF_DATA19,
 938         MX6_PAD_LCD_DATA20__LCDIF_DATA20,
 939         MX6_PAD_LCD_DATA21__LCDIF_DATA21,
 940         MX6_PAD_LCD_DATA22__LCDIF_DATA22,
 941         MX6_PAD_LCD_DATA23__LCDIF_DATA23,
 942         MX6_PAD_LCD_HSYNC__LCDIF_HSYNC, /* HSYNC */
 943         MX6_PAD_LCD_VSYNC__LCDIF_VSYNC, /* VSYNC */
 944         MX6_PAD_LCD_ENABLE__LCDIF_ENABLE, /* OE_ACD */
 945         MX6_PAD_LCD_CLK__LCDIF_CLK, /* LSCLK */
 946 #endif
 947 };
 948
 949 static const struct gpio stk5_lcd_gpios[] = {
 950         { TX6UL_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
 951         { TX6UL_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
 952         { TX6UL_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 953 };
 954
 955 /* run with valid env from NAND/eMMC */
 956 void lcd_enable(void)
 957 {
 958         /* HACK ALERT:
 959          * global variable from common/lcd.c
 960          * Set to 0 here to prevent messages from going to LCD
 961          * rather than serial console
 962          */
 963         lcd_is_enabled = 0;
 964
 965         if (lcd_enabled) {
 966                 karo_load_splashimage(1);
 967
 968                 debug("Switching LCD on\n");
 969                 gpio_set_value(TX6UL_LCD_PWR_GPIO, 1);
 970                 udelay(100);
 971                 gpio_set_value(TX6UL_LCD_RST_GPIO, 1);
 972                 udelay(300000);
 973                 gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
 974                         lcd_backlight_polarity());
 975         }
 976 }
 977
 978 static void lcd_disable(void)
 979 {
 980         if (lcd_enabled) {
 981                 printf("Disabling LCD\n");
 982                 panel_info.vl_row = 0;
 983                 lcd_enabled = 0;
 984         }
 985 }
 986
 987 void lcd_ctrl_init(void *lcdbase)
 988 {
 989         int color_depth = 24;
 990         const char *video_mode = karo_get_vmode(getenv("video_mode"));
 991         const char *vm;
 992         unsigned long val;
 993         int refresh = 60;
 994         struct fb_videomode *p = &tx6_fb_modes[0];
 995         struct fb_videomode fb_mode;
 996         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 997
 998         if (!lcd_enabled) {
 999                 debug("LCD disabled\n");
1000                 return;
1001         }
1002
1003         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1004                 lcd_disable();
1005                 setenv("splashimage", NULL);
1006                 return;
1007         }
1008
1009         karo_fdt_move_fdt();
1010         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1011
1012         if (video_mode == NULL) {
1013                 lcd_disable();
1014                 return;
1015         }
1016         vm = video_mode;
1017         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1018                 p = &fb_mode;
1019                 debug("Using video mode from FDT\n");
1020                 vm += strlen(vm);
1021                 if (fb_mode.xres > panel_info.vl_col ||
1022                         fb_mode.yres > panel_info.vl_row) {
1023                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1024                                 fb_mode.xres, fb_mode.yres,
1025                                 panel_info.vl_col, panel_info.vl_row);
1026                         lcd_enabled = 0;
1027                         return;
1028                 }
1029         }
1030         if (p->name != NULL)
1031                 debug("Trying compiled-in video modes\n");
1032         while (p->name != NULL) {
1033                 if (strcmp(p->name, vm) == 0) {
1034                         debug("Using video mode: '%s'\n", p->name);
1035                         vm += strlen(vm);
1036                         break;
1037                 }
1038                 p++;
1039         }
1040         if (*vm != '\0')
1041                 debug("Trying to decode video_mode: '%s'\n", vm);
1042         while (*vm != '\0') {
1043                 if (*vm >= '0' && *vm <= '9') {
1044                         char *end;
1045
1046                         val = simple_strtoul(vm, &end, 0);
1047                         if (end > vm) {
1048                                 if (!xres_set) {
1049                                         if (val > panel_info.vl_col)
1050                                                 val = panel_info.vl_col;
1051                                         p->xres = val;
1052                                         panel_info.vl_col = val;
1053                                         xres_set = 1;
1054                                 } else if (!yres_set) {
1055                                         if (val > panel_info.vl_row)
1056                                                 val = panel_info.vl_row;
1057                                         p->yres = val;
1058                                         panel_info.vl_row = val;
1059                                         yres_set = 1;
1060                                 } else if (!bpp_set) {
1061                                         switch (val) {
1062                                         case 8:
1063                                         case 16:
1064                                         case 18:
1065                                         case 24:
1066                                         case 32:
1067                                                 color_depth = val;
1068                                                 break;
1069
1070                                         default:
1071                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1072                                                         end - vm, vm, color_depth);
1073                                         }
1074                                         bpp_set = 1;
1075                                 } else if (!refresh_set) {
1076                                         refresh = val;
1077                                         refresh_set = 1;
1078                                 }
1079                         }
1080                         vm = end;
1081                 }
1082                 switch (*vm) {
1083                 case '@':
1084                         bpp_set = 1;
1085                         /* fallthru */
1086                 case '-':
1087                         yres_set = 1;
1088                         /* fallthru */
1089                 case 'x':
1090                         xres_set = 1;
1091                         /* fallthru */
1092                 case 'M':
1093                 case 'R':
1094                         vm++;
1095                         break;
1096
1097                 default:
1098                         if (*vm != '\0')
1099                                 vm++;
1100                 }
1101         }
1102         if (p->xres == 0 || p->yres == 0) {
1103                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1104                 lcd_enabled = 0;
1105                 printf("Supported video modes are:");
1106                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1107                         printf(" %s", p->name);
1108                 }
1109                 printf("\n");
1110                 return;
1111         }
1112         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1113                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1114                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1115                 lcd_enabled = 0;
1116                 return;
1117         }
1118         panel_info.vl_col = p->xres;
1119         panel_info.vl_row = p->yres;
1120
1121         switch (color_depth) {
1122         case 8:
1123                 panel_info.vl_bpix = LCD_COLOR8;
1124                 break;
1125         case 16:
1126                 panel_info.vl_bpix = LCD_COLOR16;
1127                 break;
1128         default:
1129                 panel_info.vl_bpix = LCD_COLOR32;
1130         }
1131
1132         p->pixclock = KHZ2PICOS(refresh *
1133                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1134                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1135                                 1000);
1136         debug("Pixel clock set to %lu.%03lu MHz\n",
1137                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1138
1139         if (p != &fb_mode) {
1140                 int ret;
1141
1142                 debug("Creating new display-timing node from '%s'\n",
1143                         video_mode);
1144                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1145                 if (ret)
1146                         printf("Failed to create new display-timing node from '%s': %d\n",
1147                                 video_mode, ret);
1148         }
1149
1150         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1151         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1152                                         ARRAY_SIZE(stk5_lcd_pads));
1153
1154         debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
1155                 color_depth, refresh);
1156
1157         if (karo_load_splashimage(0) == 0) {
1158                 char vmode[128];
1159
1160                 /* setup env variable for mxsfb display driver */
1161                 snprintf(vmode, sizeof(vmode),
1162                         "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
1163                         p->xres, p->yres, p->left_margin, p->right_margin,
1164                         p->upper_margin, p->lower_margin, p->hsync_len,
1165                         p->vsync_len, p->sync, p->pixclock, color_depth);
1166                 setenv("videomode", vmode);
1167
1168                 debug("Initializing LCD controller\n");
1169                 lcdif_clk_enable();
1170                 video_hw_init();
1171                 setenv("videomode", NULL);
1172         } else {
1173                 debug("Skipping initialization of LCD controller\n");
1174         }
1175 }
1176 #else
1177 #define lcd_enabled 0
1178 #endif /* CONFIG_LCD */
1179
1180 #ifndef CONFIG_ENV_IS_IN_MMC
1181 static void tx6_mmc_init(void)
1182 {
1183         puts("MMC:   ");
1184         if (board_mmc_init(gd->bd) < 0)
1185                 cpu_mmc_init(gd->bd);
1186         print_mmc_devices(',');
1187 }
1188 #else
1189 static inline void tx6_mmc_init(void)
1190 {
1191 }
1192 #endif
1193
1194 static void stk5_board_init(void)
1195 {
1196         int ret;
1197
1198         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1199         if (ret < 0) {
1200                 printf("Failed to request stk5_gpios: %d\n", ret);
1201                 return;
1202         }
1203         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1204         debug("%s@%d: \n", __func__, __LINE__);
1205 }
1206
1207 static void stk5v3_board_init(void)
1208 {
1209         debug("%s@%d: \n", __func__, __LINE__);
1210         stk5_board_init();
1211         debug("%s@%d: \n", __func__, __LINE__);
1212         tx6_mmc_init();
1213 }
1214
1215 static void stk5v5_board_init(void)
1216 {
1217         int ret;
1218
1219         stk5_board_init();
1220         tx6_mmc_init();
1221
1222         ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
1223                         "Flexcan Transceiver");
1224         if (ret) {
1225                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1226                 return;
1227         }
1228
1229         imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 |
1230                         MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL));
1231 }
1232
1233 static void tx6ul_set_cpu_clock(void)
1234 {
1235         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1236
1237         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1238                 return;
1239
1240         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1241                 printf("%s detected; skipping cpu clock change\n",
1242                         (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1243                 return;
1244         }
1245         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1246                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1247                 printf("CPU clock set to %lu.%03lu MHz\n",
1248                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1249         } else {
1250                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1251         }
1252 }
1253
1254 int board_late_init(void)
1255 {
1256         const char *baseboard;
1257
1258         debug("%s@%d: \n", __func__, __LINE__);
1259
1260         env_cleanup();
1261
1262         if (tx6_temp_check_enabled)
1263                 check_cpu_temperature(1);
1264
1265         tx6ul_set_cpu_clock();
1266
1267         if (had_ctrlc())
1268                 setenv_ulong("safeboot", 1);
1269         else if (wrsr & WRSR_TOUT)
1270                 setenv_ulong("wdreset", 1);
1271         else
1272                 karo_fdt_move_fdt();
1273
1274         baseboard = getenv("baseboard");
1275         if (!baseboard)
1276                 goto exit;
1277
1278         printf("Baseboard: %s\n", baseboard);
1279
1280         if (strncmp(baseboard, "stk5", 4) == 0) {
1281                 if ((strlen(baseboard) == 4) ||
1282                         strcmp(baseboard, "stk5-v3") == 0) {
1283                         stk5v3_board_init();
1284                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1285                         const char *otg_mode = getenv("otg_mode");
1286
1287                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1288                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1289                                         otg_mode, baseboard);
1290                                 setenv("otg_mode", "none");
1291                         }
1292                         stk5v5_board_init();
1293                 } else {
1294                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1295                                 baseboard + 4);
1296                 }
1297         } else if (strncmp(baseboard, "ulmb-", 5) == 0) {
1298                         const char *otg_mode = getenv("otg_mode");
1299
1300                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1301                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1302                                         otg_mode, baseboard);
1303                                 setenv("otg_mode", "none");
1304                         }
1305                         stk5_board_init();
1306         } else {
1307                 printf("WARNING: Unsupported baseboard: '%s'\n",
1308                         baseboard);
1309                 if (!had_ctrlc())
1310                         return -EINVAL;
1311         }
1312
1313 exit:
1314         debug("%s@%d: \n", __func__, __LINE__);
1315
1316         clear_ctrlc();
1317         return 0;
1318 }
1319
1320 #ifdef CONFIG_FEC_MXC
1321
1322 #ifndef ETH_ALEN
1323 #define ETH_ALEN 6
1324 #endif
1325
1326 static void tx6_init_mac(void)
1327 {
1328         u8 mac[ETH_ALEN];
1329         const char *baseboard = getenv("baseboard");
1330
1331         imx_get_mac_from_fuse(0, mac);
1332         if (!is_valid_ethaddr(mac)) {
1333                 printf("No valid MAC address programmed\n");
1334                 return;
1335         }
1336         printf("MAC addr from fuse: %pM\n", mac);
1337         if (!getenv("ethaddr"))
1338                 eth_setenv_enetaddr("ethaddr", mac);
1339
1340         if (!baseboard || strncmp(baseboard, "stk5", 4) == 0) {
1341                 setenv("eth1addr", NULL);
1342                 return;
1343         }
1344         if (getenv("eth1addr"))
1345                 return;
1346         imx_get_mac_from_fuse(1, mac);
1347         eth_setenv_enetaddr("eth1addr", mac);
1348 }
1349
1350 int board_eth_init(bd_t *bis)
1351 {
1352         int ret;
1353
1354         tx6_init_mac();
1355
1356         /* delay at least 21ms for the PHY internal POR signal to deassert */
1357         udelay(22000);
1358
1359         imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads,
1360                                         ARRAY_SIZE(tx6ul_enet1_pads));
1361
1362         /* Deassert RESET to the external phys */
1363         gpio_set_value(TX6UL_FEC_RST_GPIO, 1);
1364
1365         if (getenv("ethaddr")) {
1366                 ret = fecmxc_initialize_multi(bis, 0, 0, ENET_BASE_ADDR);
1367                 if (ret) {
1368                         printf("failed to initialize FEC0: %d\n", ret);
1369                         return ret;
1370                 }
1371         }
1372         if (getenv("eth1addr")) {
1373                 ret = gpio_request_array(tx6ul_fec2_gpios,
1374                                         ARRAY_SIZE(tx6ul_fec2_gpios));
1375                 if (ret < 0) {
1376                         printf("Failed to request tx6ul_fec2_gpios: %d\n", ret);
1377                 }
1378                 imx_iomux_v3_setup_multiple_pads(tx6ul_enet2_pads,
1379                                                 ARRAY_SIZE(tx6ul_enet2_pads));
1380
1381                 writel(0x00100000, 0x020c80e4); /* assert ENET2_125M_EN */
1382
1383                 /* Minimum PHY reset duration */
1384                 udelay(100);
1385                 gpio_set_value(TX6UL_FEC2_RST_GPIO, 1);
1386                 /* Wait for PHY internal POR to finish */
1387                 udelay(22000);
1388
1389                 ret = fecmxc_initialize_multi(bis, 1, 2, ENET2_BASE_ADDR);
1390                 if (ret) {
1391                         printf("failed to initialize FEC1: %d\n", ret);
1392                         return ret;
1393                 }
1394         }
1395         return 0;
1396 }
1397 #endif /* CONFIG_FEC_MXC */
1398
1399 #ifdef CONFIG_SERIAL_TAG
1400 void get_board_serial(struct tag_serialnr *serialnr)
1401 {
1402         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1403         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1404
1405         serialnr->low = readl(&fuse->cfg0);
1406         serialnr->high = readl(&fuse->cfg1);
1407 }
1408 #endif
1409
1410 #if defined(CONFIG_OF_BOARD_SETUP)
1411 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1412 #include <jffs2/jffs2.h>
1413 #include <mtd_node.h>
1414 static struct node_info nodes[] = {
1415         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1416 };
1417 #else
1418 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1419 #endif
1420
1421 static const char *tx6_touchpanels[] = {
1422         "ti,tsc2007",
1423         "edt,edt-ft5x06",
1424         "eeti,egalax_ts",
1425 };
1426
1427 int ft_board_setup(void *blob, bd_t *bd)
1428 {
1429         const char *baseboard = getenv("baseboard");
1430         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1431         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1432         int ret;
1433
1434         ret = fdt_increase_size(blob, 4096);
1435         if (ret) {
1436                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1437                 return ret;
1438         }
1439         if (stk5_v5)
1440                 karo_fdt_enable_node(blob, "stk5led", 0);
1441
1442         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1443
1444         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1445                                 ARRAY_SIZE(tx6_touchpanels));
1446         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1447         karo_fdt_fixup_flexcan(blob, stk5_v5);
1448
1449         karo_fdt_update_fb_mode(blob, video_mode);
1450
1451         return 0;
1452 }
1453 #endif /* CONFIG_OF_BOARD_SETUP */