board/karo/tx6/tx6ul.c

   1 /*
   2  * Copyright (C) 2015 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  *
   6  */
   7 #include <common.h>
   8 #include <errno.h>
   9 #include <libfdt.h>
  10 #include <fdt_support.h>
  11 #include <lcd.h>
  12 #include <netdev.h>
  13 #include <mmc.h>
  14 #include <fsl_esdhc.h>
  15 #include <video_fb.h>
  16 #include <ipu.h>
  17 #include <mxcfb.h>
  18 #include <i2c.h>
  19 #include <linux/fb.h>
  20 #include <asm/io.h>
  21 #include <asm/gpio.h>
  22 #include <asm/arch/mx6-pins.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/hab.h>
  25 #include <asm/arch/imx-regs.h>
  26 #include <asm/arch/crm_regs.h>
  27 #include <asm/arch/sys_proto.h>
  28
  29 #include "../common/karo.h"
  30 #include "pmic.h"
  31
  32 #define __data __attribute__((section(".data")))
  33
  34 #define TX6UL_FEC_RST_GPIO              IMX_GPIO_NR(5, 6)
  35 #define TX6UL_FEC_PWR_GPIO              IMX_GPIO_NR(5, 7)
  36 #define TX6UL_FEC_INT_GPIO              IMX_GPIO_NR(5, 5)
  37
  38 #define TX6UL_FEC2_RST_GPIO             IMX_GPIO_NR(4, 28)
  39 #define TX6UL_FEC2_INT_GPIO             IMX_GPIO_NR(4, 27)
  40
  41 #define TX6UL_LED_GPIO                  IMX_GPIO_NR(5, 9)
  42
  43 #define TX6UL_LCD_PWR_GPIO              IMX_GPIO_NR(5, 4)
  44 #define TX6UL_LCD_RST_GPIO              IMX_GPIO_NR(3, 4)
  45 #define TX6UL_LCD_BACKLIGHT_GPIO        IMX_GPIO_NR(4, 16)
  46
  47 #ifdef CONFIG_SYS_I2C_SOFT
  48 #define TX6UL_I2C1_SCL_GPIO             CONFIG_SOFT_I2C_GPIO_SCL
  49 #define TX6UL_I2C1_SDA_GPIO             CONFIG_SOFT_I2C_GPIO_SDA
  50 #endif
  51
  52 #define TX6UL_SD1_CD_GPIO               IMX_GPIO_NR(4, 14)
  53
  54 #ifdef CONFIG_MX6_TEMPERATURE_MIN
  55 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
  56 #else
  57 #define TEMPERATURE_MIN                 (-40)
  58 #endif
  59 #ifdef CONFIG_MX6_TEMPERATURE_HOT
  60 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
  61 #else
  62 #define TEMPERATURE_HOT                 80
  63 #endif
  64
  65 DECLARE_GLOBAL_DATA_PTR;
  66
  67 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  68
  69 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
  70 #ifdef CONFIG_SECURE_BOOT
  71 char __csf_data[0] __attribute__((section(".__csf_data")));
  72 #endif
  73
  74 #define TX6UL_DEFAULT_PAD_CTRL  MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |      \
  75                                         PAD_CTL_SPEED_MED |             \
  76                                         PAD_CTL_DSE_40ohm |             \
  77                                         PAD_CTL_SRE_FAST)
  78 #define TX6UL_I2C_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |       \
  79                                         PAD_CTL_ODE |                   \
  80                                         PAD_CTL_HYS |                   \
  81                                         PAD_CTL_SPEED_LOW |             \
  82                                         PAD_CTL_DSE_34ohm |             \
  83                                         PAD_CTL_SRE_FAST)
  84 #define TX6UL_ENET_PAD_CTRL     MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |       \
  85                                         PAD_CTL_DSE_120ohm |            \
  86                                         PAD_CTL_PUS_100K_UP |           \
  87                                         PAD_CTL_SRE_FAST)
  88 #define TX6UL_GPIO_OUT_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |        \
  89                                         PAD_CTL_DSE_60ohm |             \
  90                                         PAD_CTL_SRE_SLOW)
  91 #define TX6UL_GPIO_IN_PAD_CTRL  MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |        \
  92                                         PAD_CTL_PUS_47K_UP)
  93
  94
  95 static const iomux_v3_cfg_t const tx6ul_pads[] = {
  96         /* UART pads */
  97 #if CONFIG_MXC_UART_BASE == UART1_BASE
  98         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
  99         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
 100         MX6_PAD_UART1_RTS_B__UART1_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
 101         MX6_PAD_UART1_CTS_B__UART1_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
 102 #endif
 103 #if CONFIG_MXC_UART_BASE == UART2_BASE
 104         MX6_PAD_UART2_TX_DATA__UART2_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
 105         MX6_PAD_UART2_RX_DATA__UART2_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
 106         MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
 107         MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
 108 #endif
 109 #if CONFIG_MXC_UART_BASE == UART5_BASE
 110         MX6_PAD_GPIO1_IO04__UART5_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
 111         MX6_PAD_GPIO1_IO05__UART5_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
 112         MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
 113         MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
 114 #endif
 115         /* FEC PHY GPIO functions */
 116         MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY POWER */
 117         MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY RESET */
 118         MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | TX6UL_GPIO_IN_PAD_CTRL, /* PHY INT */
 119 };
 120
 121 static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = {
 122         /* FEC functions */
 123         MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm |
 124                                                      PAD_CTL_SPEED_LOW),
 125         MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
 126                                                       PAD_CTL_DSE_120ohm |
 127                                                       PAD_CTL_SPEED_LOW),
 128         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |
 129                                                      PAD_CTL_DSE_80ohm |
 130                                                      PAD_CTL_SRE_SLOW),
 131
 132         MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | TX6UL_ENET_PAD_CTRL,
 133         MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | TX6UL_ENET_PAD_CTRL,
 134         MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | TX6UL_ENET_PAD_CTRL,
 135         MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | TX6UL_ENET_PAD_CTRL,
 136         MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | TX6UL_ENET_PAD_CTRL,
 137         MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | TX6UL_ENET_PAD_CTRL,
 138         MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | TX6UL_ENET_PAD_CTRL,
 139 };
 140
 141 static const iomux_v3_cfg_t const tx6ul_enet2_pads[] = {
 142         MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |
 143                                                             PAD_CTL_DSE_80ohm |
 144                                                             PAD_CTL_SRE_SLOW),
 145         MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | TX6UL_ENET_PAD_CTRL,
 146         MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | TX6UL_ENET_PAD_CTRL,
 147         MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | TX6UL_ENET_PAD_CTRL,
 148         MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | TX6UL_ENET_PAD_CTRL,
 149         MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | TX6UL_ENET_PAD_CTRL,
 150         MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | TX6UL_ENET_PAD_CTRL,
 151         MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | TX6UL_ENET_PAD_CTRL,
 152 };
 153
 154 static const iomux_v3_cfg_t const tx6ul_i2c_pads[] = {
 155         /* internal I2C */
 156         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
 157                         TX6UL_I2C_PAD_CTRL, /* I2C SCL */
 158         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
 159                         TX6UL_I2C_PAD_CTRL, /* I2C SDA */
 160 };
 161
 162 static const struct gpio const tx6ul_gpios[] = {
 163 #ifdef CONFIG_SYS_I2C_SOFT
 164         /* These two entries are used to forcefully reinitialize the I2C bus */
 165         { TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
 166         { TX6UL_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
 167 #endif
 168         { TX6UL_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 169         { TX6UL_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 170         { TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
 171 };
 172
 173 static const struct gpio const tx6ul_fec2_gpios[] = {
 174         { TX6UL_FEC2_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC2 PHY RESET", },
 175         { TX6UL_FEC2_INT_GPIO, GPIOFLAG_INPUT, "FEC2 PHY INT", },
 176 };
 177
 178 #define GPIO_DR 0
 179 #define GPIO_DIR 4
 180 #define GPIO_PSR 8
 181
 182 /* run with default environment */
 183 #if defined(TX6UL_I2C1_SCL_GPIO) && defined(TX6UL_I2C1_SDA_GPIO)
 184 #define SCL_BANK        (TX6UL_I2C1_SCL_GPIO / 32)
 185 #define SDA_BANK        (TX6UL_I2C1_SDA_GPIO / 32)
 186 #define SCL_BIT         (1 << (TX6UL_I2C1_SCL_GPIO % 32))
 187 #define SDA_BIT         (1 << (TX6UL_I2C1_SDA_GPIO % 32))
 188
 189 static void * const gpio_ports[] = {
 190         (void *)GPIO1_BASE_ADDR,
 191         (void *)GPIO2_BASE_ADDR,
 192         (void *)GPIO3_BASE_ADDR,
 193         (void *)GPIO4_BASE_ADDR,
 194         (void *)GPIO5_BASE_ADDR,
 195 };
 196
 197 static void tx6ul_i2c_recover(void)
 198 {
 199         int i;
 200         int bad = 0;
 201         struct gpio_regs *scl_regs = gpio_ports[SCL_BANK];
 202         struct gpio_regs *sda_regs = gpio_ports[SDA_BANK];
 203
 204         if ((readl(&scl_regs->gpio_psr) & SCL_BIT) &&
 205             (readl(&sda_regs->gpio_psr) & SDA_BIT))
 206                 return;
 207
 208         debug("Clearing I2C bus\n");
 209         if (!(readl(&scl_regs->gpio_psr) & SCL_BIT)) {
 210                 printf("I2C SCL stuck LOW\n");
 211                 bad++;
 212
 213                 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
 214                 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
 215
 216                 imx_iomux_v3_setup_pad(MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 |
 217                                        MUX_CFG_SION | TX6UL_GPIO_OUT_PAD_CTRL);
 218         }
 219         if (!(readl(&sda_regs->gpio_psr) & SDA_BIT)) {
 220                 printf("I2C SDA stuck LOW\n");
 221                 bad++;
 222
 223                 clrbits_le32(&sda_regs->gpio_dir, SDA_BIT);
 224                 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
 225                 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
 226
 227                 udelay(5);
 228
 229                 for (i = 0; i < 18; i++) {
 230                         u32 reg = readl(&scl_regs->gpio_dr) ^ SCL_BIT;
 231
 232                         debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
 233                         writel(reg, &scl_regs->gpio_dr);
 234                         udelay(5);
 235                         if (reg & SCL_BIT) {
 236                                 if (readl(&sda_regs->gpio_psr) & SDA_BIT)
 237                                         break;
 238                                 if (!(readl(&scl_regs->gpio_psr) & SCL_BIT))
 239                                         break;
 240                                 break;
 241                         }
 242                 }
 243         }
 244         if (bad) {
 245                 bool scl = !!(readl(&scl_regs->gpio_psr) & SCL_BIT);
 246                 bool sda = !!(readl(&sda_regs->gpio_psr) & SDA_BIT);
 247
 248                 if (scl && sda) {
 249                         printf("I2C bus recovery succeeded\n");
 250                 } else {
 251                         printf("I2C bus recovery FAILED: SCL: %d SDA: %d\n",
 252                                scl, sda);
 253                 }
 254                 imx_iomux_v3_setup_multiple_pads(tx6ul_i2c_pads,
 255                                                  ARRAY_SIZE(tx6ul_i2c_pads));
 256         }
 257 }
 258 #else
 259 static inline void tx6ul_i2c_recover(void)
 260 {
 261 }
 262 #endif
 263
 264 /* placed in section '.data' to prevent overwriting relocation info
 265  * overlayed with bss
 266  */
 267 static u32 wrsr __data;
 268
 269 #define WRSR_POR                        (1 << 4)
 270 #define WRSR_TOUT                       (1 << 1)
 271 #define WRSR_SFTW                       (1 << 0)
 272
 273 static void print_reset_cause(void)
 274 {
 275         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 276         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 277         u32 srsr;
 278         char *dlm = "";
 279
 280         printf("Reset cause: ");
 281
 282         srsr = readl(&src_regs->srsr);
 283         wrsr = readw(wdt_base + 4);
 284
 285         if (wrsr & WRSR_POR) {
 286                 printf("%sPOR", dlm);
 287                 dlm = " | ";
 288         }
 289         if (srsr & 0x00004) {
 290                 printf("%sCSU", dlm);
 291                 dlm = " | ";
 292         }
 293         if (srsr & 0x00008) {
 294                 printf("%sIPP USER", dlm);
 295                 dlm = " | ";
 296         }
 297         if (srsr & 0x00010) {
 298                 if (wrsr & WRSR_SFTW) {
 299                         printf("%sSOFT", dlm);
 300                         dlm = " | ";
 301                 }
 302                 if (wrsr & WRSR_TOUT) {
 303                         printf("%sWDOG", dlm);
 304                         dlm = " | ";
 305                 }
 306         }
 307         if (srsr & 0x00020) {
 308                 printf("%sJTAG HIGH-Z", dlm);
 309                 dlm = " | ";
 310         }
 311         if (srsr & 0x00040) {
 312                 printf("%sJTAG SW", dlm);
 313                 dlm = " | ";
 314         }
 315         if (srsr & 0x10000) {
 316                 printf("%sWARM BOOT", dlm);
 317                 dlm = " | ";
 318         }
 319         if (dlm[0] == '\0')
 320                 printf("unknown");
 321
 322         printf("\n");
 323 }
 324
 325 #ifdef CONFIG_IMX6_THERMAL
 326 #include <thermal.h>
 327 #include <imx_thermal.h>
 328 #include <fuse.h>
 329
 330 static void print_temperature(void)
 331 {
 332         struct udevice *thermal_dev;
 333         int cpu_tmp, minc, maxc, ret;
 334         char const *grade_str;
 335         static u32 __data thermal_calib;
 336
 337         puts("Temperature: ");
 338         switch (get_cpu_temp_grade(&minc, &maxc)) {
 339         case TEMP_AUTOMOTIVE:
 340                 grade_str = "Automotive";
 341                 break;
 342         case TEMP_INDUSTRIAL:
 343                 grade_str = "Industrial";
 344                 break;
 345         case TEMP_EXTCOMMERCIAL:
 346                 grade_str = "Extended Commercial";
 347                 break;
 348         default:
 349                 grade_str = "Commercial";
 350         }
 351         printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
 352         ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
 353         if (ret == 0) {
 354                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
 355
 356                 if (ret == 0)
 357                         printf(" at %dC", cpu_tmp);
 358                 else
 359                         puts(" - failed to read sensor data");
 360         } else {
 361                 puts(" - no sensor device found");
 362         }
 363
 364         if (fuse_read(1, 6, &thermal_calib) == 0) {
 365                 printf(" - calibration data 0x%08x\n", thermal_calib);
 366         } else {
 367                 puts(" - Failed to read thermal calib fuse\n");
 368         }
 369 }
 370 #else
 371 static inline void print_temperature(void)
 372 {
 373 }
 374 #endif
 375
 376 int checkboard(void)
 377 {
 378         u32 cpurev = get_cpu_rev();
 379         char *cpu_str = "?";
 380
 381         if (is_cpu_type(MXC_CPU_MX6SL))
 382                 cpu_str = "SL";
 383         else if (is_cpu_type(MXC_CPU_MX6DL))
 384                 cpu_str = "DL";
 385         else if (is_cpu_type(MXC_CPU_MX6SOLO))
 386                 cpu_str = "SOLO";
 387         else if (is_cpu_type(MXC_CPU_MX6Q))
 388                 cpu_str = "Q";
 389         else if (is_cpu_type(MXC_CPU_MX6UL))
 390                 cpu_str = "UL";
 391         else if (is_cpu_type(MXC_CPU_MX6ULL))
 392                 cpu_str = "ULL";
 393
 394         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
 395                 cpu_str,
 396                 (cpurev & 0x000F0) >> 4,
 397                 (cpurev & 0x0000F) >> 0,
 398                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 399
 400         print_temperature();
 401         print_reset_cause();
 402 #ifdef CONFIG_MX6_TEMPERATURE_HOT
 403         check_cpu_temperature(1);
 404 #endif
 405         tx6ul_i2c_recover();
 406         return 0;
 407 }
 408
 409 /* serial port not initialized at this point */
 410 int board_early_init_f(void)
 411 {
 412         return 0;
 413 }
 414
 415 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 416 static bool tx6ul_temp_check_enabled = true;
 417 #else
 418 #define tx6ul_temp_check_enabled        0
 419 #endif
 420
 421 static inline u8 tx6ul_mem_suffix(void)
 422 {
 423         return '0' + CONFIG_SYS_SDRAM_CHIP_SIZE / 1024 * 2 +
 424                 IS_ENABLED(CONFIG_TX6_EMMC);
 425 }
 426
 427 #ifdef CONFIG_RN5T567
 428 /* PMIC settings */
 429 #define VDD_RTC_VAL             rn5t_mV_to_regval_rtc(3000)
 430 #define VDD_CORE_VAL            rn5t_mV_to_regval(1300)         /* DCDC1 */
 431 #define VDD_CORE_VAL_LP         rn5t_mV_to_regval(900)
 432 #define VDD_DDR_VAL             rn5t_mV_to_regval(1350)         /* DCDC3 */
 433 #define VDD_DDR_VAL_LP          rn5t_mV_to_regval(1350)
 434 #define VDD_IO_EXT_VAL          rn5t_mV_to_regval(3300)         /* DCDC4 */
 435 #define VDD_IO_EXT_VAL_LP       rn5t_mV_to_regval(3300)
 436 #define VDD_IO_INT_VAL          rn5t_mV_to_regval2(3300)        /* LDO1 */
 437 #define VDD_IO_INT_VAL_LP       rn5t_mV_to_regval2(3300)
 438 #define VDD_ADC_VAL             rn5t_mV_to_regval2(3300)        /* LDO2 */
 439 #define VDD_ADC_VAL_LP          rn5t_mV_to_regval2(3300)
 440 #define VDD_PMIC_VAL            rn5t_mV_to_regval2(2500)        /* LDO3 */
 441 #define VDD_PMIC_VAL_LP         rn5t_mV_to_regval2(2500)
 442 #define VDD_CSI_VAL             rn5t_mV_to_regval2(1800)        /* LDO4 */
 443 #define VDD_CSI_VAL_LP          rn5t_mV_to_regval2(1800)
 444
 445 static struct pmic_regs rn5t567_regs[] = {
 446         { RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, },
 447         { RN5T567_DC1DAC, VDD_CORE_VAL, },
 448         { RN5T567_DC3DAC, VDD_DDR_VAL, },
 449         { RN5T567_DC4DAC, VDD_IO_EXT_VAL, },
 450         { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
 451         { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
 452         { RN5T567_DC4DAC_SLP, VDD_IO_EXT_VAL_LP, },
 453         { RN5T567_DC1CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
 454         { RN5T567_DC2CTL, DCnCTL_DCnDIS, },
 455         { RN5T567_DC3CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
 456         { RN5T567_DC4CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
 457         { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
 458         { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
 459         { RN5T567_LDO1DAC, VDD_IO_INT_VAL, },
 460         { RN5T567_LDO2DAC, VDD_ADC_VAL, },
 461         { RN5T567_LDO3DAC, VDD_PMIC_VAL, },
 462         { RN5T567_LDO4DAC, VDD_CSI_VAL, },
 463         { RN5T567_LDOEN1, 0x0f, ~0x1f, },
 464         { RN5T567_LDOEN2, 0x10, ~0x30, },
 465         { RN5T567_LDODIS, 0x10, ~0x1f, },
 466         { RN5T567_INTPOL, 0, },
 467         { RN5T567_INTEN, 0x3, },
 468         { RN5T567_IREN, 0xf, },
 469         { RN5T567_EN_GPIR, 0, },
 470 };
 471
 472 static int pmic_addr = 0x33;
 473 #endif
 474
 475 int board_init(void)
 476 {
 477         int ret;
 478         u32 cpurev = get_cpu_rev();
 479         char f = '?';
 480
 481         if (is_cpu_type(MXC_CPU_MX6UL))
 482                 f = ((cpurev & 0xff) > 0x10) ? '5' : '0';
 483         else if (is_cpu_type(MXC_CPU_MX6ULL))
 484                 f = '8';
 485
 486         debug("%s@%d: cpurev=%08x\n", __func__, __LINE__, cpurev);
 487
 488         printf("Board: Ka-Ro TXUL-%c01%c\n", f, tx6ul_mem_suffix());
 489
 490         get_hab_status();
 491
 492         ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios));
 493         if (ret < 0)
 494                 printf("Failed to request tx6ul_gpios: %d\n", ret);
 495
 496         imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads));
 497
 498         /* Address of boot parameters */
 499         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 500         gd->bd->bi_arch_number = -1;
 501
 502         if (ctrlc() || (wrsr & WRSR_TOUT)) {
 503                 if (wrsr & WRSR_TOUT)
 504                         printf("WDOG RESET detected; Skipping PMIC setup\n");
 505                 else
 506                         printf("<CTRL-C> detected; safeboot enabled\n");
 507 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 508                 tx6ul_temp_check_enabled = false;
 509 #endif
 510                 return 0;
 511         }
 512
 513         ret = tx6_pmic_init(pmic_addr, rn5t567_regs, ARRAY_SIZE(rn5t567_regs));
 514         if (ret) {
 515                 printf("Failed to setup PMIC voltages: %d\n", ret);
 516                 hang();
 517         }
 518         return 0;
 519 }
 520
 521 int dram_init(void)
 522 {
 523         debug("%s@%d: \n", __func__, __LINE__);
 524
 525         /* dram_init must store complete ramsize in gd->ram_size */
 526         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 527                                     PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
 528         return 0;
 529 }
 530
 531 void dram_init_banksize(void)
 532 {
 533         debug("%s@%d: \n", __func__, __LINE__);
 534
 535         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 536         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 537                                                PHYS_SDRAM_1_SIZE);
 538 #if CONFIG_NR_DRAM_BANKS > 1
 539         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 540         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 541                                                PHYS_SDRAM_2_SIZE);
 542 #endif
 543 }
 544
 545 #ifdef  CONFIG_FSL_ESDHC
 546 #define TX6UL_SD_PAD_CTRL       MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |       \
 547                                         PAD_CTL_SPEED_MED |             \
 548                                         PAD_CTL_DSE_40ohm |             \
 549                                         PAD_CTL_SRE_FAST)
 550
 551 static const iomux_v3_cfg_t mmc0_pads[] = {
 552         MX6_PAD_SD1_CMD__USDHC1_CMD | TX6UL_SD_PAD_CTRL,
 553         MX6_PAD_SD1_CLK__USDHC1_CLK | TX6UL_SD_PAD_CTRL,
 554         MX6_PAD_SD1_DATA0__USDHC1_DATA0 | TX6UL_SD_PAD_CTRL,
 555         MX6_PAD_SD1_DATA1__USDHC1_DATA1 | TX6UL_SD_PAD_CTRL,
 556         MX6_PAD_SD1_DATA2__USDHC1_DATA2 | TX6UL_SD_PAD_CTRL,
 557         MX6_PAD_SD1_DATA3__USDHC1_DATA3 | TX6UL_SD_PAD_CTRL,
 558         /* SD1 CD */
 559         MX6_PAD_NAND_CE1_B__GPIO4_IO14 | TX6UL_SD_PAD_CTRL,
 560 };
 561
 562 #ifdef CONFIG_TX6_EMMC
 563 static const iomux_v3_cfg_t mmc1_pads[] = {
 564         MX6_PAD_NAND_WE_B__USDHC2_CMD | TX6UL_SD_PAD_CTRL,
 565         MX6_PAD_NAND_RE_B__USDHC2_CLK | TX6UL_SD_PAD_CTRL,
 566         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | TX6UL_SD_PAD_CTRL,
 567         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | TX6UL_SD_PAD_CTRL,
 568         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | TX6UL_SD_PAD_CTRL,
 569         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | TX6UL_SD_PAD_CTRL,
 570         /* eMMC RESET */
 571         MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
 572                                                         PAD_CTL_DSE_40ohm),
 573 };
 574 #endif
 575
 576 static struct tx6ul_esdhc_cfg {
 577         const iomux_v3_cfg_t *pads;
 578         int num_pads;
 579         enum mxc_clock clkid;
 580         struct fsl_esdhc_cfg cfg;
 581         int cd_gpio;
 582 } tx6ul_esdhc_cfg[] = {
 583 #ifdef CONFIG_TX6_EMMC
 584         {
 585                 .pads = mmc1_pads,
 586                 .num_pads = ARRAY_SIZE(mmc1_pads),
 587                 .clkid = MXC_ESDHC2_CLK,
 588                 .cfg = {
 589                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
 590                         .max_bus_width = 4,
 591                 },
 592                 .cd_gpio = -EINVAL,
 593         },
 594 #endif
 595         {
 596                 .pads = mmc0_pads,
 597                 .num_pads = ARRAY_SIZE(mmc0_pads),
 598                 .clkid = MXC_ESDHC_CLK,
 599                 .cfg = {
 600                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
 601                         .max_bus_width = 4,
 602                 },
 603                 .cd_gpio = TX6UL_SD1_CD_GPIO,
 604         },
 605 };
 606
 607 static inline struct tx6ul_esdhc_cfg *to_tx6ul_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 608 {
 609         return container_of(cfg, struct tx6ul_esdhc_cfg, cfg);
 610 }
 611
 612 int board_mmc_getcd(struct mmc *mmc)
 613 {
 614         struct tx6ul_esdhc_cfg *cfg = to_tx6ul_esdhc_cfg(mmc->priv);
 615
 616         if (cfg->cd_gpio < 0)
 617                 return 1;
 618
 619         debug("SD card %d is %spresent (GPIO %d)\n",
 620               cfg - tx6ul_esdhc_cfg,
 621               gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
 622               cfg->cd_gpio);
 623         return !gpio_get_value(cfg->cd_gpio);
 624 }
 625
 626 int board_mmc_init(bd_t *bis)
 627 {
 628         int i;
 629
 630         debug("%s@%d: \n", __func__, __LINE__);
 631
 632 #ifndef CONFIG_ENV_IS_IN_MMC
 633         if (!(gd->flags & GD_FLG_ENV_READY)) {
 634                 printf("deferred ...");
 635                 return 0;
 636         }
 637 #endif
 638         for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) {
 639                 struct mmc *mmc;
 640                 struct tx6ul_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
 641                 int ret;
 642
 643                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
 644                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
 645
 646                 if (cfg->cd_gpio >= 0) {
 647                         ret = gpio_request_one(cfg->cd_gpio,
 648                                                GPIOFLAG_INPUT, "MMC CD");
 649                         if (ret) {
 650                                 printf("Error %d requesting GPIO%d_%d\n",
 651                                        ret, cfg->cd_gpio / 32,
 652                                        cfg->cd_gpio % 32);
 653                                 continue;
 654                         }
 655                 }
 656
 657                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 658                 fsl_esdhc_initialize(bis, &cfg->cfg);
 659
 660                 mmc = find_mmc_device(i);
 661                 if (mmc == NULL)
 662                         continue;
 663                 if (board_mmc_getcd(mmc))
 664                         mmc_init(mmc);
 665         }
 666         return 0;
 667 }
 668 #endif /* CONFIG_FSL_ESDHC */
 669
 670 enum {
 671         LED_STATE_INIT = -1,
 672         LED_STATE_OFF,
 673         LED_STATE_ON,
 674         LED_STATE_ERR,
 675 };
 676
 677 static inline int calc_blink_rate(void)
 678 {
 679         if (!tx6ul_temp_check_enabled)
 680                 return CONFIG_SYS_HZ;
 681
 682         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
 683                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
 684                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
 685 }
 686
 687 void show_activity(int arg)
 688 {
 689         static int led_state = LED_STATE_INIT;
 690         static int blink_rate;
 691         static ulong last;
 692         int ret;
 693
 694         switch (led_state) {
 695         case LED_STATE_ERR:
 696                 return;
 697
 698         case LED_STATE_INIT:
 699                 last = get_timer(0);
 700                 ret = gpio_set_value(TX6UL_LED_GPIO, 1);
 701                 if (ret)
 702                         led_state = LED_STATE_ERR;
 703                 else
 704                         led_state = LED_STATE_ON;
 705                 blink_rate = calc_blink_rate();
 706                 break;
 707
 708         case LED_STATE_ON:
 709         case LED_STATE_OFF:
 710                 if (get_timer(last) > blink_rate) {
 711                         blink_rate = calc_blink_rate();
 712                         last = get_timer_masked();
 713                         if (led_state == LED_STATE_ON) {
 714                                 gpio_set_value(TX6UL_LED_GPIO, 0);
 715                         } else {
 716                                 gpio_set_value(TX6UL_LED_GPIO, 1);
 717                         }
 718                         led_state = 1 - led_state;
 719                 }
 720                 break;
 721         }
 722 }
 723
 724 static const iomux_v3_cfg_t stk5_jtag_pads[] = {
 725         MX6_PAD_JTAG_MOD__SJC_MOD | TX6UL_GPIO_IN_PAD_CTRL,
 726         MX6_PAD_JTAG_TCK__SJC_TCK | TX6UL_GPIO_IN_PAD_CTRL,
 727         MX6_PAD_JTAG_TRST_B__SJC_TRSTB | TX6UL_GPIO_IN_PAD_CTRL,
 728         MX6_PAD_JTAG_TDI__SJC_TDI | TX6UL_GPIO_IN_PAD_CTRL,
 729         MX6_PAD_JTAG_TDO__SJC_TDO | TX6UL_GPIO_OUT_PAD_CTRL,
 730         MX6_PAD_JTAG_TMS__SJC_TMS | TX6UL_GPIO_IN_PAD_CTRL,
 731 };
 732
 733 static const iomux_v3_cfg_t stk5_pads[] = {
 734         /* SW controlled LED on STK5 baseboard */
 735         MX6_PAD_SNVS_TAMPER9__GPIO5_IO09,
 736
 737         /* I2C bus on DIMM pins 40/41 */
 738         MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
 739         MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
 740
 741         /* TSC200x PEN IRQ */
 742         MX6_PAD_JTAG_TMS__GPIO1_IO11 | TX6UL_GPIO_IN_PAD_CTRL,
 743
 744         /* EDT-FT5x06 Polytouch panel */
 745         MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | TX6UL_GPIO_IN_PAD_CTRL, /* IRQ */
 746         MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 | TX6UL_GPIO_OUT_PAD_CTRL, /* RESET */
 747         MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | TX6UL_GPIO_OUT_PAD_CTRL, /* WAKE */
 748
 749         /* USBH1 */
 750         MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
 751         MX6_PAD_GPIO1_IO03__USB_OTG2_OC | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
 752
 753         /* USBOTG */
 754         MX6_PAD_UART3_CTS_B__GPIO1_IO26 | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
 755         MX6_PAD_UART3_RTS_B__GPIO1_IO27 | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
 756 };
 757
 758 static const struct gpio stk5_gpios[] = {
 759         { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 760
 761         { IMX_GPIO_NR(1, 27), GPIOFLAG_INPUT, "USBOTG OC", },
 762         { IMX_GPIO_NR(1, 26), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 763 };
 764
 765 static const iomux_v3_cfg_t tx_tester_pads[] = {
 766         /* SW controlled LEDs on TX-TESTER-V5 baseboard */
 767         MX6_PAD_SNVS_TAMPER4__GPIO5_IO04, /* red LED */
 768         MX6_PAD_SNVS_TAMPER9__GPIO5_IO09, /* yellow LED */
 769         MX6_PAD_SNVS_TAMPER8__GPIO5_IO08, /* green LED */
 770
 771         MX6_PAD_LCD_DATA04__GPIO3_IO09, /* IO_RESET */
 772
 773         /* I2C bus on DIMM pins 40/41 */
 774         MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
 775         MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
 776
 777         /* USBH1 */
 778         MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
 779         MX6_PAD_GPIO1_IO03__USB_OTG2_OC | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
 780
 781         /* USBOTG */
 782         MX6_PAD_UART3_CTS_B__GPIO1_IO26 | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
 783         MX6_PAD_UART3_RTS_B__GPIO1_IO27 | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
 784
 785         MX6_PAD_LCD_DATA08__GPIO3_IO13 | TX6UL_GPIO_OUT_PAD_CTRL,
 786         MX6_PAD_LCD_DATA09__GPIO3_IO14 | TX6UL_GPIO_OUT_PAD_CTRL,
 787         MX6_PAD_LCD_DATA10__GPIO3_IO15 | TX6UL_GPIO_OUT_PAD_CTRL,
 788
 789         /* USBH_VBUSEN */
 790         MX6_PAD_LCD_DATA11__GPIO3_IO16 | TX6UL_GPIO_OUT_PAD_CTRL,
 791
 792         /*
 793          * no drive capability for DUT_ETN_LINKLED, DUT_ETN_ACTLED
 794          * to not interfere whith the DUT ETN PHY strap pins
 795          */
 796         MX6_PAD_SNVS_TAMPER2__GPIO5_IO02, MUX_PAD_CTRL(PAD_CTL_HYS |
 797                                                        PAD_CTL_DSE_DISABLE |
 798                                                        PAD_CTL_SPEED_LOW),
 799         MX6_PAD_SNVS_TAMPER3__GPIO5_IO03, MUX_PAD_CTRL(PAD_CTL_HYS |
 800                                                        PAD_CTL_DSE_DISABLE |
 801                                                        PAD_CTL_SPEED_LOW),
 802 };
 803
 804 static const struct gpio tx_tester_gpios[] = {
 805         { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LEDGE#", },
 806         { IMX_GPIO_NR(5, 4), GPIOFLAG_OUTPUT_INIT_LOW, "LEDRT#", },
 807         { IMX_GPIO_NR(5, 8), GPIOFLAG_OUTPUT_INIT_LOW, "LEDGN#", },
 808
 809         { IMX_GPIO_NR(1, 26), GPIOFLAG_OUTPUT_INIT_HIGH, "PMIC PWR_ON", },
 810
 811         { IMX_GPIO_NR(3, 5), GPIOFLAG_INPUT, "TSTART#", },
 812         { IMX_GPIO_NR(3, 6), GPIOFLAG_INPUT, "STARTED", },
 813         { IMX_GPIO_NR(3, 7), GPIOFLAG_INPUT, "TSTOP#", },
 814         { IMX_GPIO_NR(3, 8), GPIOFLAG_OUTPUT_INIT_LOW, "STOP#", },
 815
 816         { IMX_GPIO_NR(3, 10), GPIOFLAG_INPUT, "DUT_PGOOD", },
 817
 818         { IMX_GPIO_NR(3, 11), GPIOFLAG_OUTPUT_INIT_HIGH, "VBACKUP_OFF", },
 819         { IMX_GPIO_NR(3, 12), GPIOFLAG_OUTPUT_INIT_LOW, "VBACKUP_LOAD", },
 820
 821         { IMX_GPIO_NR(1, 10), GPIOFLAG_OUTPUT_INIT_LOW, "VOUTLOAD1", },
 822         { IMX_GPIO_NR(3, 30), GPIOFLAG_OUTPUT_INIT_LOW, "VOUTLOAD2", },
 823         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "VOUTLOAD3", },
 824
 825         { IMX_GPIO_NR(3, 13), GPIOFLAG_OUTPUT_INIT_LOW, "VIOLOAD1", },
 826         { IMX_GPIO_NR(3, 14), GPIOFLAG_OUTPUT_INIT_LOW, "VIOLOAD2", },
 827         { IMX_GPIO_NR(3, 15), GPIOFLAG_OUTPUT_INIT_LOW, "VIOLOAD3", },
 828 };
 829
 830 #ifdef CONFIG_LCD
 831 vidinfo_t panel_info = {
 832         /* set to max. size supported by SoC */
 833         .vl_col = 4096,
 834         .vl_row = 1024,
 835
 836         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 837 };
 838
 839 static struct fb_videomode tx6ul_fb_modes[] = {
 840 #ifndef CONFIG_SYS_LVDS_IF
 841         {
 842                 /* Standard VGA timing */
 843                 .name           = "VGA",
 844                 .refresh        = 60,
 845                 .xres           = 640,
 846                 .yres           = 480,
 847                 .pixclock       = KHZ2PICOS(25175),
 848                 .left_margin    = 48,
 849                 .hsync_len      = 96,
 850                 .right_margin   = 16,
 851                 .upper_margin   = 31,
 852                 .vsync_len      = 2,
 853                 .lower_margin   = 12,
 854                 .sync           = FB_SYNC_CLK_LAT_FALL,
 855         },
 856         {
 857                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 858                  * DE high active, 115.2 mm x 86.4 mm display area
 859                  * VGA compatible timing
 860                  */
 861                 .name           = "ETV570",
 862                 .refresh        = 60,
 863                 .xres           = 640,
 864                 .yres           = 480,
 865                 .pixclock       = KHZ2PICOS(25175),
 866                 .left_margin    = 114,
 867                 .hsync_len      = 30,
 868                 .right_margin   = 16,
 869                 .upper_margin   = 32,
 870                 .vsync_len      = 3,
 871                 .lower_margin   = 10,
 872                 .sync           = FB_SYNC_CLK_LAT_FALL,
 873         },
 874         {
 875                 /* Emerging ET0350G0DH6 320 x 240 display.
 876                  * 70.08 mm x 52.56 mm display area.
 877                  */
 878                 .name           = "ET0350",
 879                 .refresh        = 60,
 880                 .xres           = 320,
 881                 .yres           = 240,
 882                 .pixclock       = KHZ2PICOS(6500),
 883                 .left_margin    = 68 - 34,
 884                 .hsync_len      = 34,
 885                 .right_margin   = 20,
 886                 .upper_margin   = 18 - 3,
 887                 .vsync_len      = 3,
 888                 .lower_margin   = 4,
 889                 .sync           = FB_SYNC_CLK_LAT_FALL,
 890         },
 891         {
 892                 /* Emerging ET0430G0DH6 480 x 272 display.
 893                  * 95.04 mm x 53.856 mm display area.
 894                  */
 895                 .name           = "ET0430",
 896                 .refresh        = 60,
 897                 .xres           = 480,
 898                 .yres           = 272,
 899                 .pixclock       = KHZ2PICOS(9000),
 900                 .left_margin    = 2,
 901                 .hsync_len      = 41,
 902                 .right_margin   = 2,
 903                 .upper_margin   = 2,
 904                 .vsync_len      = 10,
 905                 .lower_margin   = 2,
 906         },
 907         {
 908                 /* Emerging ET0500G0DH6 800 x 480 display.
 909                  * 109.6 mm x 66.4 mm display area.
 910                  */
 911                 .name           = "ET0500",
 912                 .refresh        = 60,
 913                 .xres           = 800,
 914                 .yres           = 480,
 915                 .pixclock       = KHZ2PICOS(33260),
 916                 .left_margin    = 216 - 128,
 917                 .hsync_len      = 128,
 918                 .right_margin   = 1056 - 800 - 216,
 919                 .upper_margin   = 35 - 2,
 920                 .vsync_len      = 2,
 921                 .lower_margin   = 525 - 480 - 35,
 922                 .sync           = FB_SYNC_CLK_LAT_FALL,
 923         },
 924         {
 925                 /* Emerging ETQ570G0DH6 320 x 240 display.
 926                  * 115.2 mm x 86.4 mm display area.
 927                  */
 928                 .name           = "ETQ570",
 929                 .refresh        = 60,
 930                 .xres           = 320,
 931                 .yres           = 240,
 932                 .pixclock       = KHZ2PICOS(6400),
 933                 .left_margin    = 38,
 934                 .hsync_len      = 30,
 935                 .right_margin   = 30,
 936                 .upper_margin   = 16, /* 15 according to datasheet */
 937                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 938                 .lower_margin   = 4, /* 4.5 according to datasheet */
 939                 .sync           = FB_SYNC_CLK_LAT_FALL,
 940         },
 941         {
 942                 /* Emerging ET0700G0DH6 800 x 480 display.
 943                  * 152.4 mm x 91.44 mm display area.
 944                  */
 945                 .name           = "ET0700",
 946                 .refresh        = 60,
 947                 .xres           = 800,
 948                 .yres           = 480,
 949                 .pixclock       = KHZ2PICOS(33260),
 950                 .left_margin    = 216 - 128,
 951                 .hsync_len      = 128,
 952                 .right_margin   = 1056 - 800 - 216,
 953                 .upper_margin   = 35 - 2,
 954                 .vsync_len      = 2,
 955                 .lower_margin   = 525 - 480 - 35,
 956                 .sync           = FB_SYNC_CLK_LAT_FALL,
 957         },
 958         {
 959                 /* Emerging ET070001DM6 800 x 480 display.
 960                  * 152.4 mm x 91.44 mm display area.
 961                  */
 962                 .name           = "ET070001DM6",
 963                 .refresh        = 60,
 964                 .xres           = 800,
 965                 .yres           = 480,
 966                 .pixclock       = KHZ2PICOS(33260),
 967                 .left_margin    = 216 - 128,
 968                 .hsync_len      = 128,
 969                 .right_margin   = 1056 - 800 - 216,
 970                 .upper_margin   = 35 - 2,
 971                 .vsync_len      = 2,
 972                 .lower_margin   = 525 - 480 - 35,
 973                 .sync           = 0,
 974         },
 975 #else
 976         {
 977                 /* HannStar HSD100PXN1
 978                  * 202.7m mm x 152.06 mm display area.
 979                  */
 980                 .name           = "HSD100PXN1",
 981                 .refresh        = 60,
 982                 .xres           = 1024,
 983                 .yres           = 768,
 984                 .pixclock       = KHZ2PICOS(65000),
 985                 .left_margin    = 0,
 986                 .hsync_len      = 0,
 987                 .right_margin   = 320,
 988                 .upper_margin   = 0,
 989                 .vsync_len      = 0,
 990                 .lower_margin   = 38,
 991                 .sync           = FB_SYNC_CLK_LAT_FALL,
 992         },
 993 #endif
 994         {
 995                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 996                 .refresh        = 60,
 997                 .left_margin    = 48,
 998                 .hsync_len      = 96,
 999                 .right_margin   = 16,
1000                 .upper_margin   = 31,
1001                 .vsync_len      = 2,
1002                 .lower_margin   = 12,
1003                 .sync           = FB_SYNC_CLK_LAT_FALL,
1004         },
1005 };
1006
1007 static int lcd_enabled = 1;
1008 static int lcd_bl_polarity;
1009
1010 static int lcd_backlight_polarity(void)
1011 {
1012         return lcd_bl_polarity;
1013 }
1014
1015 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
1016 #ifdef CONFIG_LCD
1017         /* LCD RESET */
1018         MX6_PAD_LCD_RESET__GPIO3_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
1019         /* LCD POWER_ENABLE */
1020         MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
1021         /* LCD Backlight (PWM) */
1022         MX6_PAD_NAND_DQS__GPIO4_IO16 | TX6UL_GPIO_OUT_PAD_CTRL,
1023         /* Display */
1024         MX6_PAD_LCD_DATA00__LCDIF_DATA00,
1025         MX6_PAD_LCD_DATA01__LCDIF_DATA01,
1026         MX6_PAD_LCD_DATA02__LCDIF_DATA02,
1027         MX6_PAD_LCD_DATA03__LCDIF_DATA03,
1028         MX6_PAD_LCD_DATA04__LCDIF_DATA04,
1029         MX6_PAD_LCD_DATA05__LCDIF_DATA05,
1030         MX6_PAD_LCD_DATA06__LCDIF_DATA06,
1031         MX6_PAD_LCD_DATA07__LCDIF_DATA07,
1032         MX6_PAD_LCD_DATA08__LCDIF_DATA08,
1033         MX6_PAD_LCD_DATA09__LCDIF_DATA09,
1034         MX6_PAD_LCD_DATA10__LCDIF_DATA10,
1035         MX6_PAD_LCD_DATA11__LCDIF_DATA11,
1036         MX6_PAD_LCD_DATA12__LCDIF_DATA12,
1037         MX6_PAD_LCD_DATA13__LCDIF_DATA13,
1038         MX6_PAD_LCD_DATA14__LCDIF_DATA14,
1039         MX6_PAD_LCD_DATA15__LCDIF_DATA15,
1040         MX6_PAD_LCD_DATA16__LCDIF_DATA16,
1041         MX6_PAD_LCD_DATA17__LCDIF_DATA17,
1042         MX6_PAD_LCD_DATA18__LCDIF_DATA18,
1043         MX6_PAD_LCD_DATA19__LCDIF_DATA19,
1044         MX6_PAD_LCD_DATA20__LCDIF_DATA20,
1045         MX6_PAD_LCD_DATA21__LCDIF_DATA21,
1046         MX6_PAD_LCD_DATA22__LCDIF_DATA22,
1047         MX6_PAD_LCD_DATA23__LCDIF_DATA23,
1048         MX6_PAD_LCD_HSYNC__LCDIF_HSYNC, /* HSYNC */
1049         MX6_PAD_LCD_VSYNC__LCDIF_VSYNC, /* VSYNC */
1050         MX6_PAD_LCD_ENABLE__LCDIF_ENABLE, /* OE_ACD */
1051         MX6_PAD_LCD_CLK__LCDIF_CLK, /* LSCLK */
1052 #endif
1053 };
1054
1055 static const struct gpio stk5_lcd_gpios[] = {
1056         { TX6UL_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1057         { TX6UL_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1058         { TX6UL_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1059 };
1060
1061 /* run with valid env from NAND/eMMC */
1062 void lcd_enable(void)
1063 {
1064         /* HACK ALERT:
1065          * global variable from common/lcd.c
1066          * Set to 0 here to prevent messages from going to LCD
1067          * rather than serial console
1068          */
1069         lcd_is_enabled = 0;
1070
1071         if (lcd_enabled) {
1072                 karo_load_splashimage(1);
1073
1074                 debug("Switching LCD on\n");
1075                 gpio_set_value(TX6UL_LCD_PWR_GPIO, 1);
1076                 udelay(100);
1077                 gpio_set_value(TX6UL_LCD_RST_GPIO, 1);
1078                 udelay(300000);
1079                 gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
1080                                lcd_backlight_polarity());
1081         }
1082 }
1083
1084 static void lcd_disable(void)
1085 {
1086         if (lcd_enabled) {
1087                 printf("Disabling LCD\n");
1088                 panel_info.vl_row = 0;
1089                 lcd_enabled = 0;
1090         }
1091 }
1092
1093 void lcd_ctrl_init(void *lcdbase)
1094 {
1095         int color_depth = 24;
1096         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1097         const char *vm;
1098         unsigned long val;
1099         int refresh = 60;
1100         struct fb_videomode *p = &tx6ul_fb_modes[0];
1101         struct fb_videomode fb_mode;
1102         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1103
1104         if (!lcd_enabled) {
1105                 debug("LCD disabled\n");
1106                 return;
1107         }
1108
1109         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1110                 lcd_disable();
1111                 setenv("splashimage", NULL);
1112                 return;
1113         }
1114
1115         karo_fdt_move_fdt();
1116         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1117
1118         if (video_mode == NULL) {
1119                 lcd_disable();
1120                 return;
1121         }
1122         vm = video_mode;
1123         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1124                 p = &fb_mode;
1125                 debug("Using video mode from FDT\n");
1126                 vm += strlen(vm);
1127                 if (fb_mode.xres > panel_info.vl_col ||
1128                         fb_mode.yres > panel_info.vl_row) {
1129                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1130                                fb_mode.xres, fb_mode.yres,
1131                                panel_info.vl_col, panel_info.vl_row);
1132                         lcd_enabled = 0;
1133                         return;
1134                 }
1135         }
1136         if (p->name != NULL)
1137                 debug("Trying compiled-in video modes\n");
1138         while (p->name != NULL) {
1139                 if (strcmp(p->name, vm) == 0) {
1140                         debug("Using video mode: '%s'\n", p->name);
1141                         vm += strlen(vm);
1142                         break;
1143                 }
1144                 p++;
1145         }
1146         if (*vm != '\0')
1147                 debug("Trying to decode video_mode: '%s'\n", vm);
1148         while (*vm != '\0') {
1149                 if (*vm >= '0' && *vm <= '9') {
1150                         char *end;
1151
1152                         val = simple_strtoul(vm, &end, 0);
1153                         if (end > vm) {
1154                                 if (!xres_set) {
1155                                         if (val > panel_info.vl_col)
1156                                                 val = panel_info.vl_col;
1157                                         p->xres = val;
1158                                         panel_info.vl_col = val;
1159                                         xres_set = 1;
1160                                 } else if (!yres_set) {
1161                                         if (val > panel_info.vl_row)
1162                                                 val = panel_info.vl_row;
1163                                         p->yres = val;
1164                                         panel_info.vl_row = val;
1165                                         yres_set = 1;
1166                                 } else if (!bpp_set) {
1167                                         switch (val) {
1168                                         case 8:
1169                                         case 16:
1170                                         case 18:
1171                                         case 24:
1172                                         case 32:
1173                                                 color_depth = val;
1174                                                 break;
1175
1176                                         default:
1177                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1178                                                        end - vm, vm,
1179                                                        color_depth);
1180                                         }
1181                                         bpp_set = 1;
1182                                 } else if (!refresh_set) {
1183                                         refresh = val;
1184                                         refresh_set = 1;
1185                                 }
1186                         }
1187                         vm = end;
1188                 }
1189                 switch (*vm) {
1190                 case '@':
1191                         bpp_set = 1;
1192                         /* fallthru */
1193                 case '-':
1194                         yres_set = 1;
1195                         /* fallthru */
1196                 case 'x':
1197                         xres_set = 1;
1198                         /* fallthru */
1199                 case 'M':
1200                 case 'R':
1201                         vm++;
1202                         break;
1203
1204                 default:
1205                         if (*vm != '\0')
1206                                 vm++;
1207                 }
1208         }
1209         if (p->xres == 0 || p->yres == 0) {
1210                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1211                 lcd_enabled = 0;
1212                 printf("Supported video modes are:");
1213                 for (p = &tx6ul_fb_modes[0]; p->name != NULL; p++) {
1214                         printf(" %s", p->name);
1215                 }
1216                 printf("\n");
1217                 return;
1218         }
1219         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1220                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1221                        p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1222                 lcd_enabled = 0;
1223                 return;
1224         }
1225         panel_info.vl_col = p->xres;
1226         panel_info.vl_row = p->yres;
1227
1228         switch (color_depth) {
1229         case 8:
1230                 panel_info.vl_bpix = LCD_COLOR8;
1231                 break;
1232         case 16:
1233                 panel_info.vl_bpix = LCD_COLOR16;
1234                 break;
1235         default:
1236                 panel_info.vl_bpix = LCD_COLOR32;
1237         }
1238
1239         p->pixclock = KHZ2PICOS(refresh *
1240                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1241                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1242                                 1000);
1243         debug("Pixel clock set to %lu.%03lu MHz\n",
1244               PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1245
1246         if (p != &fb_mode) {
1247                 int ret;
1248
1249                 debug("Creating new display-timing node from '%s'\n",
1250                       video_mode);
1251                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1252                 if (ret)
1253                         printf("Failed to create new display-timing node from '%s': %d\n",
1254                                video_mode, ret);
1255         }
1256
1257         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1258         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1259                                          ARRAY_SIZE(stk5_lcd_pads));
1260
1261         debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
1262               color_depth, refresh);
1263
1264         if (karo_load_splashimage(0) == 0) {
1265                 char vmode[128];
1266
1267                 /* setup env variable for mxsfb display driver */
1268                 snprintf(vmode, sizeof(vmode),
1269                          "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
1270                          p->xres, p->yres, p->left_margin, p->right_margin,
1271                          p->upper_margin, p->lower_margin, p->hsync_len,
1272                          p->vsync_len, p->sync, p->pixclock, color_depth);
1273                 setenv("videomode", vmode);
1274
1275                 debug("Initializing LCD controller\n");
1276                 lcdif_clk_enable();
1277                 video_hw_init();
1278                 setenv("videomode", NULL);
1279         } else {
1280                 debug("Skipping initialization of LCD controller\n");
1281         }
1282 }
1283 #else
1284 #define lcd_enabled 0
1285 #endif /* CONFIG_LCD */
1286
1287 #ifndef CONFIG_ENV_IS_IN_MMC
1288 static void tx6ul_mmc_init(void)
1289 {
1290         puts("MMC:   ");
1291         if (board_mmc_init(gd->bd) < 0)
1292                 cpu_mmc_init(gd->bd);
1293         print_mmc_devices(',');
1294 }
1295 #else
1296 static inline void tx6ul_mmc_init(void)
1297 {
1298 }
1299 #endif
1300
1301 static void stk5_board_init(void)
1302 {
1303         int ret;
1304
1305         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1306         if (ret < 0) {
1307                 printf("Failed to request stk5_gpios: %d\n", ret);
1308                 return;
1309         }
1310
1311         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1312         if (getenv_yesno("jtag_enable") != 0) {
1313                 /* true if unset or set to one of: 'yYtT1' */
1314                 imx_iomux_v3_setup_multiple_pads(stk5_jtag_pads, ARRAY_SIZE(stk5_jtag_pads));
1315         }
1316
1317         debug("%s@%d: \n", __func__, __LINE__);
1318 }
1319
1320 static void stk5v3_board_init(void)
1321 {
1322         debug("%s@%d: \n", __func__, __LINE__);
1323         stk5_board_init();
1324         debug("%s@%d: \n", __func__, __LINE__);
1325         tx6ul_mmc_init();
1326 }
1327
1328 static void stk5v5_board_init(void)
1329 {
1330         int ret;
1331
1332         stk5_board_init();
1333         tx6ul_mmc_init();
1334
1335         ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
1336                                "Flexcan Transceiver");
1337         if (ret) {
1338                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1339                 return;
1340         }
1341
1342         imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 |
1343                                TX6UL_GPIO_OUT_PAD_CTRL);
1344 }
1345
1346 static void tx_tester_board_init(void)
1347 {
1348         int ret;
1349
1350         setenv("video_mode", NULL);
1351         setenv("touchpanel", NULL);
1352         if (getenv("eth1addr") && !getenv("ethprime"))
1353                 setenv("ethprime", "FEC1");
1354
1355         ret = gpio_request_array(tx_tester_gpios, ARRAY_SIZE(tx_tester_gpios));
1356         if (ret) {
1357                 printf("Failed to request TX-Tester GPIOs: %d\n", ret);
1358                 return;
1359         }
1360         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1361
1362         if (wrsr & WRSR_TOUT)
1363                 gpio_set_value(IMX_GPIO_NR(5, 4), 1);
1364
1365         if (getenv_yesno("jtag_enable") != 0) {
1366                 /* true if unset or set to one of: 'yYtT1' */
1367                 imx_iomux_v3_setup_multiple_pads(stk5_jtag_pads,
1368                                                  ARRAY_SIZE(stk5_jtag_pads));
1369         }
1370
1371         gpio_set_value(IMX_GPIO_NR(3, 8), 1);
1372 }
1373
1374 static void tx6ul_set_cpu_clock(void)
1375 {
1376         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1377
1378         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1379                 return;
1380
1381         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1382                 printf("%s detected; skipping cpu clock change\n",
1383                        (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1384                 return;
1385         }
1386         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1387                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1388                 printf("CPU clock set to %lu.%03lu MHz\n",
1389                        cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1390         } else {
1391                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1392         }
1393 }
1394
1395 int board_late_init(void)
1396 {
1397         const char *baseboard;
1398
1399         debug("%s@%d: \n", __func__, __LINE__);
1400
1401         env_cleanup();
1402
1403         if (tx6ul_temp_check_enabled)
1404                 check_cpu_temperature(1);
1405
1406         tx6ul_set_cpu_clock();
1407
1408         if (had_ctrlc())
1409                 setenv_ulong("safeboot", 1);
1410         else if (wrsr & WRSR_TOUT)
1411                 setenv_ulong("wdreset", 1);
1412         else
1413                 karo_fdt_move_fdt();
1414
1415         baseboard = getenv("baseboard");
1416         if (!baseboard)
1417                 goto exit;
1418
1419         printf("Baseboard: %s\n", baseboard);
1420
1421         if (strncmp(baseboard, "stk5", 4) == 0) {
1422                 if ((strlen(baseboard) == 4) ||
1423                         strcmp(baseboard, "stk5-v3") == 0) {
1424                         stk5v3_board_init();
1425                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1426                         const char *otg_mode = getenv("otg_mode");
1427
1428                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1429                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1430                                        otg_mode, baseboard);
1431                                 setenv("otg_mode", "none");
1432                         }
1433                         stk5v5_board_init();
1434                 } else {
1435                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1436                                 baseboard + 4);
1437                 }
1438         } else if (strncmp(baseboard, "ulmb-", 5) == 0) {
1439                         const char *otg_mode = getenv("otg_mode");
1440
1441                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1442                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1443                                        otg_mode, baseboard);
1444                                 setenv("otg_mode", "none");
1445                         }
1446                         stk5_board_init();
1447         } else if (strncmp(baseboard, "tx-tester-", 10) == 0) {
1448                         const char *otg_mode = getenv("otg_mode");
1449
1450                         if (!otg_mode || strcmp(otg_mode, "none") != 0)
1451                                 setenv("otg_mode", "device");
1452                         tx_tester_board_init();
1453         } else {
1454                 printf("WARNING: Unsupported baseboard: '%s'\n",
1455                         baseboard);
1456                 printf("Reboot with <CTRL-C> pressed to fix this\n");
1457                 if (!had_ctrlc())
1458                         return -EINVAL;
1459         }
1460
1461 exit:
1462         debug("%s@%d: \n", __func__, __LINE__);
1463
1464         clear_ctrlc();
1465         return 0;
1466 }
1467
1468 #ifdef CONFIG_FEC_MXC
1469
1470 #ifndef ETH_ALEN
1471 #define ETH_ALEN 6
1472 #endif
1473
1474 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
1475 {
1476         unsigned int mac0, mac1, mac2;
1477         unsigned int __maybe_unused fuse3_override, fuse4_override;
1478
1479         memset(mac, 0, 6);
1480
1481         switch (dev_id) {
1482         case 0:
1483                 if (fuse_read(4, 2, &mac0)) {
1484                         printf("Failed to read MAC0 fuse\n");
1485                         return;
1486                 }
1487                 if (fuse_read(4, 3, &mac1)) {
1488                         printf("Failed to read MAC1 fuse\n");
1489                         return;
1490                 }
1491                 mac[0] = mac1 >> 8;
1492                 mac[1] = mac1;
1493                 mac[2] = mac0 >> 24;
1494                 mac[3] = mac0 >> 16;
1495                 mac[4] = mac0 >> 8;
1496                 mac[5] = mac0;
1497                 break;
1498
1499         case 1:
1500                 if (fuse_read(4, 3, &mac1)) {
1501                         printf("Failed to read MAC1 fuse\n");
1502                         return;
1503                 }
1504                 debug("read %08x from fuse 3\n", mac1);
1505                 if (fuse_read(4, 4, &mac2)) {
1506                         printf("Failed to read MAC2 fuse\n");
1507                         return;
1508                 }
1509                 debug("read %08x from fuse 4\n", mac2);
1510                 mac[0] = mac2 >> 24;
1511                 mac[1] = mac2 >> 16;
1512                 mac[2] = mac2 >> 8;
1513                 mac[3] = mac2;
1514                 mac[4] = mac1 >> 24;
1515                 mac[5] = mac1 >> 16;
1516                 break;
1517
1518         default:
1519                 return;
1520         }
1521         debug("%s@%d: Done %d %pM\n", __func__, __LINE__, dev_id, mac);
1522 }
1523
1524 static void tx6ul_init_mac(void)
1525 {
1526         u8 mac[ETH_ALEN];
1527         const char *baseboard = getenv("baseboard");
1528
1529         imx_get_mac_from_fuse(0, mac);
1530         if (!is_valid_ethaddr(mac)) {
1531                 printf("No valid MAC address programmed\n");
1532                 return;
1533         }
1534         printf("MAC addr from fuse: %pM\n", mac);
1535         if (!getenv("ethaddr"))
1536                 eth_setenv_enetaddr("ethaddr", mac);
1537
1538         if (!baseboard || strncmp(baseboard, "stk5", 4) == 0) {
1539                 setenv("eth1addr", NULL);
1540                 return;
1541         }
1542         if (getenv("eth1addr"))
1543                 return;
1544         imx_get_mac_from_fuse(1, mac);
1545         if (is_valid_ethaddr(mac))
1546                 eth_setenv_enetaddr("eth1addr", mac);
1547 }
1548
1549 int board_eth_init(bd_t *bis)
1550 {
1551         int ret;
1552
1553         tx6ul_init_mac();
1554
1555         /* delay at least 21ms for the PHY internal POR signal to deassert */
1556         udelay(22000);
1557
1558         imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads,
1559                                          ARRAY_SIZE(tx6ul_enet1_pads));
1560
1561         /* Deassert RESET to the external phys */
1562         gpio_set_value(TX6UL_FEC_RST_GPIO, 1);
1563
1564         if (getenv("ethaddr")) {
1565                 ret = fecmxc_initialize_multi(bis, 0, 0, ENET_BASE_ADDR);
1566                 if (ret) {
1567                         printf("failed to initialize FEC0: %d\n", ret);
1568                         return ret;
1569                 }
1570         }
1571         if (getenv("eth1addr")) {
1572                 ret = gpio_request_array(tx6ul_fec2_gpios,
1573                                          ARRAY_SIZE(tx6ul_fec2_gpios));
1574                 if (ret < 0) {
1575                         printf("Failed to request tx6ul_fec2_gpios: %d\n", ret);
1576                 }
1577                 imx_iomux_v3_setup_multiple_pads(tx6ul_enet2_pads,
1578                                                  ARRAY_SIZE(tx6ul_enet2_pads));
1579
1580                 writel(0x00100000, 0x020c80e4); /* assert ENET2_125M_EN */
1581
1582                 /* Minimum PHY reset duration */
1583                 udelay(100);
1584                 gpio_set_value(TX6UL_FEC2_RST_GPIO, 1);
1585                 /* Wait for PHY internal POR to finish */
1586                 udelay(22000);
1587
1588                 ret = fecmxc_initialize_multi(bis, 1, 2, ENET2_BASE_ADDR);
1589                 if (ret) {
1590                         printf("failed to initialize FEC1: %d\n", ret);
1591                         return ret;
1592                 }
1593         }
1594         return 0;
1595 }
1596 #endif /* CONFIG_FEC_MXC */
1597
1598 #ifdef CONFIG_SERIAL_TAG
1599 void get_board_serial(struct tag_serialnr *serialnr)
1600 {
1601         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1602         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1603
1604         serialnr->low = readl(&fuse->cfg0);
1605         serialnr->high = readl(&fuse->cfg1);
1606 }
1607 #endif
1608
1609 #if defined(CONFIG_OF_BOARD_SETUP)
1610 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1611 #include <jffs2/jffs2.h>
1612 #include <mtd_node.h>
1613 static struct node_info nodes[] = {
1614         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1615 };
1616 #else
1617 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1618 #endif
1619
1620 static const char *tx6ul_touchpanels[] = {
1621         "ti,tsc2007",
1622         "edt,edt-ft5x06",
1623         "eeti,egalax_ts",
1624 };
1625
1626 int ft_board_setup(void *blob, bd_t *bd)
1627 {
1628         const char *baseboard = getenv("baseboard");
1629         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1630         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1631         int ret;
1632
1633         ret = fdt_increase_size(blob, 4096);
1634         if (ret) {
1635                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1636                 return ret;
1637         }
1638         if (stk5_v5)
1639                 karo_fdt_enable_node(blob, "stk5led", 0);
1640
1641         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1642
1643         karo_fdt_fixup_touchpanel(blob, tx6ul_touchpanels,
1644                                   ARRAY_SIZE(tx6ul_touchpanels));
1645         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1646         karo_fdt_fixup_flexcan(blob, stk5_v5);
1647
1648         karo_fdt_update_fb_mode(blob, video_mode, "/lcd-panel");
1649
1650         return 0;
1651 }
1652 #endif /* CONFIG_OF_BOARD_SETUP */