2 * Copyright (C) 2015 Lothar Waßmann <LW@KARO-electronics.de>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <fdt_support.h>
14 #include <fsl_esdhc.h>
22 #include <asm/arch/mx6-pins.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/hab.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/crm_regs.h>
27 #include <asm/arch/sys_proto.h>
29 #include "../common/karo.h"
32 #define __data __attribute__((section(".data")))
34 #define TX6UL_FEC_RST_GPIO IMX_GPIO_NR(5, 6)
35 #define TX6UL_FEC_PWR_GPIO IMX_GPIO_NR(5, 7)
36 #define TX6UL_FEC_INT_GPIO IMX_GPIO_NR(5, 5)
38 #define TX6UL_FEC2_RST_GPIO IMX_GPIO_NR(4, 28)
39 #define TX6UL_FEC2_INT_GPIO IMX_GPIO_NR(4, 27)
41 #define TX6UL_LED_GPIO IMX_GPIO_NR(5, 9)
43 #define TX6UL_LCD_PWR_GPIO IMX_GPIO_NR(5, 4)
44 #define TX6UL_LCD_RST_GPIO IMX_GPIO_NR(3, 4)
45 #define TX6UL_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(4, 16)
47 #ifdef CONFIG_SYS_I2C_SOFT
48 #define TX6UL_I2C1_SCL_GPIO CONFIG_SOFT_I2C_GPIO_SCL
49 #define TX6UL_I2C1_SDA_GPIO CONFIG_SOFT_I2C_GPIO_SDA
52 #define TX6UL_SD1_CD_GPIO IMX_GPIO_NR(4, 14)
54 #ifdef CONFIG_MX6_TEMPERATURE_MIN
55 #define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN
57 #define TEMPERATURE_MIN (-40)
59 #ifdef CONFIG_MX6_TEMPERATURE_HOT
60 #define TEMPERATURE_HOT CONFIG_MX6_TEMPERATURE_HOT
62 #define TEMPERATURE_HOT 80
65 DECLARE_GLOBAL_DATA_PTR;
67 #define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
69 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
70 #ifdef CONFIG_SECURE_BOOT
71 char __csf_data[0] __attribute__((section(".__csf_data")));
74 #define TX6UL_DEFAULT_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP | \
78 #define TX6UL_I2C_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | \
84 #define TX6UL_I2C_GPIO_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | \
88 #define TX6UL_ENET_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH | \
90 PAD_CTL_PUS_100K_UP | \
92 #define TX6UL_GPIO_OUT_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_LOW | \
95 #define TX6UL_GPIO_IN_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_LOW | \
99 static const iomux_v3_cfg_t const tx6ul_pads[] = {
101 #if CONFIG_MXC_UART_BASE == UART1_BASE
102 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
103 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
104 MX6_PAD_UART1_RTS_B__UART1_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
105 MX6_PAD_UART1_CTS_B__UART1_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
107 #if CONFIG_MXC_UART_BASE == UART2_BASE
108 MX6_PAD_UART2_TX_DATA__UART2_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
109 MX6_PAD_UART2_RX_DATA__UART2_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
110 MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
111 MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
113 #if CONFIG_MXC_UART_BASE == UART5_BASE
114 MX6_PAD_GPIO1_IO04__UART5_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
115 MX6_PAD_GPIO1_IO05__UART5_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
116 MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
117 MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
119 /* FEC PHY GPIO functions */
120 MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY POWER */
121 MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY RESET */
122 MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | TX6UL_GPIO_IN_PAD_CTRL, /* PHY INT */
125 static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = {
127 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_48ohm |
129 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
130 PAD_CTL_DSE_48ohm | PAD_CTL_SPEED_MED),
131 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_CFG_SION |
132 MUX_PAD_CTRL(PAD_CTL_SPEED_MED |
133 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST),
134 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | TX6UL_ENET_PAD_CTRL,
135 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | TX6UL_ENET_PAD_CTRL,
136 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | TX6UL_ENET_PAD_CTRL,
137 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | TX6UL_ENET_PAD_CTRL,
138 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | TX6UL_ENET_PAD_CTRL,
139 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | TX6UL_ENET_PAD_CTRL,
140 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | TX6UL_ENET_PAD_CTRL,
143 static const iomux_v3_cfg_t const tx6ul_enet2_pads[] = {
144 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_CFG_SION |
145 MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |
146 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST),
147 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | TX6UL_ENET_PAD_CTRL,
148 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | TX6UL_ENET_PAD_CTRL,
149 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | TX6UL_ENET_PAD_CTRL,
150 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | TX6UL_ENET_PAD_CTRL,
151 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | TX6UL_ENET_PAD_CTRL,
152 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | TX6UL_ENET_PAD_CTRL,
153 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | TX6UL_ENET_PAD_CTRL,
156 static const iomux_v3_cfg_t const tx6ul_i2c_pads[] = {
158 MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
159 TX6UL_I2C_PAD_CTRL, /* I2C SCL */
160 MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
161 TX6UL_I2C_PAD_CTRL, /* I2C SDA */
164 static const iomux_v3_cfg_t const tx6ul_i2c_gpio_pads[] = {
165 /* internal I2C set up for I2C bus recovery */
166 MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
167 TX6UL_I2C_PAD_CTRL, /* I2C SCL */
168 MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
169 TX6UL_I2C_PAD_CTRL, /* I2C SDA */
172 static const struct gpio const tx6ul_gpios[] = {
173 #ifdef CONFIG_SYS_I2C_SOFT
174 /* These two entries are used to forcefully reinitialize the I2C bus */
175 { TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
176 { TX6UL_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
178 { TX6UL_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
179 { TX6UL_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
180 { TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
183 static const struct gpio const tx6ul_fec2_gpios[] = {
184 { TX6UL_FEC2_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC2 PHY RESET", },
185 { TX6UL_FEC2_INT_GPIO, GPIOFLAG_INPUT, "FEC2 PHY INT", },
192 /* run with default environment */
193 #if defined(TX6UL_I2C1_SCL_GPIO) && defined(TX6UL_I2C1_SDA_GPIO)
194 #define SCL_BANK (TX6UL_I2C1_SCL_GPIO / 32)
195 #define SDA_BANK (TX6UL_I2C1_SDA_GPIO / 32)
196 #define SCL_BIT (1 << (TX6UL_I2C1_SCL_GPIO % 32))
197 #define SDA_BIT (1 << (TX6UL_I2C1_SDA_GPIO % 32))
199 static void * const gpio_ports[] = {
200 (void *)GPIO1_BASE_ADDR,
201 (void *)GPIO2_BASE_ADDR,
202 (void *)GPIO3_BASE_ADDR,
203 (void *)GPIO4_BASE_ADDR,
204 (void *)GPIO5_BASE_ADDR,
207 static void tx6ul_i2c_recover(void)
211 struct gpio_regs *scl_regs = gpio_ports[SCL_BANK];
212 struct gpio_regs *sda_regs = gpio_ports[SDA_BANK];
214 if ((readl(&scl_regs->gpio_psr) & SCL_BIT) &&
215 (readl(&sda_regs->gpio_psr) & SDA_BIT))
218 debug("Clearing I2C bus\n");
219 if (!(readl(&scl_regs->gpio_psr) & SCL_BIT)) {
220 printf("I2C SCL stuck LOW\n");
223 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
224 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
226 imx_iomux_v3_setup_pad(MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 |
227 MUX_CFG_SION | TX6UL_GPIO_OUT_PAD_CTRL);
229 if (!(readl(&sda_regs->gpio_psr) & SDA_BIT)) {
230 printf("I2C SDA stuck LOW\n");
233 clrbits_le32(&sda_regs->gpio_dir, SDA_BIT);
234 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
235 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
237 imx_iomux_v3_setup_multiple_pads(tx6ul_i2c_gpio_pads,
238 ARRAY_SIZE(tx6ul_i2c_gpio_pads));
242 for (i = 0; i < 18; i++) {
243 u32 reg = readl(&scl_regs->gpio_dr) ^ SCL_BIT;
245 debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
246 writel(reg, &scl_regs->gpio_dr);
249 if (readl(&sda_regs->gpio_psr) & SDA_BIT)
251 if (!(readl(&scl_regs->gpio_psr) & SCL_BIT))
258 bool scl = !!(readl(&scl_regs->gpio_psr) & SCL_BIT);
259 bool sda = !!(readl(&sda_regs->gpio_psr) & SDA_BIT);
262 printf("I2C bus recovery succeeded\n");
264 printf("I2C bus recovery FAILED: SCL: %d SDA: %d\n",
267 imx_iomux_v3_setup_multiple_pads(tx6ul_i2c_pads,
268 ARRAY_SIZE(tx6ul_i2c_pads));
272 static inline void tx6ul_i2c_recover(void)
277 /* placed in section '.data' to prevent overwriting relocation info
280 static u32 wrsr __data;
282 #define WRSR_POR (1 << 4)
283 #define WRSR_TOUT (1 << 1)
284 #define WRSR_SFTW (1 << 0)
286 static void print_reset_cause(void)
288 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
289 void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
293 printf("Reset cause: ");
295 srsr = readl(&src_regs->srsr);
296 wrsr = readw(wdt_base + 4);
298 if (wrsr & WRSR_POR) {
299 printf("%sPOR", dlm);
302 if (srsr & 0x00004) {
303 printf("%sCSU", dlm);
306 if (srsr & 0x00008) {
307 printf("%sIPP USER", dlm);
310 if (srsr & 0x00010) {
311 if (wrsr & WRSR_SFTW) {
312 printf("%sSOFT", dlm);
315 if (wrsr & WRSR_TOUT) {
316 printf("%sWDOG", dlm);
320 if (srsr & 0x00020) {
321 printf("%sJTAG HIGH-Z", dlm);
324 if (srsr & 0x00040) {
325 printf("%sJTAG SW", dlm);
328 if (srsr & 0x10000) {
329 printf("%sWARM BOOT", dlm);
338 #ifdef CONFIG_IMX6_THERMAL
340 #include <imx_thermal.h>
343 static void print_temperature(void)
345 struct udevice *thermal_dev;
346 int cpu_tmp, minc, maxc, ret;
347 char const *grade_str;
348 static u32 __data thermal_calib;
350 puts("Temperature: ");
351 switch (get_cpu_temp_grade(&minc, &maxc)) {
352 case TEMP_AUTOMOTIVE:
353 grade_str = "Automotive";
355 case TEMP_INDUSTRIAL:
356 grade_str = "Industrial";
358 case TEMP_EXTCOMMERCIAL:
359 grade_str = "Extended Commercial";
362 grade_str = "Commercial";
364 printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
365 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
367 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
370 printf(" at %dC", cpu_tmp);
372 puts(" - failed to read sensor data");
374 puts(" - no sensor device found");
377 if (fuse_read(1, 6, &thermal_calib) == 0) {
378 printf(" - calibration data 0x%08x\n", thermal_calib);
380 puts(" - Failed to read thermal calib fuse\n");
384 static inline void print_temperature(void)
391 u32 cpurev = get_cpu_rev();
394 if (is_cpu_type(MXC_CPU_MX6SL))
396 else if (is_cpu_type(MXC_CPU_MX6DL))
398 else if (is_cpu_type(MXC_CPU_MX6SOLO))
400 else if (is_cpu_type(MXC_CPU_MX6Q))
402 else if (is_cpu_type(MXC_CPU_MX6UL))
405 printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n",
407 (cpurev & 0x000F0) >> 4,
408 (cpurev & 0x0000F) >> 0,
409 mxc_get_clock(MXC_ARM_CLK) / 1000000);
413 #ifdef CONFIG_MX6_TEMPERATURE_HOT
414 check_cpu_temperature(1);
420 /* serial port not initialized at this point */
421 int board_early_init_f(void)
426 #ifndef CONFIG_MX6_TEMPERATURE_HOT
427 static bool tx6ul_temp_check_enabled = true;
429 #define tx6ul_temp_check_enabled 0
432 static inline u8 tx6ul_mem_suffix(void)
434 #ifdef CONFIG_TX6UL_NAND
441 #ifdef CONFIG_RN5T567
443 #define VDD_RTC_VAL rn5t_mV_to_regval_rtc(3000)
444 #define VDD_CORE_VAL rn5t_mV_to_regval(1300) /* DCDC1 */
445 #define VDD_CORE_VAL_LP rn5t_mV_to_regval(900)
446 #define VDD_DDR_VAL rn5t_mV_to_regval(1350) /* DCDC3 */
447 #define VDD_DDR_VAL_LP rn5t_mV_to_regval(1350)
448 #define VDD_HIGH_VAL rn5t_mV_to_regval(3300) /* DCDC4 */
449 #define VDD_HIGH_VAL_LP rn5t_mV_to_regval(3300)
450 #define VDD_CSI_VAL rn5t_mV_to_regval2(3300) /* LDO4 */
451 #define VDD_CSI_VAL_LP rn5t_mV_to_regval2(3300)
453 static struct pmic_regs rn5t567_regs[] = {
454 { RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, },
455 { RN5T567_DC2CTL, DC2_DC2DIS, },
456 { RN5T567_DC1DAC, VDD_CORE_VAL, },
457 { RN5T567_DC3DAC, VDD_DDR_VAL, },
458 { RN5T567_DC4DAC, VDD_HIGH_VAL, },
459 { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
460 { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
461 { RN5T567_DC4DAC_SLP, VDD_HIGH_VAL_LP, },
462 { RN5T567_LDOEN1, 0x01f, ~0x1f, },
463 { RN5T567_LDOEN2, 0x10, ~0x30, },
464 { RN5T567_LDODIS, 0x00, },
465 { RN5T567_LDO4DAC, VDD_CSI_VAL, },
466 { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
467 { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
470 static int pmic_addr = 0x33;
476 u32 cpurev = get_cpu_rev();
478 debug("%s@%d: \n", __func__, __LINE__);
480 printf("Board: Ka-Ro TXUL-%c01%c\n",
481 ((cpurev &0xff) > 0x10) ? '5' : '0',
486 ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios));
488 printf("Failed to request tx6ul_gpios: %d\n", ret);
490 imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads));
492 /* Address of boot parameters */
493 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
494 gd->bd->bi_arch_number = -1;
496 if (ctrlc() || (wrsr & WRSR_TOUT)) {
497 if (wrsr & WRSR_TOUT)
498 printf("WDOG RESET detected; Skipping PMIC setup\n");
500 printf("<CTRL-C> detected; safeboot enabled\n");
501 #ifndef CONFIG_MX6_TEMPERATURE_HOT
502 tx6ul_temp_check_enabled = false;
507 ret = tx6_pmic_init(pmic_addr, rn5t567_regs, ARRAY_SIZE(rn5t567_regs));
509 printf("Failed to setup PMIC voltages: %d\n", ret);
517 debug("%s@%d: \n", __func__, __LINE__);
519 /* dram_init must store complete ramsize in gd->ram_size */
520 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
521 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
525 void dram_init_banksize(void)
527 debug("%s@%d: \n", __func__, __LINE__);
529 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
530 gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
532 #if CONFIG_NR_DRAM_BANKS > 1
533 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
534 gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
539 #ifdef CONFIG_FSL_ESDHC
540 #define TX6UL_SD_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP | \
541 PAD_CTL_SPEED_MED | \
542 PAD_CTL_DSE_40ohm | \
545 static const iomux_v3_cfg_t mmc0_pads[] = {
546 MX6_PAD_SD1_CMD__USDHC1_CMD | TX6UL_SD_PAD_CTRL,
547 MX6_PAD_SD1_CLK__USDHC1_CLK | TX6UL_SD_PAD_CTRL,
548 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | TX6UL_SD_PAD_CTRL,
549 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | TX6UL_SD_PAD_CTRL,
550 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | TX6UL_SD_PAD_CTRL,
551 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | TX6UL_SD_PAD_CTRL,
553 MX6_PAD_NAND_CE1_B__GPIO4_IO14 | TX6UL_SD_PAD_CTRL,
556 #ifdef CONFIG_TX6_EMMC
557 static const iomux_v3_cfg_t mmc1_pads[] = {
558 MX6_PAD_NAND_WE_B__USDHC2_CMD | TX6UL_SD_PAD_CTRL,
559 MX6_PAD_NAND_RE_B__USDHC2_CLK | TX6UL_SD_PAD_CTRL,
560 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | TX6UL_SD_PAD_CTRL,
561 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | TX6UL_SD_PAD_CTRL,
562 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | TX6UL_SD_PAD_CTRL,
563 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | TX6UL_SD_PAD_CTRL,
565 MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
570 static struct tx6ul_esdhc_cfg {
571 const iomux_v3_cfg_t *pads;
573 enum mxc_clock clkid;
574 struct fsl_esdhc_cfg cfg;
576 } tx6ul_esdhc_cfg[] = {
577 #ifdef CONFIG_TX6_EMMC
580 .num_pads = ARRAY_SIZE(mmc1_pads),
581 .clkid = MXC_ESDHC2_CLK,
583 .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
591 .num_pads = ARRAY_SIZE(mmc0_pads),
592 .clkid = MXC_ESDHC_CLK,
594 .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
597 .cd_gpio = TX6UL_SD1_CD_GPIO,
601 static inline struct tx6ul_esdhc_cfg *to_tx6ul_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
603 return container_of(cfg, struct tx6ul_esdhc_cfg, cfg);
606 int board_mmc_getcd(struct mmc *mmc)
608 struct tx6ul_esdhc_cfg *cfg = to_tx6ul_esdhc_cfg(mmc->priv);
610 if (cfg->cd_gpio < 0)
613 debug("SD card %d is %spresent (GPIO %d)\n",
614 cfg - tx6ul_esdhc_cfg,
615 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
617 return !gpio_get_value(cfg->cd_gpio);
620 int board_mmc_init(bd_t *bis)
624 debug("%s@%d: \n", __func__, __LINE__);
626 #ifndef CONFIG_ENV_IS_IN_MMC
627 if (!(gd->flags & GD_FLG_ENV_READY)) {
628 printf("deferred ...");
632 for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) {
634 struct tx6ul_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
637 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
638 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
640 if (cfg->cd_gpio >= 0) {
641 ret = gpio_request_one(cfg->cd_gpio,
642 GPIOFLAG_INPUT, "MMC CD");
644 printf("Error %d requesting GPIO%d_%d\n",
645 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
650 debug("%s: Initializing MMC slot %d\n", __func__, i);
651 fsl_esdhc_initialize(bis, &cfg->cfg);
653 mmc = find_mmc_device(i);
656 if (board_mmc_getcd(mmc))
661 #endif /* CONFIG_FSL_ESDHC */
670 static inline int calc_blink_rate(void)
672 if (!tx6ul_temp_check_enabled)
673 return CONFIG_SYS_HZ;
675 return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
676 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
677 (TEMPERATURE_HOT - TEMPERATURE_MIN);
680 void show_activity(int arg)
682 static int led_state = LED_STATE_INIT;
683 static int blink_rate;
693 ret = gpio_set_value(TX6UL_LED_GPIO, 1);
695 led_state = LED_STATE_ERR;
697 led_state = LED_STATE_ON;
698 blink_rate = calc_blink_rate();
703 if (get_timer(last) > blink_rate) {
704 blink_rate = calc_blink_rate();
705 last = get_timer_masked();
706 if (led_state == LED_STATE_ON) {
707 gpio_set_value(TX6UL_LED_GPIO, 0);
709 gpio_set_value(TX6UL_LED_GPIO, 1);
711 led_state = 1 - led_state;
717 static const iomux_v3_cfg_t stk5_jtag_pads[] = {
718 MX6_PAD_JTAG_MOD__SJC_MOD | TX6UL_GPIO_IN_PAD_CTRL,
719 MX6_PAD_JTAG_TCK__SJC_TCK | TX6UL_GPIO_IN_PAD_CTRL,
720 MX6_PAD_JTAG_TRST_B__SJC_TRSTB | TX6UL_GPIO_IN_PAD_CTRL,
721 MX6_PAD_JTAG_TDI__SJC_TDI | TX6UL_GPIO_IN_PAD_CTRL,
722 MX6_PAD_JTAG_TDO__SJC_TDO | TX6UL_GPIO_OUT_PAD_CTRL,
723 MX6_PAD_JTAG_TMS__SJC_TMS | TX6UL_GPIO_IN_PAD_CTRL,
726 static const iomux_v3_cfg_t stk5_pads[] = {
727 /* SW controlled LED on STK5 baseboard */
728 MX6_PAD_SNVS_TAMPER9__GPIO5_IO09,
730 /* I2C bus on DIMM pins 40/41 */
731 MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
732 MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
734 /* TSC200x PEN IRQ */
735 MX6_PAD_JTAG_TMS__GPIO1_IO11 | TX6UL_GPIO_IN_PAD_CTRL,
737 /* EDT-FT5x06 Polytouch panel */
738 MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | TX6UL_GPIO_IN_PAD_CTRL, /* IRQ */
739 MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 | TX6UL_GPIO_OUT_PAD_CTRL, /* RESET */
740 MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | TX6UL_GPIO_OUT_PAD_CTRL, /* WAKE */
743 MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
744 MX6_PAD_GPIO1_IO03__USB_OTG2_OC | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
747 MX6_PAD_UART3_CTS_B__GPIO1_IO26 | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
748 MX6_PAD_UART3_RTS_B__GPIO1_IO27 | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
751 static const struct gpio stk5_gpios[] = {
752 { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
754 { IMX_GPIO_NR(1, 27), GPIOFLAG_INPUT, "USBOTG OC", },
755 { IMX_GPIO_NR(1, 26), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
759 vidinfo_t panel_info = {
760 /* set to max. size supported by SoC */
764 .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
767 static struct fb_videomode tx6ul_fb_modes[] = {
768 #ifndef CONFIG_SYS_LVDS_IF
770 /* Standard VGA timing */
775 .pixclock = KHZ2PICOS(25175),
782 .sync = FB_SYNC_CLK_LAT_FALL,
785 /* Emerging ETV570 640 x 480 display. Syncs low active,
786 * DE high active, 115.2 mm x 86.4 mm display area
787 * VGA compatible timing
793 .pixclock = KHZ2PICOS(25175),
800 .sync = FB_SYNC_CLK_LAT_FALL,
803 /* Emerging ET0350G0DH6 320 x 240 display.
804 * 70.08 mm x 52.56 mm display area.
810 .pixclock = KHZ2PICOS(6500),
811 .left_margin = 68 - 34,
814 .upper_margin = 18 - 3,
817 .sync = FB_SYNC_CLK_LAT_FALL,
820 /* Emerging ET0430G0DH6 480 x 272 display.
821 * 95.04 mm x 53.856 mm display area.
827 .pixclock = KHZ2PICOS(9000),
836 /* Emerging ET0500G0DH6 800 x 480 display.
837 * 109.6 mm x 66.4 mm display area.
843 .pixclock = KHZ2PICOS(33260),
844 .left_margin = 216 - 128,
846 .right_margin = 1056 - 800 - 216,
847 .upper_margin = 35 - 2,
849 .lower_margin = 525 - 480 - 35,
850 .sync = FB_SYNC_CLK_LAT_FALL,
853 /* Emerging ETQ570G0DH6 320 x 240 display.
854 * 115.2 mm x 86.4 mm display area.
860 .pixclock = KHZ2PICOS(6400),
864 .upper_margin = 16, /* 15 according to datasheet */
865 .vsync_len = 3, /* TVP -> 1>x>5 */
866 .lower_margin = 4, /* 4.5 according to datasheet */
867 .sync = FB_SYNC_CLK_LAT_FALL,
870 /* Emerging ET0700G0DH6 800 x 480 display.
871 * 152.4 mm x 91.44 mm display area.
877 .pixclock = KHZ2PICOS(33260),
878 .left_margin = 216 - 128,
880 .right_margin = 1056 - 800 - 216,
881 .upper_margin = 35 - 2,
883 .lower_margin = 525 - 480 - 35,
884 .sync = FB_SYNC_CLK_LAT_FALL,
887 /* Emerging ET070001DM6 800 x 480 display.
888 * 152.4 mm x 91.44 mm display area.
890 .name = "ET070001DM6",
894 .pixclock = KHZ2PICOS(33260),
895 .left_margin = 216 - 128,
897 .right_margin = 1056 - 800 - 216,
898 .upper_margin = 35 - 2,
900 .lower_margin = 525 - 480 - 35,
905 /* HannStar HSD100PXN1
906 * 202.7m mm x 152.06 mm display area.
908 .name = "HSD100PXN1",
912 .pixclock = KHZ2PICOS(65000),
919 .sync = FB_SYNC_CLK_LAT_FALL,
923 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
931 .sync = FB_SYNC_CLK_LAT_FALL,
935 static int lcd_enabled = 1;
936 static int lcd_bl_polarity;
938 static int lcd_backlight_polarity(void)
940 return lcd_bl_polarity;
943 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
946 MX6_PAD_LCD_RESET__GPIO3_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
947 /* LCD POWER_ENABLE */
948 MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
949 /* LCD Backlight (PWM) */
950 MX6_PAD_NAND_DQS__GPIO4_IO16 | TX6UL_GPIO_OUT_PAD_CTRL,
952 MX6_PAD_LCD_DATA00__LCDIF_DATA00,
953 MX6_PAD_LCD_DATA01__LCDIF_DATA01,
954 MX6_PAD_LCD_DATA02__LCDIF_DATA02,
955 MX6_PAD_LCD_DATA03__LCDIF_DATA03,
956 MX6_PAD_LCD_DATA04__LCDIF_DATA04,
957 MX6_PAD_LCD_DATA05__LCDIF_DATA05,
958 MX6_PAD_LCD_DATA06__LCDIF_DATA06,
959 MX6_PAD_LCD_DATA07__LCDIF_DATA07,
960 MX6_PAD_LCD_DATA08__LCDIF_DATA08,
961 MX6_PAD_LCD_DATA09__LCDIF_DATA09,
962 MX6_PAD_LCD_DATA10__LCDIF_DATA10,
963 MX6_PAD_LCD_DATA11__LCDIF_DATA11,
964 MX6_PAD_LCD_DATA12__LCDIF_DATA12,
965 MX6_PAD_LCD_DATA13__LCDIF_DATA13,
966 MX6_PAD_LCD_DATA14__LCDIF_DATA14,
967 MX6_PAD_LCD_DATA15__LCDIF_DATA15,
968 MX6_PAD_LCD_DATA16__LCDIF_DATA16,
969 MX6_PAD_LCD_DATA17__LCDIF_DATA17,
970 MX6_PAD_LCD_DATA18__LCDIF_DATA18,
971 MX6_PAD_LCD_DATA19__LCDIF_DATA19,
972 MX6_PAD_LCD_DATA20__LCDIF_DATA20,
973 MX6_PAD_LCD_DATA21__LCDIF_DATA21,
974 MX6_PAD_LCD_DATA22__LCDIF_DATA22,
975 MX6_PAD_LCD_DATA23__LCDIF_DATA23,
976 MX6_PAD_LCD_HSYNC__LCDIF_HSYNC, /* HSYNC */
977 MX6_PAD_LCD_VSYNC__LCDIF_VSYNC, /* VSYNC */
978 MX6_PAD_LCD_ENABLE__LCDIF_ENABLE, /* OE_ACD */
979 MX6_PAD_LCD_CLK__LCDIF_CLK, /* LSCLK */
983 static const struct gpio stk5_lcd_gpios[] = {
984 { TX6UL_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
985 { TX6UL_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
986 { TX6UL_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
989 /* run with valid env from NAND/eMMC */
990 void lcd_enable(void)
993 * global variable from common/lcd.c
994 * Set to 0 here to prevent messages from going to LCD
995 * rather than serial console
1000 karo_load_splashimage(1);
1002 debug("Switching LCD on\n");
1003 gpio_set_value(TX6UL_LCD_PWR_GPIO, 1);
1005 gpio_set_value(TX6UL_LCD_RST_GPIO, 1);
1007 gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
1008 lcd_backlight_polarity());
1012 static void lcd_disable(void)
1015 printf("Disabling LCD\n");
1016 panel_info.vl_row = 0;
1021 void lcd_ctrl_init(void *lcdbase)
1023 int color_depth = 24;
1024 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1028 struct fb_videomode *p = &tx6ul_fb_modes[0];
1029 struct fb_videomode fb_mode;
1030 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1033 debug("LCD disabled\n");
1037 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1039 setenv("splashimage", NULL);
1043 karo_fdt_move_fdt();
1044 lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1046 if (video_mode == NULL) {
1051 if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1053 debug("Using video mode from FDT\n");
1055 if (fb_mode.xres > panel_info.vl_col ||
1056 fb_mode.yres > panel_info.vl_row) {
1057 printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1058 fb_mode.xres, fb_mode.yres,
1059 panel_info.vl_col, panel_info.vl_row);
1064 if (p->name != NULL)
1065 debug("Trying compiled-in video modes\n");
1066 while (p->name != NULL) {
1067 if (strcmp(p->name, vm) == 0) {
1068 debug("Using video mode: '%s'\n", p->name);
1075 debug("Trying to decode video_mode: '%s'\n", vm);
1076 while (*vm != '\0') {
1077 if (*vm >= '0' && *vm <= '9') {
1080 val = simple_strtoul(vm, &end, 0);
1083 if (val > panel_info.vl_col)
1084 val = panel_info.vl_col;
1086 panel_info.vl_col = val;
1088 } else if (!yres_set) {
1089 if (val > panel_info.vl_row)
1090 val = panel_info.vl_row;
1092 panel_info.vl_row = val;
1094 } else if (!bpp_set) {
1105 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1106 end - vm, vm, color_depth);
1109 } else if (!refresh_set) {
1136 if (p->xres == 0 || p->yres == 0) {
1137 printf("Invalid video mode: %s\n", getenv("video_mode"));
1139 printf("Supported video modes are:");
1140 for (p = &tx6ul_fb_modes[0]; p->name != NULL; p++) {
1141 printf(" %s", p->name);
1146 if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1147 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1148 p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1152 panel_info.vl_col = p->xres;
1153 panel_info.vl_row = p->yres;
1155 switch (color_depth) {
1157 panel_info.vl_bpix = LCD_COLOR8;
1160 panel_info.vl_bpix = LCD_COLOR16;
1163 panel_info.vl_bpix = LCD_COLOR32;
1166 p->pixclock = KHZ2PICOS(refresh *
1167 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1168 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1170 debug("Pixel clock set to %lu.%03lu MHz\n",
1171 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1173 if (p != &fb_mode) {
1176 debug("Creating new display-timing node from '%s'\n",
1178 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1180 printf("Failed to create new display-timing node from '%s': %d\n",
1184 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1185 imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1186 ARRAY_SIZE(stk5_lcd_pads));
1188 debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
1189 color_depth, refresh);
1191 if (karo_load_splashimage(0) == 0) {
1194 /* setup env variable for mxsfb display driver */
1195 snprintf(vmode, sizeof(vmode),
1196 "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
1197 p->xres, p->yres, p->left_margin, p->right_margin,
1198 p->upper_margin, p->lower_margin, p->hsync_len,
1199 p->vsync_len, p->sync, p->pixclock, color_depth);
1200 setenv("videomode", vmode);
1202 debug("Initializing LCD controller\n");
1205 setenv("videomode", NULL);
1207 debug("Skipping initialization of LCD controller\n");
1211 #define lcd_enabled 0
1212 #endif /* CONFIG_LCD */
1214 #ifndef CONFIG_ENV_IS_IN_MMC
1215 static void tx6ul_mmc_init(void)
1218 if (board_mmc_init(gd->bd) < 0)
1219 cpu_mmc_init(gd->bd);
1220 print_mmc_devices(',');
1223 static inline void tx6ul_mmc_init(void)
1228 static void stk5_board_init(void)
1232 ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1234 printf("Failed to request stk5_gpios: %d\n", ret);
1237 imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1238 if (getenv_yesno("jtag_enable") != 0) {
1239 /* true if unset or set to one of: 'yYtT1' */
1240 imx_iomux_v3_setup_multiple_pads(stk5_jtag_pads, ARRAY_SIZE(stk5_jtag_pads));
1242 debug("%s@%d: \n", __func__, __LINE__);
1245 static void stk5v3_board_init(void)
1247 debug("%s@%d: \n", __func__, __LINE__);
1249 debug("%s@%d: \n", __func__, __LINE__);
1253 static void stk5v5_board_init(void)
1260 ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
1261 "Flexcan Transceiver");
1263 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1267 imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 |
1268 TX6UL_GPIO_OUT_PAD_CTRL);
1271 static void tx6ul_set_cpu_clock(void)
1273 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1275 if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1278 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1279 printf("%s detected; skipping cpu clock change\n",
1280 (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1283 if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1284 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1285 printf("CPU clock set to %lu.%03lu MHz\n",
1286 cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1288 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1292 int board_late_init(void)
1294 const char *baseboard;
1296 debug("%s@%d: \n", __func__, __LINE__);
1300 if (tx6ul_temp_check_enabled)
1301 check_cpu_temperature(1);
1303 tx6ul_set_cpu_clock();
1306 setenv_ulong("safeboot", 1);
1307 else if (wrsr & WRSR_TOUT)
1308 setenv_ulong("wdreset", 1);
1310 karo_fdt_move_fdt();
1312 baseboard = getenv("baseboard");
1316 printf("Baseboard: %s\n", baseboard);
1318 if (strncmp(baseboard, "stk5", 4) == 0) {
1319 if ((strlen(baseboard) == 4) ||
1320 strcmp(baseboard, "stk5-v3") == 0) {
1321 stk5v3_board_init();
1322 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1323 const char *otg_mode = getenv("otg_mode");
1325 if (otg_mode && strcmp(otg_mode, "host") == 0) {
1326 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1327 otg_mode, baseboard);
1328 setenv("otg_mode", "none");
1330 stk5v5_board_init();
1332 printf("WARNING: Unsupported STK5 board rev.: %s\n",
1335 } else if (strncmp(baseboard, "ulmb-", 5) == 0) {
1336 const char *otg_mode = getenv("otg_mode");
1338 if (otg_mode && strcmp(otg_mode, "host") == 0) {
1339 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1340 otg_mode, baseboard);
1341 setenv("otg_mode", "none");
1345 printf("WARNING: Unsupported baseboard: '%s'\n",
1352 debug("%s@%d: \n", __func__, __LINE__);
1358 #ifdef CONFIG_FEC_MXC
1364 static void tx6ul_init_mac(void)
1367 const char *baseboard = getenv("baseboard");
1369 imx_get_mac_from_fuse(0, mac);
1370 if (!is_valid_ethaddr(mac)) {
1371 printf("No valid MAC address programmed\n");
1374 printf("MAC addr from fuse: %pM\n", mac);
1375 if (!getenv("ethaddr"))
1376 eth_setenv_enetaddr("ethaddr", mac);
1378 if (!baseboard || strncmp(baseboard, "stk5", 4) == 0) {
1379 setenv("eth1addr", NULL);
1382 if (getenv("eth1addr"))
1384 imx_get_mac_from_fuse(1, mac);
1385 eth_setenv_enetaddr("eth1addr", mac);
1388 int board_eth_init(bd_t *bis)
1394 /* delay at least 21ms for the PHY internal POR signal to deassert */
1397 imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads,
1398 ARRAY_SIZE(tx6ul_enet1_pads));
1400 /* Deassert RESET to the external phys */
1401 gpio_set_value(TX6UL_FEC_RST_GPIO, 1);
1403 if (getenv("ethaddr")) {
1404 ret = fecmxc_initialize_multi(bis, 0, 0, ENET_BASE_ADDR);
1406 printf("failed to initialize FEC0: %d\n", ret);
1410 if (getenv("eth1addr")) {
1411 ret = gpio_request_array(tx6ul_fec2_gpios,
1412 ARRAY_SIZE(tx6ul_fec2_gpios));
1414 printf("Failed to request tx6ul_fec2_gpios: %d\n", ret);
1416 imx_iomux_v3_setup_multiple_pads(tx6ul_enet2_pads,
1417 ARRAY_SIZE(tx6ul_enet2_pads));
1419 writel(0x00100000, 0x020c80e4); /* assert ENET2_125M_EN */
1421 /* Minimum PHY reset duration */
1423 gpio_set_value(TX6UL_FEC2_RST_GPIO, 1);
1424 /* Wait for PHY internal POR to finish */
1427 ret = fecmxc_initialize_multi(bis, 1, 2, ENET2_BASE_ADDR);
1429 printf("failed to initialize FEC1: %d\n", ret);
1435 #endif /* CONFIG_FEC_MXC */
1437 #ifdef CONFIG_SERIAL_TAG
1438 void get_board_serial(struct tag_serialnr *serialnr)
1440 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1441 struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1443 serialnr->low = readl(&fuse->cfg0);
1444 serialnr->high = readl(&fuse->cfg1);
1448 #if defined(CONFIG_OF_BOARD_SETUP)
1449 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1450 #include <jffs2/jffs2.h>
1451 #include <mtd_node.h>
1452 static struct node_info nodes[] = {
1453 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1456 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1459 static const char *tx6ul_touchpanels[] = {
1465 int ft_board_setup(void *blob, bd_t *bd)
1467 const char *baseboard = getenv("baseboard");
1468 int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1469 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1472 ret = fdt_increase_size(blob, 4096);
1474 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1478 karo_fdt_enable_node(blob, "stk5led", 0);
1480 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1482 karo_fdt_fixup_touchpanel(blob, tx6ul_touchpanels,
1483 ARRAY_SIZE(tx6ul_touchpanels));
1484 karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1485 karo_fdt_fixup_flexcan(blob, stk5_v5);
1487 karo_fdt_update_fb_mode(blob, video_mode);
1491 #endif /* CONFIG_OF_BOARD_SETUP */