board/karo/tx6/tx6ul.c

   1 /*
   2  * Copyright (C) 2015 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  *
   6  */
   7 #include <common.h>
   8 #include <errno.h>
   9 #include <libfdt.h>
  10 #include <fdt_support.h>
  11 #include <lcd.h>
  12 #include <netdev.h>
  13 #include <mmc.h>
  14 #include <fsl_esdhc.h>
  15 #include <video_fb.h>
  16 #include <ipu.h>
  17 #include <mxcfb.h>
  18 #include <i2c.h>
  19 #include <linux/fb.h>
  20 #include <asm/io.h>
  21 #include <asm/gpio.h>
  22 #include <asm/arch/mx6-pins.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/hab.h>
  25 #include <asm/arch/imx-regs.h>
  26 #include <asm/arch/crm_regs.h>
  27 #include <asm/arch/sys_proto.h>
  28
  29 #include "../common/karo.h"
  30 #include "pmic.h"
  31
  32 #define __data __attribute__((section(".data")))
  33
  34 #define TX6UL_FEC_RST_GPIO              IMX_GPIO_NR(5, 6)
  35 #define TX6UL_FEC_PWR_GPIO              IMX_GPIO_NR(5, 7)
  36 #define TX6UL_FEC_INT_GPIO              IMX_GPIO_NR(5, 5)
  37
  38 #define TX6UL_FEC2_RST_GPIO             IMX_GPIO_NR(4, 28)
  39 #define TX6UL_FEC2_INT_GPIO             IMX_GPIO_NR(4, 27)
  40
  41 #define TX6UL_LED_GPIO                  IMX_GPIO_NR(5, 9)
  42
  43 #define TX6UL_LCD_PWR_GPIO              IMX_GPIO_NR(5, 4)
  44 #define TX6UL_LCD_RST_GPIO              IMX_GPIO_NR(3, 4)
  45 #define TX6UL_LCD_BACKLIGHT_GPIO        IMX_GPIO_NR(4, 16)
  46
  47 #ifdef CONFIG_SYS_I2C_SOFT
  48 #define TX6UL_I2C1_SCL_GPIO             CONFIG_SOFT_I2C_GPIO_SCL
  49 #define TX6UL_I2C1_SDA_GPIO             CONFIG_SOFT_I2C_GPIO_SDA
  50 #endif
  51
  52 #define TX6UL_SD1_CD_GPIO               IMX_GPIO_NR(4, 14)
  53
  54 #ifdef CONFIG_MX6_TEMPERATURE_MIN
  55 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
  56 #else
  57 #define TEMPERATURE_MIN                 (-40)
  58 #endif
  59 #ifdef CONFIG_MX6_TEMPERATURE_HOT
  60 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
  61 #else
  62 #define TEMPERATURE_HOT                 80
  63 #endif
  64
  65 DECLARE_GLOBAL_DATA_PTR;
  66
  67 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  68
  69 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
  70 #ifdef CONFIG_SECURE_BOOT
  71 char __csf_data[0] __attribute__((section(".__csf_data")));
  72 #endif
  73
  74 #define TX6UL_DEFAULT_PAD_CTRL  MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |      \
  75                                         PAD_CTL_SPEED_MED |             \
  76                                         PAD_CTL_DSE_40ohm |             \
  77                                         PAD_CTL_SRE_FAST)
  78 #define TX6UL_I2C_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |       \
  79                                         PAD_CTL_ODE |                   \
  80                                         PAD_CTL_HYS |                   \
  81                                         PAD_CTL_SPEED_LOW |             \
  82                                         PAD_CTL_DSE_34ohm |             \
  83                                         PAD_CTL_SRE_FAST)
  84 #define TX6UL_I2C_GPIO_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |       \
  85                                         PAD_CTL_HYS |                   \
  86                                         PAD_CTL_DSE_34ohm |             \
  87                                         PAD_CTL_SPEED_MED)
  88 #define TX6UL_ENET_PAD_CTRL     MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |       \
  89                                         PAD_CTL_DSE_120ohm |            \
  90                                         PAD_CTL_PUS_100K_UP |           \
  91                                         PAD_CTL_SRE_FAST)
  92 #define TX6UL_GPIO_OUT_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |        \
  93                                         PAD_CTL_DSE_60ohm |             \
  94                                         PAD_CTL_SRE_SLOW)
  95 #define TX6UL_GPIO_IN_PAD_CTRL  MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |        \
  96                                         PAD_CTL_PUS_47K_UP)
  97
  98
  99 static const iomux_v3_cfg_t const tx6ul_pads[] = {
 100         /* UART pads */
 101 #if CONFIG_MXC_UART_BASE == UART1_BASE
 102         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
 103         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
 104         MX6_PAD_UART1_RTS_B__UART1_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
 105         MX6_PAD_UART1_CTS_B__UART1_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
 106 #endif
 107 #if CONFIG_MXC_UART_BASE == UART2_BASE
 108         MX6_PAD_UART2_TX_DATA__UART2_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
 109         MX6_PAD_UART2_RX_DATA__UART2_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
 110         MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
 111         MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
 112 #endif
 113 #if CONFIG_MXC_UART_BASE == UART5_BASE
 114         MX6_PAD_GPIO1_IO04__UART5_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
 115         MX6_PAD_GPIO1_IO05__UART5_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
 116         MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
 117         MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
 118 #endif
 119         /* FEC PHY GPIO functions */
 120         MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY POWER */
 121         MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY RESET */
 122         MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | TX6UL_GPIO_IN_PAD_CTRL, /* PHY INT */
 123 };
 124
 125 static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = {
 126         /* FEC functions */
 127         MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm |
 128                                                      PAD_CTL_SPEED_LOW),
 129         MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
 130                                                       PAD_CTL_DSE_120ohm |
 131                                                       PAD_CTL_SPEED_LOW),
 132         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |
 133                                                      PAD_CTL_DSE_80ohm |
 134                                                      PAD_CTL_SRE_SLOW),
 135
 136         MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | TX6UL_ENET_PAD_CTRL,
 137         MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | TX6UL_ENET_PAD_CTRL,
 138         MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | TX6UL_ENET_PAD_CTRL,
 139         MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | TX6UL_ENET_PAD_CTRL,
 140         MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | TX6UL_ENET_PAD_CTRL,
 141         MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | TX6UL_ENET_PAD_CTRL,
 142         MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | TX6UL_ENET_PAD_CTRL,
 143 };
 144
 145 static const iomux_v3_cfg_t const tx6ul_enet2_pads[] = {
 146         MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |
 147                                                             PAD_CTL_DSE_80ohm |
 148                                                             PAD_CTL_SRE_SLOW),
 149         MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | TX6UL_ENET_PAD_CTRL,
 150         MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | TX6UL_ENET_PAD_CTRL,
 151         MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | TX6UL_ENET_PAD_CTRL,
 152         MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | TX6UL_ENET_PAD_CTRL,
 153         MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | TX6UL_ENET_PAD_CTRL,
 154         MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | TX6UL_ENET_PAD_CTRL,
 155         MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | TX6UL_ENET_PAD_CTRL,
 156 };
 157
 158 static const iomux_v3_cfg_t const tx6ul_i2c_pads[] = {
 159         /* internal I2C */
 160         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
 161                         TX6UL_I2C_PAD_CTRL, /* I2C SCL */
 162         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
 163                         TX6UL_I2C_PAD_CTRL, /* I2C SDA */
 164 };
 165
 166 static const iomux_v3_cfg_t const tx6ul_i2c_gpio_pads[] = {
 167         /* internal I2C set up for I2C bus recovery */
 168         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
 169                         TX6UL_I2C_PAD_CTRL, /* I2C SCL */
 170         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
 171                         TX6UL_I2C_PAD_CTRL, /* I2C SDA */
 172 };
 173
 174 static const struct gpio const tx6ul_gpios[] = {
 175 #ifdef CONFIG_SYS_I2C_SOFT
 176         /* These two entries are used to forcefully reinitialize the I2C bus */
 177         { TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
 178         { TX6UL_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
 179 #endif
 180         { TX6UL_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 181         { TX6UL_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 182         { TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
 183 };
 184
 185 static const struct gpio const tx6ul_fec2_gpios[] = {
 186         { TX6UL_FEC2_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC2 PHY RESET", },
 187         { TX6UL_FEC2_INT_GPIO, GPIOFLAG_INPUT, "FEC2 PHY INT", },
 188 };
 189
 190 #define GPIO_DR 0
 191 #define GPIO_DIR 4
 192 #define GPIO_PSR 8
 193
 194 /* run with default environment */
 195 #if defined(TX6UL_I2C1_SCL_GPIO) && defined(TX6UL_I2C1_SDA_GPIO)
 196 #define SCL_BANK        (TX6UL_I2C1_SCL_GPIO / 32)
 197 #define SDA_BANK        (TX6UL_I2C1_SDA_GPIO / 32)
 198 #define SCL_BIT         (1 << (TX6UL_I2C1_SCL_GPIO % 32))
 199 #define SDA_BIT         (1 << (TX6UL_I2C1_SDA_GPIO % 32))
 200
 201 static void * const gpio_ports[] = {
 202         (void *)GPIO1_BASE_ADDR,
 203         (void *)GPIO2_BASE_ADDR,
 204         (void *)GPIO3_BASE_ADDR,
 205         (void *)GPIO4_BASE_ADDR,
 206         (void *)GPIO5_BASE_ADDR,
 207 };
 208
 209 static void tx6ul_i2c_recover(void)
 210 {
 211         int i;
 212         int bad = 0;
 213         struct gpio_regs *scl_regs = gpio_ports[SCL_BANK];
 214         struct gpio_regs *sda_regs = gpio_ports[SDA_BANK];
 215
 216         if ((readl(&scl_regs->gpio_psr) & SCL_BIT) &&
 217             (readl(&sda_regs->gpio_psr) & SDA_BIT))
 218                 return;
 219
 220         debug("Clearing I2C bus\n");
 221         if (!(readl(&scl_regs->gpio_psr) & SCL_BIT)) {
 222                 printf("I2C SCL stuck LOW\n");
 223                 bad++;
 224
 225                 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
 226                 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
 227
 228                 imx_iomux_v3_setup_pad(MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 |
 229                                        MUX_CFG_SION | TX6UL_GPIO_OUT_PAD_CTRL);
 230         }
 231         if (!(readl(&sda_regs->gpio_psr) & SDA_BIT)) {
 232                 printf("I2C SDA stuck LOW\n");
 233                 bad++;
 234
 235                 clrbits_le32(&sda_regs->gpio_dir, SDA_BIT);
 236                 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
 237                 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
 238
 239                 imx_iomux_v3_setup_multiple_pads(tx6ul_i2c_gpio_pads,
 240                                                  ARRAY_SIZE(tx6ul_i2c_gpio_pads));
 241
 242                 udelay(5);
 243
 244                 for (i = 0; i < 18; i++) {
 245                         u32 reg = readl(&scl_regs->gpio_dr) ^ SCL_BIT;
 246
 247                         debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
 248                         writel(reg, &scl_regs->gpio_dr);
 249                         udelay(5);
 250                         if (reg & SCL_BIT) {
 251                                 if (readl(&sda_regs->gpio_psr) & SDA_BIT)
 252                                         break;
 253                                 if (!(readl(&scl_regs->gpio_psr) & SCL_BIT))
 254                                         break;
 255                                 break;
 256                         }
 257                 }
 258         }
 259         if (bad) {
 260                 bool scl = !!(readl(&scl_regs->gpio_psr) & SCL_BIT);
 261                 bool sda = !!(readl(&sda_regs->gpio_psr) & SDA_BIT);
 262
 263                 if (scl && sda) {
 264                         printf("I2C bus recovery succeeded\n");
 265                 } else {
 266                         printf("I2C bus recovery FAILED: SCL: %d SDA: %d\n",
 267                                scl, sda);
 268                 }
 269                 imx_iomux_v3_setup_multiple_pads(tx6ul_i2c_pads,
 270                                                  ARRAY_SIZE(tx6ul_i2c_pads));
 271         }
 272 }
 273 #else
 274 static inline void tx6ul_i2c_recover(void)
 275 {
 276 }
 277 #endif
 278
 279 /* placed in section '.data' to prevent overwriting relocation info
 280  * overlayed with bss
 281  */
 282 static u32 wrsr __data;
 283
 284 #define WRSR_POR                        (1 << 4)
 285 #define WRSR_TOUT                       (1 << 1)
 286 #define WRSR_SFTW                       (1 << 0)
 287
 288 static void print_reset_cause(void)
 289 {
 290         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 291         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 292         u32 srsr;
 293         char *dlm = "";
 294
 295         printf("Reset cause: ");
 296
 297         srsr = readl(&src_regs->srsr);
 298         wrsr = readw(wdt_base + 4);
 299
 300         if (wrsr & WRSR_POR) {
 301                 printf("%sPOR", dlm);
 302                 dlm = " | ";
 303         }
 304         if (srsr & 0x00004) {
 305                 printf("%sCSU", dlm);
 306                 dlm = " | ";
 307         }
 308         if (srsr & 0x00008) {
 309                 printf("%sIPP USER", dlm);
 310                 dlm = " | ";
 311         }
 312         if (srsr & 0x00010) {
 313                 if (wrsr & WRSR_SFTW) {
 314                         printf("%sSOFT", dlm);
 315                         dlm = " | ";
 316                 }
 317                 if (wrsr & WRSR_TOUT) {
 318                         printf("%sWDOG", dlm);
 319                         dlm = " | ";
 320                 }
 321         }
 322         if (srsr & 0x00020) {
 323                 printf("%sJTAG HIGH-Z", dlm);
 324                 dlm = " | ";
 325         }
 326         if (srsr & 0x00040) {
 327                 printf("%sJTAG SW", dlm);
 328                 dlm = " | ";
 329         }
 330         if (srsr & 0x10000) {
 331                 printf("%sWARM BOOT", dlm);
 332                 dlm = " | ";
 333         }
 334         if (dlm[0] == '\0')
 335                 printf("unknown");
 336
 337         printf("\n");
 338 }
 339
 340 #ifdef CONFIG_IMX6_THERMAL
 341 #include <thermal.h>
 342 #include <imx_thermal.h>
 343 #include <fuse.h>
 344
 345 static void print_temperature(void)
 346 {
 347         struct udevice *thermal_dev;
 348         int cpu_tmp, minc, maxc, ret;
 349         char const *grade_str;
 350         static u32 __data thermal_calib;
 351
 352         puts("Temperature: ");
 353         switch (get_cpu_temp_grade(&minc, &maxc)) {
 354         case TEMP_AUTOMOTIVE:
 355                 grade_str = "Automotive";
 356                 break;
 357         case TEMP_INDUSTRIAL:
 358                 grade_str = "Industrial";
 359                 break;
 360         case TEMP_EXTCOMMERCIAL:
 361                 grade_str = "Extended Commercial";
 362                 break;
 363         default:
 364                 grade_str = "Commercial";
 365         }
 366         printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
 367         ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
 368         if (ret == 0) {
 369                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
 370
 371                 if (ret == 0)
 372                         printf(" at %dC", cpu_tmp);
 373                 else
 374                         puts(" - failed to read sensor data");
 375         } else {
 376                 puts(" - no sensor device found");
 377         }
 378
 379         if (fuse_read(1, 6, &thermal_calib) == 0) {
 380                 printf(" - calibration data 0x%08x\n", thermal_calib);
 381         } else {
 382                 puts(" - Failed to read thermal calib fuse\n");
 383         }
 384 }
 385 #else
 386 static inline void print_temperature(void)
 387 {
 388 }
 389 #endif
 390
 391 int checkboard(void)
 392 {
 393         u32 cpurev = get_cpu_rev();
 394         char *cpu_str = "?";
 395
 396         if (is_cpu_type(MXC_CPU_MX6SL))
 397                 cpu_str = "SL";
 398         else if (is_cpu_type(MXC_CPU_MX6DL))
 399                 cpu_str = "DL";
 400         else if (is_cpu_type(MXC_CPU_MX6SOLO))
 401                 cpu_str = "SOLO";
 402         else if (is_cpu_type(MXC_CPU_MX6Q))
 403                 cpu_str = "Q";
 404         else if (is_cpu_type(MXC_CPU_MX6UL))
 405                 cpu_str = "UL";
 406         else if (is_cpu_type(MXC_CPU_MX6ULL))
 407                 cpu_str = "ULL";
 408
 409         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
 410                 cpu_str,
 411                 (cpurev & 0x000F0) >> 4,
 412                 (cpurev & 0x0000F) >> 0,
 413                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 414
 415         print_temperature();
 416         print_reset_cause();
 417 #ifdef CONFIG_MX6_TEMPERATURE_HOT
 418         check_cpu_temperature(1);
 419 #endif
 420         tx6ul_i2c_recover();
 421         return 0;
 422 }
 423
 424 /* serial port not initialized at this point */
 425 int board_early_init_f(void)
 426 {
 427         return 0;
 428 }
 429
 430 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 431 static bool tx6ul_temp_check_enabled = true;
 432 #else
 433 #define tx6ul_temp_check_enabled        0
 434 #endif
 435
 436 static inline u8 tx6ul_mem_suffix(void)
 437 {
 438         return '0' + CONFIG_SYS_SDRAM_CHIP_SIZE / 1024 * 2 +
 439                 IS_ENABLED(CONFIG_TX6_EMMC);
 440 }
 441
 442 #ifdef CONFIG_RN5T567
 443 /* PMIC settings */
 444 #define VDD_RTC_VAL             rn5t_mV_to_regval_rtc(3000)
 445 #define VDD_CORE_VAL            rn5t_mV_to_regval(1300)         /* DCDC1 */
 446 #define VDD_CORE_VAL_LP         rn5t_mV_to_regval(900)
 447 #define VDD_DDR_VAL             rn5t_mV_to_regval(1350)         /* DCDC3 */
 448 #define VDD_DDR_VAL_LP          rn5t_mV_to_regval(1350)
 449 #define VDD_IO_EXT_VAL          rn5t_mV_to_regval(3300)         /* DCDC4 */
 450 #define VDD_IO_EXT_VAL_LP       rn5t_mV_to_regval(3300)
 451 #define VDD_IO_INT_VAL          rn5t_mV_to_regval2(3300)        /* LDO1 */
 452 #define VDD_IO_INT_VAL_LP       rn5t_mV_to_regval2(3300)
 453 #define VDD_ADC_VAL             rn5t_mV_to_regval2(3300)        /* LDO2 */
 454 #define VDD_ADC_VAL_LP          rn5t_mV_to_regval2(3300)
 455 #define VDD_PMIC_VAL            rn5t_mV_to_regval2(2500)        /* LDO3 */
 456 #define VDD_PMIC_VAL_LP         rn5t_mV_to_regval2(2500)
 457 #define VDD_CSI_VAL             rn5t_mV_to_regval2(1800)        /* LDO4 */
 458 #define VDD_CSI_VAL_LP          rn5t_mV_to_regval2(1800)
 459
 460 static struct pmic_regs rn5t567_regs[] = {
 461         { RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, },
 462         { RN5T567_DC1DAC, VDD_CORE_VAL, },
 463         { RN5T567_DC3DAC, VDD_DDR_VAL, },
 464         { RN5T567_DC4DAC, VDD_IO_EXT_VAL, },
 465         { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
 466         { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
 467         { RN5T567_DC4DAC_SLP, VDD_IO_EXT_VAL_LP, },
 468         { RN5T567_DC1CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
 469         { RN5T567_DC2CTL, DCnCTL_DCnDIS, },
 470         { RN5T567_DC3CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
 471         { RN5T567_DC4CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
 472         { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
 473         { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
 474         { RN5T567_LDO1DAC, VDD_IO_INT_VAL, },
 475         { RN5T567_LDO2DAC, VDD_ADC_VAL, },
 476         { RN5T567_LDO3DAC, VDD_PMIC_VAL, },
 477         { RN5T567_LDO4DAC, VDD_CSI_VAL, },
 478         { RN5T567_LDOEN1, 0x0f, ~0x1f, },
 479         { RN5T567_LDOEN2, 0x10, ~0x30, },
 480         { RN5T567_LDODIS, 0x10, ~0x1f, },
 481         { RN5T567_INTPOL, 0, },
 482         { RN5T567_INTEN, 0x3, },
 483         { RN5T567_IREN, 0xf, },
 484         { RN5T567_EN_GPIR, 0, },
 485 };
 486
 487 static int pmic_addr = 0x33;
 488 #endif
 489
 490 int board_init(void)
 491 {
 492         int ret;
 493         u32 cpurev = get_cpu_rev();
 494         char f = '?';
 495
 496         if (is_cpu_type(MXC_CPU_MX6UL))
 497                 f = ((cpurev & 0xf0) > 0x10) ? '5' : '0';
 498         else if (is_cpu_type(MXC_CPU_MX6ULL))
 499                 f = '8';
 500
 501         debug("%s@%d: cpurev=%08x\n", __func__, __LINE__, cpurev);
 502
 503         printf("Board: Ka-Ro TXUL-%c01%c\n", f, tx6ul_mem_suffix());
 504
 505         get_hab_status();
 506
 507         ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios));
 508         if (ret < 0)
 509                 printf("Failed to request tx6ul_gpios: %d\n", ret);
 510
 511         imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads));
 512
 513         /* Address of boot parameters */
 514         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 515         gd->bd->bi_arch_number = -1;
 516
 517         if (ctrlc() || (wrsr & WRSR_TOUT)) {
 518                 if (wrsr & WRSR_TOUT)
 519                         printf("WDOG RESET detected; Skipping PMIC setup\n");
 520                 else
 521                         printf("<CTRL-C> detected; safeboot enabled\n");
 522 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 523                 tx6ul_temp_check_enabled = false;
 524 #endif
 525                 return 0;
 526         }
 527
 528         ret = tx6_pmic_init(pmic_addr, rn5t567_regs, ARRAY_SIZE(rn5t567_regs));
 529         if (ret) {
 530                 printf("Failed to setup PMIC voltages: %d\n", ret);
 531                 hang();
 532         }
 533         return 0;
 534 }
 535
 536 int dram_init(void)
 537 {
 538         debug("%s@%d: \n", __func__, __LINE__);
 539
 540         /* dram_init must store complete ramsize in gd->ram_size */
 541         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 542                                     PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
 543         return 0;
 544 }
 545
 546 void dram_init_banksize(void)
 547 {
 548         debug("%s@%d: \n", __func__, __LINE__);
 549
 550         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 551         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 552                                                PHYS_SDRAM_1_SIZE);
 553 #if CONFIG_NR_DRAM_BANKS > 1
 554         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 555         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 556                                                PHYS_SDRAM_2_SIZE);
 557 #endif
 558 }
 559
 560 #ifdef  CONFIG_FSL_ESDHC
 561 #define TX6UL_SD_PAD_CTRL       MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |       \
 562                                         PAD_CTL_SPEED_MED |             \
 563                                         PAD_CTL_DSE_40ohm |             \
 564                                         PAD_CTL_SRE_FAST)
 565
 566 static const iomux_v3_cfg_t mmc0_pads[] = {
 567         MX6_PAD_SD1_CMD__USDHC1_CMD | TX6UL_SD_PAD_CTRL,
 568         MX6_PAD_SD1_CLK__USDHC1_CLK | TX6UL_SD_PAD_CTRL,
 569         MX6_PAD_SD1_DATA0__USDHC1_DATA0 | TX6UL_SD_PAD_CTRL,
 570         MX6_PAD_SD1_DATA1__USDHC1_DATA1 | TX6UL_SD_PAD_CTRL,
 571         MX6_PAD_SD1_DATA2__USDHC1_DATA2 | TX6UL_SD_PAD_CTRL,
 572         MX6_PAD_SD1_DATA3__USDHC1_DATA3 | TX6UL_SD_PAD_CTRL,
 573         /* SD1 CD */
 574         MX6_PAD_NAND_CE1_B__GPIO4_IO14 | TX6UL_SD_PAD_CTRL,
 575 };
 576
 577 #ifdef CONFIG_TX6_EMMC
 578 static const iomux_v3_cfg_t mmc1_pads[] = {
 579         MX6_PAD_NAND_WE_B__USDHC2_CMD | TX6UL_SD_PAD_CTRL,
 580         MX6_PAD_NAND_RE_B__USDHC2_CLK | TX6UL_SD_PAD_CTRL,
 581         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | TX6UL_SD_PAD_CTRL,
 582         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | TX6UL_SD_PAD_CTRL,
 583         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | TX6UL_SD_PAD_CTRL,
 584         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | TX6UL_SD_PAD_CTRL,
 585         /* eMMC RESET */
 586         MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
 587                                                         PAD_CTL_DSE_40ohm),
 588 };
 589 #endif
 590
 591 static struct tx6ul_esdhc_cfg {
 592         const iomux_v3_cfg_t *pads;
 593         int num_pads;
 594         enum mxc_clock clkid;
 595         struct fsl_esdhc_cfg cfg;
 596         int cd_gpio;
 597 } tx6ul_esdhc_cfg[] = {
 598 #ifdef CONFIG_TX6_EMMC
 599         {
 600                 .pads = mmc1_pads,
 601                 .num_pads = ARRAY_SIZE(mmc1_pads),
 602                 .clkid = MXC_ESDHC2_CLK,
 603                 .cfg = {
 604                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
 605                         .max_bus_width = 4,
 606                 },
 607                 .cd_gpio = -EINVAL,
 608         },
 609 #endif
 610         {
 611                 .pads = mmc0_pads,
 612                 .num_pads = ARRAY_SIZE(mmc0_pads),
 613                 .clkid = MXC_ESDHC_CLK,
 614                 .cfg = {
 615                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
 616                         .max_bus_width = 4,
 617                 },
 618                 .cd_gpio = TX6UL_SD1_CD_GPIO,
 619         },
 620 };
 621
 622 static inline struct tx6ul_esdhc_cfg *to_tx6ul_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 623 {
 624         return container_of(cfg, struct tx6ul_esdhc_cfg, cfg);
 625 }
 626
 627 int board_mmc_getcd(struct mmc *mmc)
 628 {
 629         struct tx6ul_esdhc_cfg *cfg = to_tx6ul_esdhc_cfg(mmc->priv);
 630
 631         if (cfg->cd_gpio < 0)
 632                 return 1;
 633
 634         debug("SD card %d is %spresent (GPIO %d)\n",
 635               cfg - tx6ul_esdhc_cfg,
 636               gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
 637               cfg->cd_gpio);
 638         return !gpio_get_value(cfg->cd_gpio);
 639 }
 640
 641 int board_mmc_init(bd_t *bis)
 642 {
 643         int i;
 644
 645         debug("%s@%d: \n", __func__, __LINE__);
 646
 647 #ifndef CONFIG_ENV_IS_IN_MMC
 648         if (!(gd->flags & GD_FLG_ENV_READY)) {
 649                 printf("deferred ...");
 650                 return 0;
 651         }
 652 #endif
 653         for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) {
 654                 struct mmc *mmc;
 655                 struct tx6ul_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
 656                 int ret;
 657
 658                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
 659                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
 660
 661                 if (cfg->cd_gpio >= 0) {
 662                         ret = gpio_request_one(cfg->cd_gpio,
 663                                                GPIOFLAG_INPUT, "MMC CD");
 664                         if (ret) {
 665                                 printf("Error %d requesting GPIO%d_%d\n",
 666                                        ret, cfg->cd_gpio / 32,
 667                                        cfg->cd_gpio % 32);
 668                                 continue;
 669                         }
 670                 }
 671
 672                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 673                 fsl_esdhc_initialize(bis, &cfg->cfg);
 674
 675                 mmc = find_mmc_device(i);
 676                 if (mmc == NULL)
 677                         continue;
 678                 if (board_mmc_getcd(mmc))
 679                         mmc_init(mmc);
 680         }
 681         return 0;
 682 }
 683 #endif /* CONFIG_FSL_ESDHC */
 684
 685 enum {
 686         LED_STATE_INIT = -1,
 687         LED_STATE_OFF,
 688         LED_STATE_ON,
 689         LED_STATE_ERR,
 690 };
 691
 692 static inline int calc_blink_rate(void)
 693 {
 694         if (!tx6ul_temp_check_enabled)
 695                 return CONFIG_SYS_HZ;
 696
 697         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
 698                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
 699                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
 700 }
 701
 702 void show_activity(int arg)
 703 {
 704         static int led_state = LED_STATE_INIT;
 705         static int blink_rate;
 706         static ulong last;
 707         int ret;
 708
 709         switch (led_state) {
 710         case LED_STATE_ERR:
 711                 return;
 712
 713         case LED_STATE_INIT:
 714                 last = get_timer(0);
 715                 ret = gpio_set_value(TX6UL_LED_GPIO, 1);
 716                 if (ret)
 717                         led_state = LED_STATE_ERR;
 718                 else
 719                         led_state = LED_STATE_ON;
 720                 blink_rate = calc_blink_rate();
 721                 break;
 722
 723         case LED_STATE_ON:
 724         case LED_STATE_OFF:
 725                 if (get_timer(last) > blink_rate) {
 726                         blink_rate = calc_blink_rate();
 727                         last = get_timer_masked();
 728                         if (led_state == LED_STATE_ON) {
 729                                 gpio_set_value(TX6UL_LED_GPIO, 0);
 730                         } else {
 731                                 gpio_set_value(TX6UL_LED_GPIO, 1);
 732                         }
 733                         led_state = 1 - led_state;
 734                 }
 735                 break;
 736         }
 737 }
 738
 739 static const iomux_v3_cfg_t stk5_jtag_pads[] = {
 740         MX6_PAD_JTAG_MOD__SJC_MOD | TX6UL_GPIO_IN_PAD_CTRL,
 741         MX6_PAD_JTAG_TCK__SJC_TCK | TX6UL_GPIO_IN_PAD_CTRL,
 742         MX6_PAD_JTAG_TRST_B__SJC_TRSTB | TX6UL_GPIO_IN_PAD_CTRL,
 743         MX6_PAD_JTAG_TDI__SJC_TDI | TX6UL_GPIO_IN_PAD_CTRL,
 744         MX6_PAD_JTAG_TDO__SJC_TDO | TX6UL_GPIO_OUT_PAD_CTRL,
 745         MX6_PAD_JTAG_TMS__SJC_TMS | TX6UL_GPIO_IN_PAD_CTRL,
 746 };
 747
 748 static const iomux_v3_cfg_t stk5_pads[] = {
 749         /* SW controlled LED on STK5 baseboard */
 750         MX6_PAD_SNVS_TAMPER9__GPIO5_IO09,
 751
 752         /* I2C bus on DIMM pins 40/41 */
 753         MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
 754         MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
 755
 756         /* TSC200x PEN IRQ */
 757         MX6_PAD_JTAG_TMS__GPIO1_IO11 | TX6UL_GPIO_IN_PAD_CTRL,
 758
 759         /* EDT-FT5x06 Polytouch panel */
 760         MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | TX6UL_GPIO_IN_PAD_CTRL, /* IRQ */
 761         MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 | TX6UL_GPIO_OUT_PAD_CTRL, /* RESET */
 762         MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | TX6UL_GPIO_OUT_PAD_CTRL, /* WAKE */
 763
 764         /* USBH1 */
 765         MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
 766         MX6_PAD_GPIO1_IO03__USB_OTG2_OC | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
 767
 768         /* USBOTG */
 769         MX6_PAD_UART3_CTS_B__GPIO1_IO26 | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
 770         MX6_PAD_UART3_RTS_B__GPIO1_IO27 | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
 771 };
 772
 773 static const struct gpio stk5_gpios[] = {
 774         { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 775
 776         { IMX_GPIO_NR(1, 27), GPIOFLAG_INPUT, "USBOTG OC", },
 777         { IMX_GPIO_NR(1, 26), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 778 };
 779
 780 #ifdef CONFIG_LCD
 781 vidinfo_t panel_info = {
 782         /* set to max. size supported by SoC */
 783         .vl_col = 4096,
 784         .vl_row = 1024,
 785
 786         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 787 };
 788
 789 static struct fb_videomode tx6ul_fb_modes[] = {
 790 #ifndef CONFIG_SYS_LVDS_IF
 791         {
 792                 /* Standard VGA timing */
 793                 .name           = "VGA",
 794                 .refresh        = 60,
 795                 .xres           = 640,
 796                 .yres           = 480,
 797                 .pixclock       = KHZ2PICOS(25175),
 798                 .left_margin    = 48,
 799                 .hsync_len      = 96,
 800                 .right_margin   = 16,
 801                 .upper_margin   = 31,
 802                 .vsync_len      = 2,
 803                 .lower_margin   = 12,
 804                 .sync           = FB_SYNC_CLK_LAT_FALL,
 805         },
 806         {
 807                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 808                  * DE high active, 115.2 mm x 86.4 mm display area
 809                  * VGA compatible timing
 810                  */
 811                 .name           = "ETV570",
 812                 .refresh        = 60,
 813                 .xres           = 640,
 814                 .yres           = 480,
 815                 .pixclock       = KHZ2PICOS(25175),
 816                 .left_margin    = 114,
 817                 .hsync_len      = 30,
 818                 .right_margin   = 16,
 819                 .upper_margin   = 32,
 820                 .vsync_len      = 3,
 821                 .lower_margin   = 10,
 822                 .sync           = FB_SYNC_CLK_LAT_FALL,
 823         },
 824         {
 825                 /* Emerging ET0350G0DH6 320 x 240 display.
 826                  * 70.08 mm x 52.56 mm display area.
 827                  */
 828                 .name           = "ET0350",
 829                 .refresh        = 60,
 830                 .xres           = 320,
 831                 .yres           = 240,
 832                 .pixclock       = KHZ2PICOS(6500),
 833                 .left_margin    = 68 - 34,
 834                 .hsync_len      = 34,
 835                 .right_margin   = 20,
 836                 .upper_margin   = 18 - 3,
 837                 .vsync_len      = 3,
 838                 .lower_margin   = 4,
 839                 .sync           = FB_SYNC_CLK_LAT_FALL,
 840         },
 841         {
 842                 /* Emerging ET0430G0DH6 480 x 272 display.
 843                  * 95.04 mm x 53.856 mm display area.
 844                  */
 845                 .name           = "ET0430",
 846                 .refresh        = 60,
 847                 .xres           = 480,
 848                 .yres           = 272,
 849                 .pixclock       = KHZ2PICOS(9000),
 850                 .left_margin    = 2,
 851                 .hsync_len      = 41,
 852                 .right_margin   = 2,
 853                 .upper_margin   = 2,
 854                 .vsync_len      = 10,
 855                 .lower_margin   = 2,
 856         },
 857         {
 858                 /* Emerging ET0500G0DH6 800 x 480 display.
 859                  * 109.6 mm x 66.4 mm display area.
 860                  */
 861                 .name           = "ET0500",
 862                 .refresh        = 60,
 863                 .xres           = 800,
 864                 .yres           = 480,
 865                 .pixclock       = KHZ2PICOS(33260),
 866                 .left_margin    = 216 - 128,
 867                 .hsync_len      = 128,
 868                 .right_margin   = 1056 - 800 - 216,
 869                 .upper_margin   = 35 - 2,
 870                 .vsync_len      = 2,
 871                 .lower_margin   = 525 - 480 - 35,
 872                 .sync           = FB_SYNC_CLK_LAT_FALL,
 873         },
 874         {
 875                 /* Emerging ETQ570G0DH6 320 x 240 display.
 876                  * 115.2 mm x 86.4 mm display area.
 877                  */
 878                 .name           = "ETQ570",
 879                 .refresh        = 60,
 880                 .xres           = 320,
 881                 .yres           = 240,
 882                 .pixclock       = KHZ2PICOS(6400),
 883                 .left_margin    = 38,
 884                 .hsync_len      = 30,
 885                 .right_margin   = 30,
 886                 .upper_margin   = 16, /* 15 according to datasheet */
 887                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 888                 .lower_margin   = 4, /* 4.5 according to datasheet */
 889                 .sync           = FB_SYNC_CLK_LAT_FALL,
 890         },
 891         {
 892                 /* Emerging ET0700G0DH6 800 x 480 display.
 893                  * 152.4 mm x 91.44 mm display area.
 894                  */
 895                 .name           = "ET0700",
 896                 .refresh        = 60,
 897                 .xres           = 800,
 898                 .yres           = 480,
 899                 .pixclock       = KHZ2PICOS(33260),
 900                 .left_margin    = 216 - 128,
 901                 .hsync_len      = 128,
 902                 .right_margin   = 1056 - 800 - 216,
 903                 .upper_margin   = 35 - 2,
 904                 .vsync_len      = 2,
 905                 .lower_margin   = 525 - 480 - 35,
 906                 .sync           = FB_SYNC_CLK_LAT_FALL,
 907         },
 908         {
 909                 /* Emerging ET070001DM6 800 x 480 display.
 910                  * 152.4 mm x 91.44 mm display area.
 911                  */
 912                 .name           = "ET070001DM6",
 913                 .refresh        = 60,
 914                 .xres           = 800,
 915                 .yres           = 480,
 916                 .pixclock       = KHZ2PICOS(33260),
 917                 .left_margin    = 216 - 128,
 918                 .hsync_len      = 128,
 919                 .right_margin   = 1056 - 800 - 216,
 920                 .upper_margin   = 35 - 2,
 921                 .vsync_len      = 2,
 922                 .lower_margin   = 525 - 480 - 35,
 923                 .sync           = 0,
 924         },
 925 #else
 926         {
 927                 /* HannStar HSD100PXN1
 928                  * 202.7m mm x 152.06 mm display area.
 929                  */
 930                 .name           = "HSD100PXN1",
 931                 .refresh        = 60,
 932                 .xres           = 1024,
 933                 .yres           = 768,
 934                 .pixclock       = KHZ2PICOS(65000),
 935                 .left_margin    = 0,
 936                 .hsync_len      = 0,
 937                 .right_margin   = 320,
 938                 .upper_margin   = 0,
 939                 .vsync_len      = 0,
 940                 .lower_margin   = 38,
 941                 .sync           = FB_SYNC_CLK_LAT_FALL,
 942         },
 943 #endif
 944         {
 945                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 946                 .refresh        = 60,
 947                 .left_margin    = 48,
 948                 .hsync_len      = 96,
 949                 .right_margin   = 16,
 950                 .upper_margin   = 31,
 951                 .vsync_len      = 2,
 952                 .lower_margin   = 12,
 953                 .sync           = FB_SYNC_CLK_LAT_FALL,
 954         },
 955 };
 956
 957 static int lcd_enabled = 1;
 958 static int lcd_bl_polarity;
 959
 960 static int lcd_backlight_polarity(void)
 961 {
 962         return lcd_bl_polarity;
 963 }
 964
 965 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 966 #ifdef CONFIG_LCD
 967         /* LCD RESET */
 968         MX6_PAD_LCD_RESET__GPIO3_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
 969         /* LCD POWER_ENABLE */
 970         MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
 971         /* LCD Backlight (PWM) */
 972         MX6_PAD_NAND_DQS__GPIO4_IO16 | TX6UL_GPIO_OUT_PAD_CTRL,
 973         /* Display */
 974         MX6_PAD_LCD_DATA00__LCDIF_DATA00,
 975         MX6_PAD_LCD_DATA01__LCDIF_DATA01,
 976         MX6_PAD_LCD_DATA02__LCDIF_DATA02,
 977         MX6_PAD_LCD_DATA03__LCDIF_DATA03,
 978         MX6_PAD_LCD_DATA04__LCDIF_DATA04,
 979         MX6_PAD_LCD_DATA05__LCDIF_DATA05,
 980         MX6_PAD_LCD_DATA06__LCDIF_DATA06,
 981         MX6_PAD_LCD_DATA07__LCDIF_DATA07,
 982         MX6_PAD_LCD_DATA08__LCDIF_DATA08,
 983         MX6_PAD_LCD_DATA09__LCDIF_DATA09,
 984         MX6_PAD_LCD_DATA10__LCDIF_DATA10,
 985         MX6_PAD_LCD_DATA11__LCDIF_DATA11,
 986         MX6_PAD_LCD_DATA12__LCDIF_DATA12,
 987         MX6_PAD_LCD_DATA13__LCDIF_DATA13,
 988         MX6_PAD_LCD_DATA14__LCDIF_DATA14,
 989         MX6_PAD_LCD_DATA15__LCDIF_DATA15,
 990         MX6_PAD_LCD_DATA16__LCDIF_DATA16,
 991         MX6_PAD_LCD_DATA17__LCDIF_DATA17,
 992         MX6_PAD_LCD_DATA18__LCDIF_DATA18,
 993         MX6_PAD_LCD_DATA19__LCDIF_DATA19,
 994         MX6_PAD_LCD_DATA20__LCDIF_DATA20,
 995         MX6_PAD_LCD_DATA21__LCDIF_DATA21,
 996         MX6_PAD_LCD_DATA22__LCDIF_DATA22,
 997         MX6_PAD_LCD_DATA23__LCDIF_DATA23,
 998         MX6_PAD_LCD_HSYNC__LCDIF_HSYNC, /* HSYNC */
 999         MX6_PAD_LCD_VSYNC__LCDIF_VSYNC, /* VSYNC */
1000         MX6_PAD_LCD_ENABLE__LCDIF_ENABLE, /* OE_ACD */
1001         MX6_PAD_LCD_CLK__LCDIF_CLK, /* LSCLK */
1002 #endif
1003 };
1004
1005 static const struct gpio stk5_lcd_gpios[] = {
1006         { TX6UL_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1007         { TX6UL_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1008         { TX6UL_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1009 };
1010
1011 /* run with valid env from NAND/eMMC */
1012 void lcd_enable(void)
1013 {
1014         /* HACK ALERT:
1015          * global variable from common/lcd.c
1016          * Set to 0 here to prevent messages from going to LCD
1017          * rather than serial console
1018          */
1019         lcd_is_enabled = 0;
1020
1021         if (lcd_enabled) {
1022                 karo_load_splashimage(1);
1023
1024                 debug("Switching LCD on\n");
1025                 gpio_set_value(TX6UL_LCD_PWR_GPIO, 1);
1026                 udelay(100);
1027                 gpio_set_value(TX6UL_LCD_RST_GPIO, 1);
1028                 udelay(300000);
1029                 gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
1030                                lcd_backlight_polarity());
1031         }
1032 }
1033
1034 static void lcd_disable(void)
1035 {
1036         if (lcd_enabled) {
1037                 printf("Disabling LCD\n");
1038                 panel_info.vl_row = 0;
1039                 lcd_enabled = 0;
1040         }
1041 }
1042
1043 void lcd_ctrl_init(void *lcdbase)
1044 {
1045         int color_depth = 24;
1046         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1047         const char *vm;
1048         unsigned long val;
1049         int refresh = 60;
1050         struct fb_videomode *p = &tx6ul_fb_modes[0];
1051         struct fb_videomode fb_mode;
1052         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1053
1054         if (!lcd_enabled) {
1055                 debug("LCD disabled\n");
1056                 return;
1057         }
1058
1059         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1060                 lcd_disable();
1061                 setenv("splashimage", NULL);
1062                 return;
1063         }
1064
1065         karo_fdt_move_fdt();
1066         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1067
1068         if (video_mode == NULL) {
1069                 lcd_disable();
1070                 return;
1071         }
1072         vm = video_mode;
1073         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1074                 p = &fb_mode;
1075                 debug("Using video mode from FDT\n");
1076                 vm += strlen(vm);
1077                 if (fb_mode.xres > panel_info.vl_col ||
1078                         fb_mode.yres > panel_info.vl_row) {
1079                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1080                                fb_mode.xres, fb_mode.yres,
1081                                panel_info.vl_col, panel_info.vl_row);
1082                         lcd_enabled = 0;
1083                         return;
1084                 }
1085         }
1086         if (p->name != NULL)
1087                 debug("Trying compiled-in video modes\n");
1088         while (p->name != NULL) {
1089                 if (strcmp(p->name, vm) == 0) {
1090                         debug("Using video mode: '%s'\n", p->name);
1091                         vm += strlen(vm);
1092                         break;
1093                 }
1094                 p++;
1095         }
1096         if (*vm != '\0')
1097                 debug("Trying to decode video_mode: '%s'\n", vm);
1098         while (*vm != '\0') {
1099                 if (*vm >= '0' && *vm <= '9') {
1100                         char *end;
1101
1102                         val = simple_strtoul(vm, &end, 0);
1103                         if (end > vm) {
1104                                 if (!xres_set) {
1105                                         if (val > panel_info.vl_col)
1106                                                 val = panel_info.vl_col;
1107                                         p->xres = val;
1108                                         panel_info.vl_col = val;
1109                                         xres_set = 1;
1110                                 } else if (!yres_set) {
1111                                         if (val > panel_info.vl_row)
1112                                                 val = panel_info.vl_row;
1113                                         p->yres = val;
1114                                         panel_info.vl_row = val;
1115                                         yres_set = 1;
1116                                 } else if (!bpp_set) {
1117                                         switch (val) {
1118                                         case 8:
1119                                         case 16:
1120                                         case 18:
1121                                         case 24:
1122                                         case 32:
1123                                                 color_depth = val;
1124                                                 break;
1125
1126                                         default:
1127                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1128                                                        end - vm, vm,
1129                                                        color_depth);
1130                                         }
1131                                         bpp_set = 1;
1132                                 } else if (!refresh_set) {
1133                                         refresh = val;
1134                                         refresh_set = 1;
1135                                 }
1136                         }
1137                         vm = end;
1138                 }
1139                 switch (*vm) {
1140                 case '@':
1141                         bpp_set = 1;
1142                         /* fallthru */
1143                 case '-':
1144                         yres_set = 1;
1145                         /* fallthru */
1146                 case 'x':
1147                         xres_set = 1;
1148                         /* fallthru */
1149                 case 'M':
1150                 case 'R':
1151                         vm++;
1152                         break;
1153
1154                 default:
1155                         if (*vm != '\0')
1156                                 vm++;
1157                 }
1158         }
1159         if (p->xres == 0 || p->yres == 0) {
1160                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1161                 lcd_enabled = 0;
1162                 printf("Supported video modes are:");
1163                 for (p = &tx6ul_fb_modes[0]; p->name != NULL; p++) {
1164                         printf(" %s", p->name);
1165                 }
1166                 printf("\n");
1167                 return;
1168         }
1169         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1170                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1171                        p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1172                 lcd_enabled = 0;
1173                 return;
1174         }
1175         panel_info.vl_col = p->xres;
1176         panel_info.vl_row = p->yres;
1177
1178         switch (color_depth) {
1179         case 8:
1180                 panel_info.vl_bpix = LCD_COLOR8;
1181                 break;
1182         case 16:
1183                 panel_info.vl_bpix = LCD_COLOR16;
1184                 break;
1185         default:
1186                 panel_info.vl_bpix = LCD_COLOR32;
1187         }
1188
1189         p->pixclock = KHZ2PICOS(refresh *
1190                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1191                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1192                                 1000);
1193         debug("Pixel clock set to %lu.%03lu MHz\n",
1194               PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1195
1196         if (p != &fb_mode) {
1197                 int ret;
1198
1199                 debug("Creating new display-timing node from '%s'\n",
1200                       video_mode);
1201                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1202                 if (ret)
1203                         printf("Failed to create new display-timing node from '%s': %d\n",
1204                                video_mode, ret);
1205         }
1206
1207         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1208         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1209                                          ARRAY_SIZE(stk5_lcd_pads));
1210
1211         debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
1212               color_depth, refresh);
1213
1214         if (karo_load_splashimage(0) == 0) {
1215                 char vmode[128];
1216
1217                 /* setup env variable for mxsfb display driver */
1218                 snprintf(vmode, sizeof(vmode),
1219                          "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
1220                          p->xres, p->yres, p->left_margin, p->right_margin,
1221                          p->upper_margin, p->lower_margin, p->hsync_len,
1222                          p->vsync_len, p->sync, p->pixclock, color_depth);
1223                 setenv("videomode", vmode);
1224
1225                 debug("Initializing LCD controller\n");
1226                 lcdif_clk_enable();
1227                 video_hw_init();
1228                 setenv("videomode", NULL);
1229         } else {
1230                 debug("Skipping initialization of LCD controller\n");
1231         }
1232 }
1233 #else
1234 #define lcd_enabled 0
1235 #endif /* CONFIG_LCD */
1236
1237 #ifndef CONFIG_ENV_IS_IN_MMC
1238 static void tx6ul_mmc_init(void)
1239 {
1240         puts("MMC:   ");
1241         if (board_mmc_init(gd->bd) < 0)
1242                 cpu_mmc_init(gd->bd);
1243         print_mmc_devices(',');
1244 }
1245 #else
1246 static inline void tx6ul_mmc_init(void)
1247 {
1248 }
1249 #endif
1250
1251 static void stk5_board_init(void)
1252 {
1253         int ret;
1254
1255         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1256         if (ret < 0) {
1257                 printf("Failed to request stk5_gpios: %d\n", ret);
1258                 return;
1259         }
1260
1261         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1262         if (getenv_yesno("jtag_enable") != 0) {
1263                 /* true if unset or set to one of: 'yYtT1' */
1264                 imx_iomux_v3_setup_multiple_pads(stk5_jtag_pads, ARRAY_SIZE(stk5_jtag_pads));
1265         }
1266
1267         debug("%s@%d: \n", __func__, __LINE__);
1268 }
1269
1270 static void stk5v3_board_init(void)
1271 {
1272         debug("%s@%d: \n", __func__, __LINE__);
1273         stk5_board_init();
1274         debug("%s@%d: \n", __func__, __LINE__);
1275         tx6ul_mmc_init();
1276 }
1277
1278 static void stk5v5_board_init(void)
1279 {
1280         int ret;
1281
1282         stk5_board_init();
1283         tx6ul_mmc_init();
1284
1285         ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
1286                                "Flexcan Transceiver");
1287         if (ret) {
1288                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1289                 return;
1290         }
1291
1292         imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 |
1293                                TX6UL_GPIO_OUT_PAD_CTRL);
1294 }
1295
1296 static void tx6ul_set_cpu_clock(void)
1297 {
1298         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1299
1300         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1301                 return;
1302
1303         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1304                 printf("%s detected; skipping cpu clock change\n",
1305                        (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1306                 return;
1307         }
1308         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1309                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1310                 printf("CPU clock set to %lu.%03lu MHz\n",
1311                        cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1312         } else {
1313                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1314         }
1315 }
1316
1317 int board_late_init(void)
1318 {
1319         const char *baseboard;
1320
1321         debug("%s@%d: \n", __func__, __LINE__);
1322
1323         env_cleanup();
1324
1325         if (tx6ul_temp_check_enabled)
1326                 check_cpu_temperature(1);
1327
1328         tx6ul_set_cpu_clock();
1329
1330         if (had_ctrlc())
1331                 setenv_ulong("safeboot", 1);
1332         else if (wrsr & WRSR_TOUT)
1333                 setenv_ulong("wdreset", 1);
1334         else
1335                 karo_fdt_move_fdt();
1336
1337         baseboard = getenv("baseboard");
1338         if (!baseboard)
1339                 goto exit;
1340
1341         printf("Baseboard: %s\n", baseboard);
1342
1343         if (strncmp(baseboard, "stk5", 4) == 0) {
1344                 if ((strlen(baseboard) == 4) ||
1345                         strcmp(baseboard, "stk5-v3") == 0) {
1346                         stk5v3_board_init();
1347                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1348                         const char *otg_mode = getenv("otg_mode");
1349
1350                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1351                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1352                                        otg_mode, baseboard);
1353                                 setenv("otg_mode", "none");
1354                         }
1355                         stk5v5_board_init();
1356                 } else {
1357                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1358                                 baseboard + 4);
1359                 }
1360         } else if (strncmp(baseboard, "ulmb-", 5) == 0) {
1361                         const char *otg_mode = getenv("otg_mode");
1362
1363                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1364                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1365                                        otg_mode, baseboard);
1366                                 setenv("otg_mode", "none");
1367                         }
1368                         stk5_board_init();
1369         } else {
1370                 printf("WARNING: Unsupported baseboard: '%s'\n",
1371                         baseboard);
1372                 if (!had_ctrlc())
1373                         return -EINVAL;
1374         }
1375
1376 exit:
1377         debug("%s@%d: \n", __func__, __LINE__);
1378
1379         clear_ctrlc();
1380         return 0;
1381 }
1382
1383 #ifdef CONFIG_FEC_MXC
1384
1385 #ifndef ETH_ALEN
1386 #define ETH_ALEN 6
1387 #endif
1388
1389 static void tx6ul_init_mac(void)
1390 {
1391         u8 mac[ETH_ALEN];
1392         const char *baseboard = getenv("baseboard");
1393
1394         imx_get_mac_from_fuse(0, mac);
1395         if (!is_valid_ethaddr(mac)) {
1396                 printf("No valid MAC address programmed\n");
1397                 return;
1398         }
1399         printf("MAC addr from fuse: %pM\n", mac);
1400         if (!getenv("ethaddr"))
1401                 eth_setenv_enetaddr("ethaddr", mac);
1402
1403         if (!baseboard || strncmp(baseboard, "stk5", 4) == 0) {
1404                 setenv("eth1addr", NULL);
1405                 return;
1406         }
1407         if (getenv("eth1addr"))
1408                 return;
1409         imx_get_mac_from_fuse(1, mac);
1410         eth_setenv_enetaddr("eth1addr", mac);
1411 }
1412
1413 int board_eth_init(bd_t *bis)
1414 {
1415         int ret;
1416
1417         tx6ul_init_mac();
1418
1419         /* delay at least 21ms for the PHY internal POR signal to deassert */
1420         udelay(22000);
1421
1422         imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads,
1423                                          ARRAY_SIZE(tx6ul_enet1_pads));
1424
1425         /* Deassert RESET to the external phys */
1426         gpio_set_value(TX6UL_FEC_RST_GPIO, 1);
1427
1428         if (getenv("ethaddr")) {
1429                 ret = fecmxc_initialize_multi(bis, 0, 0, ENET_BASE_ADDR);
1430                 if (ret) {
1431                         printf("failed to initialize FEC0: %d\n", ret);
1432                         return ret;
1433                 }
1434         }
1435         if (getenv("eth1addr")) {
1436                 ret = gpio_request_array(tx6ul_fec2_gpios,
1437                                          ARRAY_SIZE(tx6ul_fec2_gpios));
1438                 if (ret < 0) {
1439                         printf("Failed to request tx6ul_fec2_gpios: %d\n", ret);
1440                 }
1441                 imx_iomux_v3_setup_multiple_pads(tx6ul_enet2_pads,
1442                                                  ARRAY_SIZE(tx6ul_enet2_pads));
1443
1444                 writel(0x00100000, 0x020c80e4); /* assert ENET2_125M_EN */
1445
1446                 /* Minimum PHY reset duration */
1447                 udelay(100);
1448                 gpio_set_value(TX6UL_FEC2_RST_GPIO, 1);
1449                 /* Wait for PHY internal POR to finish */
1450                 udelay(22000);
1451
1452                 ret = fecmxc_initialize_multi(bis, 1, 2, ENET2_BASE_ADDR);
1453                 if (ret) {
1454                         printf("failed to initialize FEC1: %d\n", ret);
1455                         return ret;
1456                 }
1457         }
1458         return 0;
1459 }
1460 #endif /* CONFIG_FEC_MXC */
1461
1462 #ifdef CONFIG_SERIAL_TAG
1463 void get_board_serial(struct tag_serialnr *serialnr)
1464 {
1465         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1466         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1467
1468         serialnr->low = readl(&fuse->cfg0);
1469         serialnr->high = readl(&fuse->cfg1);
1470 }
1471 #endif
1472
1473 #if defined(CONFIG_OF_BOARD_SETUP)
1474 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1475 #include <jffs2/jffs2.h>
1476 #include <mtd_node.h>
1477 static struct node_info nodes[] = {
1478         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1479 };
1480 #else
1481 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1482 #endif
1483
1484 static const char *tx6ul_touchpanels[] = {
1485         "ti,tsc2007",
1486         "edt,edt-ft5x06",
1487         "eeti,egalax_ts",
1488 };
1489
1490 int ft_board_setup(void *blob, bd_t *bd)
1491 {
1492         const char *baseboard = getenv("baseboard");
1493         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1494         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1495         int ret;
1496
1497         ret = fdt_increase_size(blob, 4096);
1498         if (ret) {
1499                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1500                 return ret;
1501         }
1502         if (stk5_v5)
1503                 karo_fdt_enable_node(blob, "stk5led", 0);
1504
1505         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1506
1507         karo_fdt_fixup_touchpanel(blob, tx6ul_touchpanels,
1508                                   ARRAY_SIZE(tx6ul_touchpanels));
1509         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1510         karo_fdt_fixup_flexcan(blob, stk5_v5);
1511
1512         karo_fdt_update_fb_mode(blob, video_mode, "/lcd-panel");
1513
1514         return 0;
1515 }
1516 #endif /* CONFIG_OF_BOARD_SETUP */