karo: tx6ul: add pad settings for FT5x06 and USB pads on STK5
[karo-tx-uboot.git] / board / karo / tx6 / tx6ul.c
1 /*
2  * Copyright (C) 2015 Lothar WaƟmann <LW@KARO-electronics.de>
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  *
6  */
7 #include <common.h>
8 #include <errno.h>
9 #include <libfdt.h>
10 #include <fdt_support.h>
11 #include <lcd.h>
12 #include <netdev.h>
13 #include <mmc.h>
14 #include <fsl_esdhc.h>
15 #include <video_fb.h>
16 #include <ipu.h>
17 #include <mxcfb.h>
18 #include <i2c.h>
19 #include <linux/fb.h>
20 #include <asm/io.h>
21 #include <asm/gpio.h>
22 #include <asm/arch/mx6-pins.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/hab.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/crm_regs.h>
27 #include <asm/arch/sys_proto.h>
28
29 #include "../common/karo.h"
30 #include "pmic.h"
31
32 #define __data __attribute__((section(".data")))
33
34 #define TX6UL_FEC_RST_GPIO              IMX_GPIO_NR(5, 6)
35 #define TX6UL_FEC_PWR_GPIO              IMX_GPIO_NR(5, 7)
36 #define TX6UL_FEC_INT_GPIO              IMX_GPIO_NR(5, 5)
37
38 #define TX6UL_FEC2_RST_GPIO             IMX_GPIO_NR(4, 28)
39 #define TX6UL_FEC2_INT_GPIO             IMX_GPIO_NR(4, 27)
40
41 #define TX6UL_LED_GPIO                  IMX_GPIO_NR(5, 9)
42
43 #define TX6UL_LCD_PWR_GPIO              IMX_GPIO_NR(5, 4)
44 #define TX6UL_LCD_RST_GPIO              IMX_GPIO_NR(3, 4)
45 #define TX6UL_LCD_BACKLIGHT_GPIO        IMX_GPIO_NR(4, 16)
46
47 #define TX6UL_I2C1_SCL_GPIO             CONFIG_SOFT_I2C_GPIO_SCL
48 #define TX6UL_I2C1_SDA_GPIO             CONFIG_SOFT_I2C_GPIO_SDA
49
50 #define TX6UL_SD1_CD_GPIO               IMX_GPIO_NR(4, 14)
51
52 #ifdef CONFIG_MX6_TEMPERATURE_MIN
53 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
54 #else
55 #define TEMPERATURE_MIN                 (-40)
56 #endif
57 #ifdef CONFIG_MX6_TEMPERATURE_HOT
58 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
59 #else
60 #define TEMPERATURE_HOT                 80
61 #endif
62
63 DECLARE_GLOBAL_DATA_PTR;
64
65 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
66
67 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
68 #ifdef CONFIG_SECURE_BOOT
69 char __csf_data[0] __attribute__((section(".__csf_data")));
70 #endif
71
72 static const iomux_v3_cfg_t const tx6ul_pads[] = {
73         /* UART pads */
74 #if CONFIG_MXC_UART_BASE == UART1_BASE
75         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX,
76         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX,
77         MX6_PAD_UART1_RTS_B__UART1_DCE_RTS,
78         MX6_PAD_UART1_CTS_B__UART1_DCE_CTS,
79 #endif
80 #if CONFIG_MXC_UART_BASE == UART2_BASE
81         MX6_PAD_UART2_TX_DATA__UART2_DCE_TX,
82         MX6_PAD_UART2_RX_DATA__UART2_DCE_RX,
83         MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS,
84         MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS,
85 #endif
86 #if CONFIG_MXC_UART_BASE == UART5_BASE
87         MX6_PAD_GPIO1_IO04__UART5_DCE_TX,
88         MX6_PAD_GPIO1_IO05__UART5_DCE_RX,
89         MX6_PAD_GPIO1_IO08__UART5_DCE_RTS,
90         MX6_PAD_GPIO1_IO09__UART5_DCE_CTS,
91 #endif
92         /* internal I2C */
93         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
94                         MUX_PAD_CTRL(PAD_CTL_DSE_240ohm), /* I2C SCL */
95         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
96                         MUX_PAD_CTRL(PAD_CTL_DSE_240ohm | PAD_CTL_HYS |
97                         PAD_CTL_ODE), /* I2C SDA */
98
99         /* FEC PHY GPIO functions */
100         MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_CFG_SION, /* PHY POWER */
101         MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | MUX_CFG_SION, /* PHY RESET */
102         MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
103                                                         PAD_CTL_DSE_40ohm), /* PHY INT */
104 };
105
106 #define TX6_ENET_PAD_CTRL       (PAD_CTL_SPEED_HIGH |   \
107                                 PAD_CTL_DSE_48ohm |     \
108                                 PAD_CTL_PUS_100K_UP |   \
109                                 PAD_CTL_SRE_FAST)
110 #define TX6_GPIO_OUT_PAD_CTRL   (PAD_CTL_SPEED_LOW |    \
111                                 PAD_CTL_DSE_60ohm |     \
112                                 PAD_CTL_SRE_SLOW)
113 #define TX6_GPIO_IN_PAD_CTRL    (PAD_CTL_SPEED_LOW |    \
114                                 PAD_CTL_PUS_47K_UP)
115
116 static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = {
117         /* FEC functions */
118         MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_48ohm |
119                                 PAD_CTL_SPEED_MED),
120         MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
121                                 PAD_CTL_DSE_48ohm |
122                                 PAD_CTL_SPEED_MED),
123         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_CFG_SION |
124                                 MUX_PAD_CTRL(PAD_CTL_SPEED_MED |
125                                 PAD_CTL_DSE_40ohm |
126                                 PAD_CTL_SRE_FAST),
127         MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
128         MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
129         MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
130         MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
131         MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
132         MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
133         MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
134 };
135
136 static const iomux_v3_cfg_t const tx6ul_enet2_pads[] = {
137         MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_CFG_SION |
138                                 MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |
139                                 PAD_CTL_DSE_48ohm |
140                                 PAD_CTL_SRE_FAST),
141         MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
142         MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
143         MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
144         MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
145         MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
146         MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
147         MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
148 };
149
150 #define TX6_I2C_PAD_CTRL        (PAD_CTL_PUS_22K_UP |   \
151                                 PAD_CTL_SPEED_MED |     \
152                                 PAD_CTL_DSE_34ohm |     \
153                                 PAD_CTL_SRE_FAST)
154
155 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
156         /* internal I2C */
157         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
158                         MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
159         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
160                         MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
161 };
162
163 static const struct gpio const tx6ul_gpios[] = {
164         /* These two entries are used to forcefully reinitialize the I2C bus */
165         { TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
166         { TX6UL_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
167
168         { TX6UL_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
169         { TX6UL_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
170         { TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
171 };
172
173 static const struct gpio const tx6ul_fec2_gpios[] = {
174         { TX6UL_FEC2_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC2 PHY RESET", },
175         { TX6UL_FEC2_INT_GPIO, GPIOFLAG_INPUT, "FEC2 PHY INT", },
176 };
177
178 #define GPIO_DR 0
179 #define GPIO_DIR 4
180 #define GPIO_PSR 8
181
182 /* run with default environment */
183 static void tx6_i2c_recover(void)
184 {
185         int i;
186         int bad = 0;
187 #define SCL_BIT         (1 << (TX6UL_I2C1_SCL_GPIO % 32))
188 #define SDA_BIT         (1 << (TX6UL_I2C1_SDA_GPIO % 32))
189 #define I2C_GPIO_BASE   (GPIO1_BASE_ADDR + TX6UL_I2C1_SCL_GPIO / 32 * 0x4000)
190
191         if ((readl(I2C_GPIO_BASE + GPIO_PSR) &
192                         (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
193                 return;
194
195         debug("Clearing I2C bus\n");
196         if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SCL_BIT)) {
197                 printf("I2C SCL stuck LOW\n");
198                 bad++;
199
200                 writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
201                         I2C_GPIO_BASE + GPIO_DR);
202                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
203                         I2C_GPIO_BASE + GPIO_DIR);
204         }
205         if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)) {
206                 printf("I2C SDA stuck LOW\n");
207                 bad++;
208
209                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) & ~SDA_BIT,
210                         I2C_GPIO_BASE + GPIO_DIR);
211                 writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
212                         I2C_GPIO_BASE + GPIO_DR);
213                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
214                         I2C_GPIO_BASE + GPIO_DIR);
215
216                 imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
217                                                 ARRAY_SIZE(tx6_i2c_gpio_pads));
218                 udelay(10);
219
220                 for (i = 0; i < 18; i++) {
221                         u32 reg = readl(I2C_GPIO_BASE + GPIO_DR) ^ SCL_BIT;
222
223                         debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
224                         writel(reg, I2C_GPIO_BASE + GPIO_DR);
225                         udelay(10);
226                         if (reg & SCL_BIT &&
227                                 readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)
228                                 break;
229                 }
230         }
231         if (bad) {
232                 u32 reg = readl(I2C_GPIO_BASE + GPIO_PSR);
233
234                 if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
235                         printf("I2C bus recovery succeeded\n");
236                 } else {
237                         printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
238                                 SCL_BIT | SDA_BIT);
239                 }
240         }
241 }
242
243 /* placed in section '.data' to prevent overwriting relocation info
244  * overlayed with bss
245  */
246 static u32 wrsr __data;
247
248 #define WRSR_POR                        (1 << 4)
249 #define WRSR_TOUT                       (1 << 1)
250 #define WRSR_SFTW                       (1 << 0)
251
252 static void print_reset_cause(void)
253 {
254         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
255         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
256         u32 srsr;
257         char *dlm = "";
258
259         printf("Reset cause: ");
260
261         srsr = readl(&src_regs->srsr);
262         wrsr = readw(wdt_base + 4);
263
264         if (wrsr & WRSR_POR) {
265                 printf("%sPOR", dlm);
266                 dlm = " | ";
267         }
268         if (srsr & 0x00004) {
269                 printf("%sCSU", dlm);
270                 dlm = " | ";
271         }
272         if (srsr & 0x00008) {
273                 printf("%sIPP USER", dlm);
274                 dlm = " | ";
275         }
276         if (srsr & 0x00010) {
277                 if (wrsr & WRSR_SFTW) {
278                         printf("%sSOFT", dlm);
279                         dlm = " | ";
280                 }
281                 if (wrsr & WRSR_TOUT) {
282                         printf("%sWDOG", dlm);
283                         dlm = " | ";
284                 }
285         }
286         if (srsr & 0x00020) {
287                 printf("%sJTAG HIGH-Z", dlm);
288                 dlm = " | ";
289         }
290         if (srsr & 0x00040) {
291                 printf("%sJTAG SW", dlm);
292                 dlm = " | ";
293         }
294         if (srsr & 0x10000) {
295                 printf("%sWARM BOOT", dlm);
296                 dlm = " | ";
297         }
298         if (dlm[0] == '\0')
299                 printf("unknown");
300
301         printf("\n");
302 }
303
304 #ifdef CONFIG_IMX6_THERMAL
305 #include <thermal.h>
306 #include <imx_thermal.h>
307 #include <fuse.h>
308
309 static void print_temperature(void)
310 {
311         struct udevice *thermal_dev;
312         int cpu_tmp, minc, maxc, ret;
313         char const *grade_str;
314         static u32 __data thermal_calib;
315
316         puts("Temperature: ");
317         switch (get_cpu_temp_grade(&minc, &maxc)) {
318         case TEMP_AUTOMOTIVE:
319                 grade_str = "Automotive";
320                 break;
321         case TEMP_INDUSTRIAL:
322                 grade_str = "Industrial";
323                 break;
324         case TEMP_EXTCOMMERCIAL:
325                 grade_str = "Extended Commercial";
326                 break;
327         default:
328                 grade_str = "Commercial";
329         }
330         printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
331         ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
332         if (ret == 0) {
333                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
334
335                 if (ret == 0)
336                         printf(" at %dC", cpu_tmp);
337                 else
338                         puts(" - failed to read sensor data");
339         } else {
340                 puts(" - no sensor device found");
341         }
342
343         if (fuse_read(1, 6, &thermal_calib) == 0) {
344                 printf(" - calibration data 0x%08x\n", thermal_calib);
345         } else {
346                 puts(" - Failed to read thermal calib fuse\n");
347         }
348 }
349 #else
350 static inline void print_temperature(void)
351 {
352 }
353 #endif
354
355 int checkboard(void)
356 {
357         u32 cpurev = get_cpu_rev();
358         char *cpu_str = "?";
359
360         switch ((cpurev >> 12) & 0xff) {
361         case MXC_CPU_MX6SL:
362                 cpu_str = "SL";
363                 break;
364         case MXC_CPU_MX6DL:
365                 cpu_str = "DL";
366                 break;
367         case MXC_CPU_MX6SOLO:
368                 cpu_str = "SOLO";
369                 break;
370         case MXC_CPU_MX6Q:
371                 cpu_str = "Q";
372                 break;
373         case MXC_CPU_MX6UL:
374                 cpu_str = "UL";
375                 break;
376         }
377
378         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
379                 cpu_str,
380                 (cpurev & 0x000F0) >> 4,
381                 (cpurev & 0x0000F) >> 0,
382                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
383
384         print_temperature();
385         print_reset_cause();
386 #ifdef CONFIG_MX6_TEMPERATURE_HOT
387         check_cpu_temperature(1);
388 #endif
389         tx6_i2c_recover();
390         return 0;
391 }
392
393 /* serial port not initialized at this point */
394 int board_early_init_f(void)
395 {
396         return 0;
397 }
398
399 #ifndef CONFIG_MX6_TEMPERATURE_HOT
400 static bool tx6_temp_check_enabled = true;
401 #else
402 #define tx6_temp_check_enabled  0
403 #endif
404
405 static inline u8 tx6ul_mem_suffix(void)
406 {
407 #ifdef CONFIG_TX6_NAND
408         return '0';
409 #else
410         return '1';
411 #endif
412 }
413
414 /* PMIC settings */
415 #define VDD_RTC_VAL             rn5t_mV_to_regval_rtc(3000)
416 #define VDD_CORE_VAL            rn5t_mV_to_regval(1300)         /* DCDC1 */
417 #define VDD_CORE_VAL_LP         rn5t_mV_to_regval(900)
418 #define VDD_DDR_VAL             rn5t_mV_to_regval(1350)         /* DCDC3 */
419 #define VDD_DDR_VAL_LP          rn5t_mV_to_regval(1350)
420 #define VDD_HIGH_VAL            rn5t_mV_to_regval(3300)         /* DCDC4 */
421 #define VDD_HIGH_VAL_LP         rn5t_mV_to_regval(3300)
422 #define VDD_CSI_VAL             rn5t_mV_to_regval2(3300)        /* LDO4 */
423 #define VDD_CSI_VAL_LP          rn5t_mV_to_regval2(3300)
424
425 static struct pmic_regs rn5t567_regs[] = {
426         { RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, },
427         { RN5T567_DC2CTL, DC2_DC2DIS, },
428         { RN5T567_DC1DAC, VDD_CORE_VAL, },
429         { RN5T567_DC3DAC, VDD_DDR_VAL, },
430         { RN5T567_DC4DAC, VDD_HIGH_VAL, },
431         { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
432         { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
433         { RN5T567_DC4DAC_SLP, VDD_HIGH_VAL_LP, },
434         { RN5T567_LDOEN1, 0x01f, ~0x1f, },
435         { RN5T567_LDOEN2, 0x10, ~0x30, },
436         { RN5T567_LDODIS, 0x00, },
437         { RN5T567_LDO4DAC, VDD_CSI_VAL, },
438         { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
439         { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
440 };
441
442 static int pmic_addr __maybe_unused = 0x33;
443
444 int board_init(void)
445 {
446         int ret;
447
448         debug("%s@%d: \n", __func__, __LINE__);
449
450         printf("Board: Ka-Ro TXUL-001%c\n",
451                 tx6ul_mem_suffix());
452
453         get_hab_status();
454
455         ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios));
456         if (ret < 0) {
457                 printf("Failed to request tx6ul_gpios: %d\n", ret);
458         }
459         imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads));
460
461         /* Address of boot parameters */
462         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
463         gd->bd->bi_arch_number = -1;
464
465         if (ctrlc() || (wrsr & WRSR_TOUT)) {
466                 if (wrsr & WRSR_TOUT)
467                         printf("WDOG RESET detected; Skipping PMIC setup\n");
468                 else
469                         printf("<CTRL-C> detected; safeboot enabled\n");
470 #ifndef CONFIG_MX6_TEMPERATURE_HOT
471                 tx6_temp_check_enabled = false;
472 #endif
473                 return 0;
474         }
475
476         ret = tx6_pmic_init(pmic_addr, rn5t567_regs, ARRAY_SIZE(rn5t567_regs));
477         if (ret) {
478                 printf("Failed to setup PMIC voltages: %d\n", ret);
479                 hang();
480         }
481         return 0;
482 }
483
484 int dram_init(void)
485 {
486         debug("%s@%d: \n", __func__, __LINE__);
487
488         /* dram_init must store complete ramsize in gd->ram_size */
489         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
490                                 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
491         return 0;
492 }
493
494 void dram_init_banksize(void)
495 {
496         debug("%s@%d: \n", __func__, __LINE__);
497
498         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
499         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
500                         PHYS_SDRAM_1_SIZE);
501 #if CONFIG_NR_DRAM_BANKS > 1
502         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
503         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
504                         PHYS_SDRAM_2_SIZE);
505 #endif
506 }
507
508 #ifdef  CONFIG_FSL_ESDHC
509 #define TX6_SD_PAD_CTRL         (PAD_CTL_PUS_47K_UP |   \
510                                 PAD_CTL_SPEED_MED |     \
511                                 PAD_CTL_DSE_40ohm |     \
512                                 PAD_CTL_SRE_FAST)
513
514 static const iomux_v3_cfg_t mmc0_pads[] = {
515         MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
516         MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
517         MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
518         MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
519         MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
520         MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
521         /* SD1 CD */
522         MX6_PAD_NAND_CE1_B__GPIO4_IO14 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
523 };
524
525 #ifdef CONFIG_TX6_EMMC
526 static const iomux_v3_cfg_t mmc1_pads[] = {
527         MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
528         MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
529         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
530         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
531         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
532         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
533         /* eMMC RESET */
534         MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
535                                                 PAD_CTL_DSE_40ohm),
536 };
537 #endif
538
539 static struct tx6_esdhc_cfg {
540         const iomux_v3_cfg_t *pads;
541         int num_pads;
542         enum mxc_clock clkid;
543         struct fsl_esdhc_cfg cfg;
544         int cd_gpio;
545 } tx6ul_esdhc_cfg[] = {
546 #ifdef CONFIG_TX6_EMMC
547         {
548                 .pads = mmc1_pads,
549                 .num_pads = ARRAY_SIZE(mmc1_pads),
550                 .clkid = MXC_ESDHC2_CLK,
551                 .cfg = {
552                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
553                         .max_bus_width = 4,
554                 },
555                 .cd_gpio = -EINVAL,
556         },
557 #endif
558         {
559                 .pads = mmc0_pads,
560                 .num_pads = ARRAY_SIZE(mmc0_pads),
561                 .clkid = MXC_ESDHC_CLK,
562                 .cfg = {
563                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
564                         .max_bus_width = 4,
565                 },
566                 .cd_gpio = TX6UL_SD1_CD_GPIO,
567         },
568 };
569
570 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
571 {
572         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
573 }
574
575 int board_mmc_getcd(struct mmc *mmc)
576 {
577         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
578
579         if (cfg->cd_gpio < 0)
580                 return 1;
581
582         debug("SD card %d is %spresent (GPIO %d)\n",
583                 cfg - tx6ul_esdhc_cfg,
584                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
585                 cfg->cd_gpio);
586         return !gpio_get_value(cfg->cd_gpio);
587 }
588
589 int board_mmc_init(bd_t *bis)
590 {
591         int i;
592
593         debug("%s@%d: \n", __func__, __LINE__);
594
595 #ifndef CONFIG_ENV_IS_IN_MMC
596         if (!(gd->flags & GD_FLG_ENV_READY)) {
597                 printf("deferred ...");
598                 return 0;
599         }
600 #endif
601         for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) {
602                 struct mmc *mmc;
603                 struct tx6_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
604                 int ret;
605
606                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
607                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
608
609                 if (cfg->cd_gpio >= 0) {
610                         ret = gpio_request_one(cfg->cd_gpio,
611                                         GPIOFLAG_INPUT, "MMC CD");
612                         if (ret) {
613                                 printf("Error %d requesting GPIO%d_%d\n",
614                                         ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
615                                 continue;
616                         }
617                 }
618
619                 debug("%s: Initializing MMC slot %d\n", __func__, i);
620                 fsl_esdhc_initialize(bis, &cfg->cfg);
621
622                 mmc = find_mmc_device(i);
623                 if (mmc == NULL)
624                         continue;
625                 if (board_mmc_getcd(mmc))
626                         mmc_init(mmc);
627         }
628         return 0;
629 }
630 #endif /* CONFIG_CMD_MMC */
631
632 enum {
633         LED_STATE_INIT = -1,
634         LED_STATE_OFF,
635         LED_STATE_ON,
636         LED_STATE_ERR,
637 };
638
639 static inline int calc_blink_rate(void)
640 {
641         if (!tx6_temp_check_enabled)
642                 return CONFIG_SYS_HZ;
643
644         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
645                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
646                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
647 }
648
649 void show_activity(int arg)
650 {
651         static int led_state = LED_STATE_INIT;
652         static int blink_rate;
653         static ulong last;
654         int ret;
655
656         switch (led_state) {
657         case LED_STATE_ERR:
658                 return;
659
660         case LED_STATE_INIT:
661                 last = get_timer(0);
662                 ret = gpio_set_value(TX6UL_LED_GPIO, 1);
663                 if (ret)
664                         led_state = LED_STATE_ERR;
665                 else
666                         led_state = LED_STATE_ON;
667                 blink_rate = calc_blink_rate();
668                 break;
669
670         case LED_STATE_ON:
671         case LED_STATE_OFF:
672                 if (get_timer(last) > blink_rate) {
673                         blink_rate = calc_blink_rate();
674                         last = get_timer_masked();
675                         if (led_state == LED_STATE_ON) {
676                                 gpio_set_value(TX6UL_LED_GPIO, 0);
677                         } else {
678                                 gpio_set_value(TX6UL_LED_GPIO, 1);
679                         }
680                         led_state = 1 - led_state;
681                 }
682                 break;
683         }
684 }
685
686 static const iomux_v3_cfg_t stk5_pads[] = {
687         /* SW controlled LED on STK5 baseboard */
688         MX6_PAD_SNVS_TAMPER9__GPIO5_IO09,
689
690         /* I2C bus on DIMM pins 40/41 */
691         MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
692         MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
693
694         /* TSC200x PEN IRQ */
695         MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL),
696
697         /* EDT-FT5x06 Polytouch panel */
698         MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* IRQ */
699         MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* RESET */
700         MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* WAKE */
701
702         /* USBH1 */
703         MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
704         MX6_PAD_GPIO1_IO03__USB_OTG2_OC | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
705
706         /* USBOTG */
707         MX6_PAD_UART3_CTS_B__GPIO1_IO26 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
708         MX6_PAD_UART3_RTS_B__GPIO1_IO27 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
709 };
710
711 static const struct gpio stk5_gpios[] = {
712         { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
713
714         { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
715         { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
716         { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
717         { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
718         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
719 };
720
721 #ifdef CONFIG_LCD
722 static u16 tx6_cmap[256];
723 vidinfo_t panel_info = {
724         /* set to max. size supported by SoC */
725         .vl_col = 4096,
726         .vl_row = 1024,
727
728         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
729         .cmap = tx6_cmap,
730 };
731
732 static struct fb_videomode tx6_fb_modes[] = {
733 #ifndef CONFIG_SYS_LVDS_IF
734         {
735                 /* Standard VGA timing */
736                 .name           = "VGA",
737                 .refresh        = 60,
738                 .xres           = 640,
739                 .yres           = 480,
740                 .pixclock       = KHZ2PICOS(25175),
741                 .left_margin    = 48,
742                 .hsync_len      = 96,
743                 .right_margin   = 16,
744                 .upper_margin   = 31,
745                 .vsync_len      = 2,
746                 .lower_margin   = 12,
747                 .sync           = FB_SYNC_CLK_LAT_FALL,
748         },
749         {
750                 /* Emerging ETV570 640 x 480 display. Syncs low active,
751                  * DE high active, 115.2 mm x 86.4 mm display area
752                  * VGA compatible timing
753                  */
754                 .name           = "ETV570",
755                 .refresh        = 60,
756                 .xres           = 640,
757                 .yres           = 480,
758                 .pixclock       = KHZ2PICOS(25175),
759                 .left_margin    = 114,
760                 .hsync_len      = 30,
761                 .right_margin   = 16,
762                 .upper_margin   = 32,
763                 .vsync_len      = 3,
764                 .lower_margin   = 10,
765                 .sync           = FB_SYNC_CLK_LAT_FALL,
766         },
767         {
768                 /* Emerging ET0350G0DH6 320 x 240 display.
769                  * 70.08 mm x 52.56 mm display area.
770                  */
771                 .name           = "ET0350",
772                 .refresh        = 60,
773                 .xres           = 320,
774                 .yres           = 240,
775                 .pixclock       = KHZ2PICOS(6500),
776                 .left_margin    = 68 - 34,
777                 .hsync_len      = 34,
778                 .right_margin   = 20,
779                 .upper_margin   = 18 - 3,
780                 .vsync_len      = 3,
781                 .lower_margin   = 4,
782                 .sync           = FB_SYNC_CLK_LAT_FALL,
783         },
784         {
785                 /* Emerging ET0430G0DH6 480 x 272 display.
786                  * 95.04 mm x 53.856 mm display area.
787                  */
788                 .name           = "ET0430",
789                 .refresh        = 60,
790                 .xres           = 480,
791                 .yres           = 272,
792                 .pixclock       = KHZ2PICOS(9000),
793                 .left_margin    = 2,
794                 .hsync_len      = 41,
795                 .right_margin   = 2,
796                 .upper_margin   = 2,
797                 .vsync_len      = 10,
798                 .lower_margin   = 2,
799         },
800         {
801                 /* Emerging ET0500G0DH6 800 x 480 display.
802                  * 109.6 mm x 66.4 mm display area.
803                  */
804                 .name           = "ET0500",
805                 .refresh        = 60,
806                 .xres           = 800,
807                 .yres           = 480,
808                 .pixclock       = KHZ2PICOS(33260),
809                 .left_margin    = 216 - 128,
810                 .hsync_len      = 128,
811                 .right_margin   = 1056 - 800 - 216,
812                 .upper_margin   = 35 - 2,
813                 .vsync_len      = 2,
814                 .lower_margin   = 525 - 480 - 35,
815                 .sync           = FB_SYNC_CLK_LAT_FALL,
816         },
817         {
818                 /* Emerging ETQ570G0DH6 320 x 240 display.
819                  * 115.2 mm x 86.4 mm display area.
820                  */
821                 .name           = "ETQ570",
822                 .refresh        = 60,
823                 .xres           = 320,
824                 .yres           = 240,
825                 .pixclock       = KHZ2PICOS(6400),
826                 .left_margin    = 38,
827                 .hsync_len      = 30,
828                 .right_margin   = 30,
829                 .upper_margin   = 16, /* 15 according to datasheet */
830                 .vsync_len      = 3, /* TVP -> 1>x>5 */
831                 .lower_margin   = 4, /* 4.5 according to datasheet */
832                 .sync           = FB_SYNC_CLK_LAT_FALL,
833         },
834         {
835                 /* Emerging ET0700G0DH6 800 x 480 display.
836                  * 152.4 mm x 91.44 mm display area.
837                  */
838                 .name           = "ET0700",
839                 .refresh        = 60,
840                 .xres           = 800,
841                 .yres           = 480,
842                 .pixclock       = KHZ2PICOS(33260),
843                 .left_margin    = 216 - 128,
844                 .hsync_len      = 128,
845                 .right_margin   = 1056 - 800 - 216,
846                 .upper_margin   = 35 - 2,
847                 .vsync_len      = 2,
848                 .lower_margin   = 525 - 480 - 35,
849                 .sync           = FB_SYNC_CLK_LAT_FALL,
850         },
851         {
852                 /* Emerging ET070001DM6 800 x 480 display.
853                  * 152.4 mm x 91.44 mm display area.
854                  */
855                 .name           = "ET070001DM6",
856                 .refresh        = 60,
857                 .xres           = 800,
858                 .yres           = 480,
859                 .pixclock       = KHZ2PICOS(33260),
860                 .left_margin    = 216 - 128,
861                 .hsync_len      = 128,
862                 .right_margin   = 1056 - 800 - 216,
863                 .upper_margin   = 35 - 2,
864                 .vsync_len      = 2,
865                 .lower_margin   = 525 - 480 - 35,
866                 .sync           = 0,
867         },
868 #else
869         {
870                 /* HannStar HSD100PXN1
871                  * 202.7m mm x 152.06 mm display area.
872                  */
873                 .name           = "HSD100PXN1",
874                 .refresh        = 60,
875                 .xres           = 1024,
876                 .yres           = 768,
877                 .pixclock       = KHZ2PICOS(65000),
878                 .left_margin    = 0,
879                 .hsync_len      = 0,
880                 .right_margin   = 320,
881                 .upper_margin   = 0,
882                 .vsync_len      = 0,
883                 .lower_margin   = 38,
884                 .sync           = FB_SYNC_CLK_LAT_FALL,
885         },
886 #endif
887         {
888                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
889                 .refresh        = 60,
890                 .left_margin    = 48,
891                 .hsync_len      = 96,
892                 .right_margin   = 16,
893                 .upper_margin   = 31,
894                 .vsync_len      = 2,
895                 .lower_margin   = 12,
896                 .sync           = FB_SYNC_CLK_LAT_FALL,
897         },
898 };
899
900 static int lcd_enabled = 1;
901 static int lcd_bl_polarity;
902
903 static int lcd_backlight_polarity(void)
904 {
905         return lcd_bl_polarity;
906 }
907
908 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
909 #ifdef CONFIG_LCD
910         /* LCD RESET */
911         MX6_PAD_LCD_RESET__GPIO3_IO04 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
912         /* LCD POWER_ENABLE */
913         MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
914         /* LCD Backlight (PWM) */
915         MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
916         /* Display */
917         MX6_PAD_LCD_DATA00__LCDIF_DATA00,
918         MX6_PAD_LCD_DATA01__LCDIF_DATA01,
919         MX6_PAD_LCD_DATA02__LCDIF_DATA02,
920         MX6_PAD_LCD_DATA03__LCDIF_DATA03,
921         MX6_PAD_LCD_DATA04__LCDIF_DATA04,
922         MX6_PAD_LCD_DATA05__LCDIF_DATA05,
923         MX6_PAD_LCD_DATA06__LCDIF_DATA06,
924         MX6_PAD_LCD_DATA07__LCDIF_DATA07,
925         MX6_PAD_LCD_DATA08__LCDIF_DATA08,
926         MX6_PAD_LCD_DATA09__LCDIF_DATA09,
927         MX6_PAD_LCD_DATA10__LCDIF_DATA10,
928         MX6_PAD_LCD_DATA11__LCDIF_DATA11,
929         MX6_PAD_LCD_DATA12__LCDIF_DATA12,
930         MX6_PAD_LCD_DATA13__LCDIF_DATA13,
931         MX6_PAD_LCD_DATA14__LCDIF_DATA14,
932         MX6_PAD_LCD_DATA15__LCDIF_DATA15,
933         MX6_PAD_LCD_DATA16__LCDIF_DATA16,
934         MX6_PAD_LCD_DATA17__LCDIF_DATA17,
935         MX6_PAD_LCD_DATA18__LCDIF_DATA18,
936         MX6_PAD_LCD_DATA19__LCDIF_DATA19,
937         MX6_PAD_LCD_DATA20__LCDIF_DATA20,
938         MX6_PAD_LCD_DATA21__LCDIF_DATA21,
939         MX6_PAD_LCD_DATA22__LCDIF_DATA22,
940         MX6_PAD_LCD_DATA23__LCDIF_DATA23,
941         MX6_PAD_LCD_HSYNC__LCDIF_HSYNC, /* HSYNC */
942         MX6_PAD_LCD_VSYNC__LCDIF_VSYNC, /* VSYNC */
943         MX6_PAD_LCD_ENABLE__LCDIF_ENABLE, /* OE_ACD */
944         MX6_PAD_LCD_CLK__LCDIF_CLK, /* LSCLK */
945 #endif
946 };
947
948 static const struct gpio stk5_lcd_gpios[] = {
949         { TX6UL_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
950         { TX6UL_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
951         { TX6UL_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
952 };
953
954 /* run with valid env from NAND/eMMC */
955 void lcd_enable(void)
956 {
957         /* HACK ALERT:
958          * global variable from common/lcd.c
959          * Set to 0 here to prevent messages from going to LCD
960          * rather than serial console
961          */
962         lcd_is_enabled = 0;
963
964         if (lcd_enabled) {
965                 karo_load_splashimage(1);
966
967                 debug("Switching LCD on\n");
968                 gpio_set_value(TX6UL_LCD_PWR_GPIO, 1);
969                 udelay(100);
970                 gpio_set_value(TX6UL_LCD_RST_GPIO, 1);
971                 udelay(300000);
972                 gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
973                         lcd_backlight_polarity());
974         }
975 }
976
977 static void lcd_disable(void)
978 {
979         if (lcd_enabled) {
980                 printf("Disabling LCD\n");
981                 panel_info.vl_row = 0;
982                 lcd_enabled = 0;
983         }
984 }
985
986 void lcd_ctrl_init(void *lcdbase)
987 {
988         int color_depth = 24;
989         const char *video_mode = karo_get_vmode(getenv("video_mode"));
990         const char *vm;
991         unsigned long val;
992         int refresh = 60;
993         struct fb_videomode *p = &tx6_fb_modes[0];
994         struct fb_videomode fb_mode;
995         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
996
997         if (!lcd_enabled) {
998                 debug("LCD disabled\n");
999                 return;
1000         }
1001
1002         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1003                 lcd_disable();
1004                 setenv("splashimage", NULL);
1005                 return;
1006         }
1007
1008         karo_fdt_move_fdt();
1009         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1010
1011         if (video_mode == NULL) {
1012                 lcd_disable();
1013                 return;
1014         }
1015         vm = video_mode;
1016         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1017                 p = &fb_mode;
1018                 debug("Using video mode from FDT\n");
1019                 vm += strlen(vm);
1020                 if (fb_mode.xres > panel_info.vl_col ||
1021                         fb_mode.yres > panel_info.vl_row) {
1022                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1023                                 fb_mode.xres, fb_mode.yres,
1024                                 panel_info.vl_col, panel_info.vl_row);
1025                         lcd_enabled = 0;
1026                         return;
1027                 }
1028         }
1029         if (p->name != NULL)
1030                 debug("Trying compiled-in video modes\n");
1031         while (p->name != NULL) {
1032                 if (strcmp(p->name, vm) == 0) {
1033                         debug("Using video mode: '%s'\n", p->name);
1034                         vm += strlen(vm);
1035                         break;
1036                 }
1037                 p++;
1038         }
1039         if (*vm != '\0')
1040                 debug("Trying to decode video_mode: '%s'\n", vm);
1041         while (*vm != '\0') {
1042                 if (*vm >= '0' && *vm <= '9') {
1043                         char *end;
1044
1045                         val = simple_strtoul(vm, &end, 0);
1046                         if (end > vm) {
1047                                 if (!xres_set) {
1048                                         if (val > panel_info.vl_col)
1049                                                 val = panel_info.vl_col;
1050                                         p->xres = val;
1051                                         panel_info.vl_col = val;
1052                                         xres_set = 1;
1053                                 } else if (!yres_set) {
1054                                         if (val > panel_info.vl_row)
1055                                                 val = panel_info.vl_row;
1056                                         p->yres = val;
1057                                         panel_info.vl_row = val;
1058                                         yres_set = 1;
1059                                 } else if (!bpp_set) {
1060                                         switch (val) {
1061                                         case 8:
1062                                         case 16:
1063                                         case 18:
1064                                         case 24:
1065                                         case 32:
1066                                                 color_depth = val;
1067                                                 break;
1068
1069                                         default:
1070                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1071                                                         end - vm, vm, color_depth);
1072                                         }
1073                                         bpp_set = 1;
1074                                 } else if (!refresh_set) {
1075                                         refresh = val;
1076                                         refresh_set = 1;
1077                                 }
1078                         }
1079                         vm = end;
1080                 }
1081                 switch (*vm) {
1082                 case '@':
1083                         bpp_set = 1;
1084                         /* fallthru */
1085                 case '-':
1086                         yres_set = 1;
1087                         /* fallthru */
1088                 case 'x':
1089                         xres_set = 1;
1090                         /* fallthru */
1091                 case 'M':
1092                 case 'R':
1093                         vm++;
1094                         break;
1095
1096                 default:
1097                         if (*vm != '\0')
1098                                 vm++;
1099                 }
1100         }
1101         if (p->xres == 0 || p->yres == 0) {
1102                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1103                 lcd_enabled = 0;
1104                 printf("Supported video modes are:");
1105                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1106                         printf(" %s", p->name);
1107                 }
1108                 printf("\n");
1109                 return;
1110         }
1111         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1112                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1113                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1114                 lcd_enabled = 0;
1115                 return;
1116         }
1117         panel_info.vl_col = p->xres;
1118         panel_info.vl_row = p->yres;
1119
1120         switch (color_depth) {
1121         case 8:
1122                 panel_info.vl_bpix = LCD_COLOR8;
1123                 break;
1124         case 16:
1125                 panel_info.vl_bpix = LCD_COLOR16;
1126                 break;
1127         default:
1128                 panel_info.vl_bpix = LCD_COLOR32;
1129         }
1130
1131         p->pixclock = KHZ2PICOS(refresh *
1132                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1133                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1134                                 1000);
1135         debug("Pixel clock set to %lu.%03lu MHz\n",
1136                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1137
1138         if (p != &fb_mode) {
1139                 int ret;
1140
1141                 debug("Creating new display-timing node from '%s'\n",
1142                         video_mode);
1143                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1144                 if (ret)
1145                         printf("Failed to create new display-timing node from '%s': %d\n",
1146                                 video_mode, ret);
1147         }
1148
1149         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1150         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1151                                         ARRAY_SIZE(stk5_lcd_pads));
1152
1153         debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
1154                 color_depth, refresh);
1155
1156         if (karo_load_splashimage(0) == 0) {
1157                 char vmode[128];
1158
1159                 /* setup env variable for mxsfb display driver */
1160                 snprintf(vmode, sizeof(vmode),
1161                         "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
1162                         p->xres, p->yres, p->left_margin, p->right_margin,
1163                         p->upper_margin, p->lower_margin, p->hsync_len,
1164                         p->vsync_len, p->sync, p->pixclock, color_depth);
1165                 setenv("videomode", vmode);
1166
1167                 debug("Initializing LCD controller\n");
1168                 lcdif_clk_enable();
1169                 video_hw_init();
1170                 setenv("videomode", NULL);
1171         } else {
1172                 debug("Skipping initialization of LCD controller\n");
1173         }
1174 }
1175 #else
1176 #define lcd_enabled 0
1177 #endif /* CONFIG_LCD */
1178
1179 #ifndef CONFIG_ENV_IS_IN_MMC
1180 static void tx6_mmc_init(void)
1181 {
1182         puts("MMC:   ");
1183         if (board_mmc_init(gd->bd) < 0)
1184                 cpu_mmc_init(gd->bd);
1185         print_mmc_devices(',');
1186 }
1187 #else
1188 static inline void tx6_mmc_init(void)
1189 {
1190 }
1191 #endif
1192
1193 static void stk5_board_init(void)
1194 {
1195         int ret;
1196
1197         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1198         if (ret < 0) {
1199                 printf("Failed to request stk5_gpios: %d\n", ret);
1200                 return;
1201         }
1202         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1203         debug("%s@%d: \n", __func__, __LINE__);
1204 }
1205
1206 static void stk5v3_board_init(void)
1207 {
1208         debug("%s@%d: \n", __func__, __LINE__);
1209         stk5_board_init();
1210         debug("%s@%d: \n", __func__, __LINE__);
1211         tx6_mmc_init();
1212 }
1213
1214 static void stk5v5_board_init(void)
1215 {
1216         int ret;
1217
1218         stk5_board_init();
1219         tx6_mmc_init();
1220
1221         ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
1222                         "Flexcan Transceiver");
1223         if (ret) {
1224                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1225                 return;
1226         }
1227
1228         imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 |
1229                         MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL));
1230 }
1231
1232 static void tx6ul_set_cpu_clock(void)
1233 {
1234         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1235
1236         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1237                 return;
1238
1239         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1240                 printf("%s detected; skipping cpu clock change\n",
1241                         (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1242                 return;
1243         }
1244         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1245                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1246                 printf("CPU clock set to %lu.%03lu MHz\n",
1247                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1248         } else {
1249                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1250         }
1251 }
1252
1253 int board_late_init(void)
1254 {
1255         const char *baseboard;
1256
1257         debug("%s@%d: \n", __func__, __LINE__);
1258
1259         env_cleanup();
1260
1261         if (tx6_temp_check_enabled)
1262                 check_cpu_temperature(1);
1263
1264         tx6ul_set_cpu_clock();
1265
1266         if (had_ctrlc())
1267                 setenv_ulong("safeboot", 1);
1268         else if (wrsr & WRSR_TOUT)
1269                 setenv_ulong("wdreset", 1);
1270         else
1271                 karo_fdt_move_fdt();
1272
1273         baseboard = getenv("baseboard");
1274         if (!baseboard)
1275                 goto exit;
1276
1277         printf("Baseboard: %s\n", baseboard);
1278
1279         if (strncmp(baseboard, "stk5", 4) == 0) {
1280                 if ((strlen(baseboard) == 4) ||
1281                         strcmp(baseboard, "stk5-v3") == 0) {
1282                         stk5v3_board_init();
1283                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1284                         const char *otg_mode = getenv("otg_mode");
1285
1286                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1287                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1288                                         otg_mode, baseboard);
1289                                 setenv("otg_mode", "none");
1290                         }
1291                         stk5v5_board_init();
1292                 } else {
1293                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1294                                 baseboard + 4);
1295                 }
1296         } else if (strncmp(baseboard, "ulmb-", 5) == 0) {
1297                         const char *otg_mode = getenv("otg_mode");
1298
1299                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1300                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1301                                         otg_mode, baseboard);
1302                                 setenv("otg_mode", "none");
1303                         }
1304                         stk5_board_init();
1305         } else {
1306                 printf("WARNING: Unsupported baseboard: '%s'\n",
1307                         baseboard);
1308                 if (!had_ctrlc())
1309                         return -EINVAL;
1310         }
1311
1312 exit:
1313         debug("%s@%d: \n", __func__, __LINE__);
1314
1315         clear_ctrlc();
1316         return 0;
1317 }
1318
1319 #ifdef CONFIG_FEC_MXC
1320
1321 #ifndef ETH_ALEN
1322 #define ETH_ALEN 6
1323 #endif
1324
1325 static void tx6_init_mac(void)
1326 {
1327         u8 mac[ETH_ALEN];
1328         const char *baseboard = getenv("baseboard");
1329
1330         imx_get_mac_from_fuse(0, mac);
1331         if (!is_valid_ethaddr(mac)) {
1332                 printf("No valid MAC address programmed\n");
1333                 return;
1334         }
1335         printf("MAC addr from fuse: %pM\n", mac);
1336         if (!getenv("ethaddr"))
1337                 eth_setenv_enetaddr("ethaddr", mac);
1338
1339         if (!baseboard || strncmp(baseboard, "stk5", 4) == 0) {
1340                 setenv("eth1addr", NULL);
1341                 return;
1342         }
1343         if (getenv("eth1addr"))
1344                 return;
1345         imx_get_mac_from_fuse(1, mac);
1346         eth_setenv_enetaddr("eth1addr", mac);
1347 }
1348
1349 int board_eth_init(bd_t *bis)
1350 {
1351         int ret;
1352
1353         tx6_init_mac();
1354
1355         /* delay at least 21ms for the PHY internal POR signal to deassert */
1356         udelay(22000);
1357
1358         imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads,
1359                                         ARRAY_SIZE(tx6ul_enet1_pads));
1360
1361         /* Deassert RESET to the external phys */
1362         gpio_set_value(TX6UL_FEC_RST_GPIO, 1);
1363
1364         if (getenv("ethaddr")) {
1365                 ret = fecmxc_initialize_multi(bis, 0, 0, ENET_BASE_ADDR);
1366                 if (ret) {
1367                         printf("failed to initialize FEC0: %d\n", ret);
1368                         return ret;
1369                 }
1370         }
1371         if (getenv("eth1addr")) {
1372                 ret = gpio_request_array(tx6ul_fec2_gpios,
1373                                         ARRAY_SIZE(tx6ul_fec2_gpios));
1374                 if (ret < 0) {
1375                         printf("Failed to request tx6ul_fec2_gpios: %d\n", ret);
1376                 }
1377                 imx_iomux_v3_setup_multiple_pads(tx6ul_enet2_pads,
1378                                                 ARRAY_SIZE(tx6ul_enet2_pads));
1379
1380                 writel(0x00100000, 0x020c80e4); /* assert ENET2_125M_EN */
1381
1382                 /* Minimum PHY reset duration */
1383                 udelay(100);
1384                 gpio_set_value(TX6UL_FEC2_RST_GPIO, 1);
1385                 /* Wait for PHY internal POR to finish */
1386                 udelay(22000);
1387
1388                 ret = fecmxc_initialize_multi(bis, 1, 2, ENET2_BASE_ADDR);
1389                 if (ret) {
1390                         printf("failed to initialize FEC1: %d\n", ret);
1391                         return ret;
1392                 }
1393         }
1394         return 0;
1395 }
1396 #endif /* CONFIG_FEC_MXC */
1397
1398 #ifdef CONFIG_SERIAL_TAG
1399 void get_board_serial(struct tag_serialnr *serialnr)
1400 {
1401         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1402         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1403
1404         serialnr->low = readl(&fuse->cfg0);
1405         serialnr->high = readl(&fuse->cfg1);
1406 }
1407 #endif
1408
1409 #if defined(CONFIG_OF_BOARD_SETUP)
1410 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1411 #include <jffs2/jffs2.h>
1412 #include <mtd_node.h>
1413 static struct node_info nodes[] = {
1414         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1415 };
1416 #else
1417 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1418 #endif
1419
1420 static const char *tx6_touchpanels[] = {
1421         "ti,tsc2007",
1422         "edt,edt-ft5x06",
1423         "eeti,egalax_ts",
1424 };
1425
1426 int ft_board_setup(void *blob, bd_t *bd)
1427 {
1428         const char *baseboard = getenv("baseboard");
1429         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1430         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1431         int ret;
1432
1433         ret = fdt_increase_size(blob, 4096);
1434         if (ret) {
1435                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1436                 return ret;
1437         }
1438         if (stk5_v5)
1439                 karo_fdt_enable_node(blob, "stk5led", 0);
1440
1441         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1442
1443         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1444                                 ARRAY_SIZE(tx6_touchpanels));
1445         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1446         karo_fdt_fixup_flexcan(blob, stk5_v5);
1447
1448         karo_fdt_update_fb_mode(blob, video_mode);
1449
1450         return 0;
1451 }
1452 #endif /* CONFIG_OF_BOARD_SETUP */