karo: tx6ul: configure JTAG_* pads for JTAG function unless disabled by env. variable
[karo-tx-uboot.git] / board / karo / tx6 / tx6ul.c
1 /*
2  * Copyright (C) 2015 Lothar WaƟmann <LW@KARO-electronics.de>
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  *
6  */
7 #include <common.h>
8 #include <errno.h>
9 #include <libfdt.h>
10 #include <fdt_support.h>
11 #include <lcd.h>
12 #include <netdev.h>
13 #include <mmc.h>
14 #include <fsl_esdhc.h>
15 #include <video_fb.h>
16 #include <ipu.h>
17 #include <mxcfb.h>
18 #include <i2c.h>
19 #include <linux/fb.h>
20 #include <asm/io.h>
21 #include <asm/gpio.h>
22 #include <asm/arch/mx6-pins.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/hab.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/crm_regs.h>
27 #include <asm/arch/sys_proto.h>
28
29 #include "../common/karo.h"
30 #include "pmic.h"
31
32 #define __data __attribute__((section(".data")))
33
34 #define TX6UL_FEC_RST_GPIO              IMX_GPIO_NR(5, 6)
35 #define TX6UL_FEC_PWR_GPIO              IMX_GPIO_NR(5, 7)
36 #define TX6UL_FEC_INT_GPIO              IMX_GPIO_NR(5, 5)
37
38 #define TX6UL_FEC2_RST_GPIO             IMX_GPIO_NR(4, 28)
39 #define TX6UL_FEC2_INT_GPIO             IMX_GPIO_NR(4, 27)
40
41 #define TX6UL_LED_GPIO                  IMX_GPIO_NR(5, 9)
42
43 #define TX6UL_LCD_PWR_GPIO              IMX_GPIO_NR(5, 4)
44 #define TX6UL_LCD_RST_GPIO              IMX_GPIO_NR(3, 4)
45 #define TX6UL_LCD_BACKLIGHT_GPIO        IMX_GPIO_NR(4, 16)
46
47 #ifdef CONFIG_SYS_I2C_SOFT
48 #define TX6UL_I2C1_SCL_GPIO             CONFIG_SOFT_I2C_GPIO_SCL
49 #define TX6UL_I2C1_SDA_GPIO             CONFIG_SOFT_I2C_GPIO_SDA
50 #endif
51
52 #define TX6UL_SD1_CD_GPIO               IMX_GPIO_NR(4, 14)
53
54 #ifdef CONFIG_MX6_TEMPERATURE_MIN
55 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
56 #else
57 #define TEMPERATURE_MIN                 (-40)
58 #endif
59 #ifdef CONFIG_MX6_TEMPERATURE_HOT
60 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
61 #else
62 #define TEMPERATURE_HOT                 80
63 #endif
64
65 DECLARE_GLOBAL_DATA_PTR;
66
67 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
68
69 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
70 #ifdef CONFIG_SECURE_BOOT
71 char __csf_data[0] __attribute__((section(".__csf_data")));
72 #endif
73
74 #define TX6UL_DEFAULT_PAD_CTRL  MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |      \
75                                         PAD_CTL_SPEED_MED |             \
76                                         PAD_CTL_DSE_40ohm |             \
77                                         PAD_CTL_SRE_FAST)
78 #define TX6UL_I2C_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |       \
79                                         PAD_CTL_HYS |                   \
80                                         PAD_CTL_SPEED_LOW |             \
81                                         PAD_CTL_DSE_34ohm |             \
82                                         PAD_CTL_SRE_FAST)
83 #define TX6UL_ENET_PAD_CTRL     MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |       \
84                                         PAD_CTL_DSE_48ohm |             \
85                                         PAD_CTL_PUS_100K_UP |           \
86                                         PAD_CTL_SRE_FAST)
87 #define TX6UL_GPIO_OUT_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |        \
88                                         PAD_CTL_DSE_60ohm |             \
89                                         PAD_CTL_SRE_SLOW)
90 #define TX6UL_GPIO_IN_PAD_CTRL  MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |        \
91                                         PAD_CTL_PUS_47K_UP)
92
93
94 static const iomux_v3_cfg_t const tx6ul_pads[] = {
95         /* UART pads */
96 #if CONFIG_MXC_UART_BASE == UART1_BASE
97         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
98         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
99         MX6_PAD_UART1_RTS_B__UART1_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
100         MX6_PAD_UART1_CTS_B__UART1_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
101 #endif
102 #if CONFIG_MXC_UART_BASE == UART2_BASE
103         MX6_PAD_UART2_TX_DATA__UART2_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
104         MX6_PAD_UART2_RX_DATA__UART2_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
105         MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
106         MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
107 #endif
108 #if CONFIG_MXC_UART_BASE == UART5_BASE
109         MX6_PAD_GPIO1_IO04__UART5_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
110         MX6_PAD_GPIO1_IO05__UART5_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
111         MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
112         MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
113 #endif
114         /* FEC PHY GPIO functions */
115         MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY POWER */
116         MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY RESET */
117         MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | TX6UL_GPIO_IN_PAD_CTRL, /* PHY INT */
118 };
119
120 static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = {
121         /* FEC functions */
122         MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_48ohm |
123                                 PAD_CTL_SPEED_MED),
124         MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
125                                 PAD_CTL_DSE_48ohm | PAD_CTL_SPEED_MED),
126         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_CFG_SION |
127                                 MUX_PAD_CTRL(PAD_CTL_SPEED_MED |
128                                 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST),
129         MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | TX6UL_ENET_PAD_CTRL,
130         MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | TX6UL_ENET_PAD_CTRL,
131         MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | TX6UL_ENET_PAD_CTRL,
132         MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | TX6UL_ENET_PAD_CTRL,
133         MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | TX6UL_ENET_PAD_CTRL,
134         MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | TX6UL_ENET_PAD_CTRL,
135         MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | TX6UL_ENET_PAD_CTRL,
136 };
137
138 static const iomux_v3_cfg_t const tx6ul_enet2_pads[] = {
139         MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_CFG_SION |
140                                 MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |
141                                 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST),
142         MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | TX6UL_ENET_PAD_CTRL,
143         MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | TX6UL_ENET_PAD_CTRL,
144         MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | TX6UL_ENET_PAD_CTRL,
145         MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | TX6UL_ENET_PAD_CTRL,
146         MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | TX6UL_ENET_PAD_CTRL,
147         MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | TX6UL_ENET_PAD_CTRL,
148         MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | TX6UL_ENET_PAD_CTRL,
149 };
150
151 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
152         /* internal I2C */
153         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
154                         MUX_PAD_CTRL(PAD_CTL_DSE_240ohm | PAD_CTL_HYS |
155                         PAD_CTL_ODE), /* I2C SCL */
156         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
157                         MUX_PAD_CTRL(PAD_CTL_DSE_240ohm | PAD_CTL_HYS |
158                         PAD_CTL_ODE), /* I2C SDA */
159 };
160
161 static const struct gpio const tx6ul_gpios[] = {
162 #ifdef CONFIG_SYS_I2C_SOFT
163         /* These two entries are used to forcefully reinitialize the I2C bus */
164         { TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
165         { TX6UL_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
166 #endif
167         { TX6UL_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
168         { TX6UL_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
169         { TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
170 };
171
172 static const struct gpio const tx6ul_fec2_gpios[] = {
173         { TX6UL_FEC2_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC2 PHY RESET", },
174         { TX6UL_FEC2_INT_GPIO, GPIOFLAG_INPUT, "FEC2 PHY INT", },
175 };
176
177 #define GPIO_DR 0
178 #define GPIO_DIR 4
179 #define GPIO_PSR 8
180
181 /* run with default environment */
182 #if defined(TX6UL_I2C1_SCL_GPIO) && defined(TX6UL_I2C1_SDA_GPIO)
183 static void tx6_i2c_recover(void)
184 {
185         int i;
186         int bad = 0;
187 #define SCL_BIT         (1 << (TX6UL_I2C1_SCL_GPIO % 32))
188 #define SDA_BIT         (1 << (TX6UL_I2C1_SDA_GPIO % 32))
189 #define I2C_GPIO_BASE   (GPIO1_BASE_ADDR + TX6UL_I2C1_SCL_GPIO / 32 * 0x4000)
190
191         if ((readl(I2C_GPIO_BASE + GPIO_PSR) &
192                         (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
193                 return;
194
195         debug("Clearing I2C bus\n");
196         if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SCL_BIT)) {
197                 printf("I2C SCL stuck LOW\n");
198                 bad++;
199
200                 writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
201                         I2C_GPIO_BASE + GPIO_DR);
202                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
203                         I2C_GPIO_BASE + GPIO_DIR);
204         }
205         if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)) {
206                 printf("I2C SDA stuck LOW\n");
207                 bad++;
208
209                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) & ~SDA_BIT,
210                         I2C_GPIO_BASE + GPIO_DIR);
211                 writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
212                         I2C_GPIO_BASE + GPIO_DR);
213                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
214                         I2C_GPIO_BASE + GPIO_DIR);
215
216                 imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
217                                                 ARRAY_SIZE(tx6_i2c_gpio_pads));
218                 udelay(10);
219
220                 for (i = 0; i < 18; i++) {
221                         u32 reg = readl(I2C_GPIO_BASE + GPIO_DR) ^ SCL_BIT;
222
223                         debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
224                         writel(reg, I2C_GPIO_BASE + GPIO_DR);
225                         udelay(10);
226                         if (reg & SCL_BIT &&
227                                 readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)
228                                 break;
229                 }
230         }
231         if (bad) {
232                 u32 reg = readl(I2C_GPIO_BASE + GPIO_PSR);
233
234                 if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
235                         printf("I2C bus recovery succeeded\n");
236                 } else {
237                         printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
238                                 SCL_BIT | SDA_BIT);
239                 }
240         }
241 }
242 #else
243 static inline void tx6_i2c_recover(void)
244 {
245 }
246 #endif
247
248 /* placed in section '.data' to prevent overwriting relocation info
249  * overlayed with bss
250  */
251 static u32 wrsr __data;
252
253 #define WRSR_POR                        (1 << 4)
254 #define WRSR_TOUT                       (1 << 1)
255 #define WRSR_SFTW                       (1 << 0)
256
257 static void print_reset_cause(void)
258 {
259         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
260         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
261         u32 srsr;
262         char *dlm = "";
263
264         printf("Reset cause: ");
265
266         srsr = readl(&src_regs->srsr);
267         wrsr = readw(wdt_base + 4);
268
269         if (wrsr & WRSR_POR) {
270                 printf("%sPOR", dlm);
271                 dlm = " | ";
272         }
273         if (srsr & 0x00004) {
274                 printf("%sCSU", dlm);
275                 dlm = " | ";
276         }
277         if (srsr & 0x00008) {
278                 printf("%sIPP USER", dlm);
279                 dlm = " | ";
280         }
281         if (srsr & 0x00010) {
282                 if (wrsr & WRSR_SFTW) {
283                         printf("%sSOFT", dlm);
284                         dlm = " | ";
285                 }
286                 if (wrsr & WRSR_TOUT) {
287                         printf("%sWDOG", dlm);
288                         dlm = " | ";
289                 }
290         }
291         if (srsr & 0x00020) {
292                 printf("%sJTAG HIGH-Z", dlm);
293                 dlm = " | ";
294         }
295         if (srsr & 0x00040) {
296                 printf("%sJTAG SW", dlm);
297                 dlm = " | ";
298         }
299         if (srsr & 0x10000) {
300                 printf("%sWARM BOOT", dlm);
301                 dlm = " | ";
302         }
303         if (dlm[0] == '\0')
304                 printf("unknown");
305
306         printf("\n");
307 }
308
309 #ifdef CONFIG_IMX6_THERMAL
310 #include <thermal.h>
311 #include <imx_thermal.h>
312 #include <fuse.h>
313
314 static void print_temperature(void)
315 {
316         struct udevice *thermal_dev;
317         int cpu_tmp, minc, maxc, ret;
318         char const *grade_str;
319         static u32 __data thermal_calib;
320
321         puts("Temperature: ");
322         switch (get_cpu_temp_grade(&minc, &maxc)) {
323         case TEMP_AUTOMOTIVE:
324                 grade_str = "Automotive";
325                 break;
326         case TEMP_INDUSTRIAL:
327                 grade_str = "Industrial";
328                 break;
329         case TEMP_EXTCOMMERCIAL:
330                 grade_str = "Extended Commercial";
331                 break;
332         default:
333                 grade_str = "Commercial";
334         }
335         printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
336         ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
337         if (ret == 0) {
338                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
339
340                 if (ret == 0)
341                         printf(" at %dC", cpu_tmp);
342                 else
343                         puts(" - failed to read sensor data");
344         } else {
345                 puts(" - no sensor device found");
346         }
347
348         if (fuse_read(1, 6, &thermal_calib) == 0) {
349                 printf(" - calibration data 0x%08x\n", thermal_calib);
350         } else {
351                 puts(" - Failed to read thermal calib fuse\n");
352         }
353 }
354 #else
355 static inline void print_temperature(void)
356 {
357 }
358 #endif
359
360 int checkboard(void)
361 {
362         u32 cpurev = get_cpu_rev();
363         char *cpu_str = "?";
364
365         if (is_cpu_type(MXC_CPU_MX6SL))
366                 cpu_str = "SL";
367         else if (is_cpu_type(MXC_CPU_MX6DL))
368                 cpu_str = "DL";
369         else if (is_cpu_type(MXC_CPU_MX6SOLO))
370                 cpu_str = "SOLO";
371         else if (is_cpu_type(MXC_CPU_MX6Q))
372                 cpu_str = "Q";
373         else if (is_cpu_type(MXC_CPU_MX6UL))
374                 cpu_str = "UL";
375
376         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
377                 cpu_str,
378                 (cpurev & 0x000F0) >> 4,
379                 (cpurev & 0x0000F) >> 0,
380                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
381
382         print_temperature();
383         print_reset_cause();
384 #ifdef CONFIG_MX6_TEMPERATURE_HOT
385         check_cpu_temperature(1);
386 #endif
387         tx6_i2c_recover();
388         return 0;
389 }
390
391 /* serial port not initialized at this point */
392 int board_early_init_f(void)
393 {
394         return 0;
395 }
396
397 #ifndef CONFIG_MX6_TEMPERATURE_HOT
398 static bool tx6_temp_check_enabled = true;
399 #else
400 #define tx6_temp_check_enabled  0
401 #endif
402
403 static inline u8 tx6ul_mem_suffix(void)
404 {
405 #ifdef CONFIG_TX6_NAND
406         return '0';
407 #else
408         return '1';
409 #endif
410 }
411
412 #ifdef CONFIG_RN5T567
413 /* PMIC settings */
414 #define VDD_RTC_VAL             rn5t_mV_to_regval_rtc(3000)
415 #define VDD_CORE_VAL            rn5t_mV_to_regval(1300)         /* DCDC1 */
416 #define VDD_CORE_VAL_LP         rn5t_mV_to_regval(900)
417 #define VDD_DDR_VAL             rn5t_mV_to_regval(1350)         /* DCDC3 */
418 #define VDD_DDR_VAL_LP          rn5t_mV_to_regval(1350)
419 #define VDD_HIGH_VAL            rn5t_mV_to_regval(3300)         /* DCDC4 */
420 #define VDD_HIGH_VAL_LP         rn5t_mV_to_regval(3300)
421 #define VDD_CSI_VAL             rn5t_mV_to_regval2(3300)        /* LDO4 */
422 #define VDD_CSI_VAL_LP          rn5t_mV_to_regval2(3300)
423
424 static struct pmic_regs rn5t567_regs[] = {
425         { RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, },
426         { RN5T567_DC2CTL, DC2_DC2DIS, },
427         { RN5T567_DC1DAC, VDD_CORE_VAL, },
428         { RN5T567_DC3DAC, VDD_DDR_VAL, },
429         { RN5T567_DC4DAC, VDD_HIGH_VAL, },
430         { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
431         { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
432         { RN5T567_DC4DAC_SLP, VDD_HIGH_VAL_LP, },
433         { RN5T567_LDOEN1, 0x01f, ~0x1f, },
434         { RN5T567_LDOEN2, 0x10, ~0x30, },
435         { RN5T567_LDODIS, 0x00, },
436         { RN5T567_LDO4DAC, VDD_CSI_VAL, },
437         { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
438         { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
439 };
440
441 static int pmic_addr __maybe_unused = 0x33;
442 #endif
443
444 int board_init(void)
445 {
446         int ret;
447         u32 cpurev = get_cpu_rev();
448
449         debug("%s@%d: \n", __func__, __LINE__);
450
451         printf("Board: Ka-Ro TXUL-%c01%c\n",
452                 ((cpurev &0xff) > 0x10) ? '5' : '0',
453                 tx6ul_mem_suffix());
454
455         get_hab_status();
456
457         ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios));
458         if (ret < 0)
459                 printf("Failed to request tx6ul_gpios: %d\n", ret);
460
461         imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads));
462
463         /* Address of boot parameters */
464         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
465         gd->bd->bi_arch_number = -1;
466
467         if (ctrlc() || (wrsr & WRSR_TOUT)) {
468                 if (wrsr & WRSR_TOUT)
469                         printf("WDOG RESET detected; Skipping PMIC setup\n");
470                 else
471                         printf("<CTRL-C> detected; safeboot enabled\n");
472 #ifndef CONFIG_MX6_TEMPERATURE_HOT
473                 tx6_temp_check_enabled = false;
474 #endif
475                 return 0;
476         }
477
478         ret = tx6_pmic_init(pmic_addr, rn5t567_regs, ARRAY_SIZE(rn5t567_regs));
479         if (ret) {
480                 printf("Failed to setup PMIC voltages: %d\n", ret);
481                 hang();
482         }
483         return 0;
484 }
485
486 int dram_init(void)
487 {
488         debug("%s@%d: \n", __func__, __LINE__);
489
490         /* dram_init must store complete ramsize in gd->ram_size */
491         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
492                                 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
493         return 0;
494 }
495
496 void dram_init_banksize(void)
497 {
498         debug("%s@%d: \n", __func__, __LINE__);
499
500         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
501         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
502                         PHYS_SDRAM_1_SIZE);
503 #if CONFIG_NR_DRAM_BANKS > 1
504         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
505         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
506                         PHYS_SDRAM_2_SIZE);
507 #endif
508 }
509
510 #ifdef  CONFIG_FSL_ESDHC
511 #define TX6UL_SD_PAD_CTRL               MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |       \
512                                         PAD_CTL_SPEED_MED |             \
513                                         PAD_CTL_DSE_40ohm |             \
514                                         PAD_CTL_SRE_FAST)
515
516 static const iomux_v3_cfg_t mmc0_pads[] = {
517         MX6_PAD_SD1_CMD__USDHC1_CMD | TX6UL_SD_PAD_CTRL,
518         MX6_PAD_SD1_CLK__USDHC1_CLK | TX6UL_SD_PAD_CTRL,
519         MX6_PAD_SD1_DATA0__USDHC1_DATA0 | TX6UL_SD_PAD_CTRL,
520         MX6_PAD_SD1_DATA1__USDHC1_DATA1 | TX6UL_SD_PAD_CTRL,
521         MX6_PAD_SD1_DATA2__USDHC1_DATA2 | TX6UL_SD_PAD_CTRL,
522         MX6_PAD_SD1_DATA3__USDHC1_DATA3 | TX6UL_SD_PAD_CTRL,
523         /* SD1 CD */
524         MX6_PAD_NAND_CE1_B__GPIO4_IO14 | TX6UL_SD_PAD_CTRL,
525 };
526
527 #ifdef CONFIG_TX6_EMMC
528 static const iomux_v3_cfg_t mmc1_pads[] = {
529         MX6_PAD_NAND_WE_B__USDHC2_CMD | TX6UL_SD_PAD_CTRL,
530         MX6_PAD_NAND_RE_B__USDHC2_CLK | TX6UL_SD_PAD_CTRL,
531         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | TX6UL_SD_PAD_CTRL,
532         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | TX6UL_SD_PAD_CTRL,
533         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | TX6UL_SD_PAD_CTRL,
534         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | TX6UL_SD_PAD_CTRL,
535         /* eMMC RESET */
536         MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
537                                                 PAD_CTL_DSE_40ohm),
538 };
539 #endif
540
541 static struct tx6_esdhc_cfg {
542         const iomux_v3_cfg_t *pads;
543         int num_pads;
544         enum mxc_clock clkid;
545         struct fsl_esdhc_cfg cfg;
546         int cd_gpio;
547 } tx6ul_esdhc_cfg[] = {
548 #ifdef CONFIG_TX6_EMMC
549         {
550                 .pads = mmc1_pads,
551                 .num_pads = ARRAY_SIZE(mmc1_pads),
552                 .clkid = MXC_ESDHC2_CLK,
553                 .cfg = {
554                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
555                         .max_bus_width = 4,
556                 },
557                 .cd_gpio = -EINVAL,
558         },
559 #endif
560         {
561                 .pads = mmc0_pads,
562                 .num_pads = ARRAY_SIZE(mmc0_pads),
563                 .clkid = MXC_ESDHC_CLK,
564                 .cfg = {
565                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
566                         .max_bus_width = 4,
567                 },
568                 .cd_gpio = TX6UL_SD1_CD_GPIO,
569         },
570 };
571
572 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
573 {
574         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
575 }
576
577 int board_mmc_getcd(struct mmc *mmc)
578 {
579         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
580
581         if (cfg->cd_gpio < 0)
582                 return 1;
583
584         debug("SD card %d is %spresent (GPIO %d)\n",
585                 cfg - tx6ul_esdhc_cfg,
586                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
587                 cfg->cd_gpio);
588         return !gpio_get_value(cfg->cd_gpio);
589 }
590
591 int board_mmc_init(bd_t *bis)
592 {
593         int i;
594
595         debug("%s@%d: \n", __func__, __LINE__);
596
597 #ifndef CONFIG_ENV_IS_IN_MMC
598         if (!(gd->flags & GD_FLG_ENV_READY)) {
599                 printf("deferred ...");
600                 return 0;
601         }
602 #endif
603         for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) {
604                 struct mmc *mmc;
605                 struct tx6_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
606                 int ret;
607
608                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
609                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
610
611                 if (cfg->cd_gpio >= 0) {
612                         ret = gpio_request_one(cfg->cd_gpio,
613                                         GPIOFLAG_INPUT, "MMC CD");
614                         if (ret) {
615                                 printf("Error %d requesting GPIO%d_%d\n",
616                                         ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
617                                 continue;
618                         }
619                 }
620
621                 debug("%s: Initializing MMC slot %d\n", __func__, i);
622                 fsl_esdhc_initialize(bis, &cfg->cfg);
623
624                 mmc = find_mmc_device(i);
625                 if (mmc == NULL)
626                         continue;
627                 if (board_mmc_getcd(mmc))
628                         mmc_init(mmc);
629         }
630         return 0;
631 }
632 #endif /* CONFIG_FSL_ESDHC */
633
634 enum {
635         LED_STATE_INIT = -1,
636         LED_STATE_OFF,
637         LED_STATE_ON,
638         LED_STATE_ERR,
639 };
640
641 static inline int calc_blink_rate(void)
642 {
643         if (!tx6_temp_check_enabled)
644                 return CONFIG_SYS_HZ;
645
646         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
647                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
648                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
649 }
650
651 void show_activity(int arg)
652 {
653         static int led_state = LED_STATE_INIT;
654         static int blink_rate;
655         static ulong last;
656         int ret;
657
658         switch (led_state) {
659         case LED_STATE_ERR:
660                 return;
661
662         case LED_STATE_INIT:
663                 last = get_timer(0);
664                 ret = gpio_set_value(TX6UL_LED_GPIO, 1);
665                 if (ret)
666                         led_state = LED_STATE_ERR;
667                 else
668                         led_state = LED_STATE_ON;
669                 blink_rate = calc_blink_rate();
670                 break;
671
672         case LED_STATE_ON:
673         case LED_STATE_OFF:
674                 if (get_timer(last) > blink_rate) {
675                         blink_rate = calc_blink_rate();
676                         last = get_timer_masked();
677                         if (led_state == LED_STATE_ON) {
678                                 gpio_set_value(TX6UL_LED_GPIO, 0);
679                         } else {
680                                 gpio_set_value(TX6UL_LED_GPIO, 1);
681                         }
682                         led_state = 1 - led_state;
683                 }
684                 break;
685         }
686 }
687
688 static const iomux_v3_cfg_t stk5_jtag_pads[] = {
689         MX6_PAD_JTAG_MOD__SJC_MOD | TX6UL_GPIO_IN_PAD_CTRL,
690         MX6_PAD_JTAG_TCK__SJC_TCK | TX6UL_GPIO_IN_PAD_CTRL,
691         MX6_PAD_JTAG_TRST_B__SJC_TRSTB | TX6UL_GPIO_IN_PAD_CTRL,
692         MX6_PAD_JTAG_TDI__SJC_TDI | TX6UL_GPIO_IN_PAD_CTRL,
693         MX6_PAD_JTAG_TDO__SJC_TDO | TX6UL_GPIO_OUT_PAD_CTRL,
694         MX6_PAD_JTAG_TMS__SJC_TMS | TX6UL_GPIO_IN_PAD_CTRL,
695 };
696
697 static const iomux_v3_cfg_t stk5_pads[] = {
698         /* SW controlled LED on STK5 baseboard */
699         MX6_PAD_SNVS_TAMPER9__GPIO5_IO09,
700
701         /* I2C bus on DIMM pins 40/41 */
702         MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
703         MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
704
705         /* TSC200x PEN IRQ */
706         MX6_PAD_JTAG_TMS__GPIO1_IO11 | TX6UL_GPIO_IN_PAD_CTRL,
707
708         /* EDT-FT5x06 Polytouch panel */
709         MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | TX6UL_GPIO_IN_PAD_CTRL, /* IRQ */
710         MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 | TX6UL_GPIO_OUT_PAD_CTRL, /* RESET */
711         MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | TX6UL_GPIO_OUT_PAD_CTRL, /* WAKE */
712
713         /* USBH1 */
714         MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
715         MX6_PAD_GPIO1_IO03__USB_OTG2_OC | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
716
717         /* USBOTG */
718         MX6_PAD_UART3_CTS_B__GPIO1_IO26 | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
719         MX6_PAD_UART3_RTS_B__GPIO1_IO27 | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
720 };
721
722 static const struct gpio stk5_gpios[] = {
723         { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
724
725         { IMX_GPIO_NR(1, 27), GPIOFLAG_INPUT, "USBOTG OC", },
726         { IMX_GPIO_NR(1, 26), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
727 };
728
729 #ifdef CONFIG_LCD
730 vidinfo_t panel_info = {
731         /* set to max. size supported by SoC */
732         .vl_col = 4096,
733         .vl_row = 1024,
734
735         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
736 };
737
738 static struct fb_videomode tx6_fb_modes[] = {
739 #ifndef CONFIG_SYS_LVDS_IF
740         {
741                 /* Standard VGA timing */
742                 .name           = "VGA",
743                 .refresh        = 60,
744                 .xres           = 640,
745                 .yres           = 480,
746                 .pixclock       = KHZ2PICOS(25175),
747                 .left_margin    = 48,
748                 .hsync_len      = 96,
749                 .right_margin   = 16,
750                 .upper_margin   = 31,
751                 .vsync_len      = 2,
752                 .lower_margin   = 12,
753                 .sync           = FB_SYNC_CLK_LAT_FALL,
754         },
755         {
756                 /* Emerging ETV570 640 x 480 display. Syncs low active,
757                  * DE high active, 115.2 mm x 86.4 mm display area
758                  * VGA compatible timing
759                  */
760                 .name           = "ETV570",
761                 .refresh        = 60,
762                 .xres           = 640,
763                 .yres           = 480,
764                 .pixclock       = KHZ2PICOS(25175),
765                 .left_margin    = 114,
766                 .hsync_len      = 30,
767                 .right_margin   = 16,
768                 .upper_margin   = 32,
769                 .vsync_len      = 3,
770                 .lower_margin   = 10,
771                 .sync           = FB_SYNC_CLK_LAT_FALL,
772         },
773         {
774                 /* Emerging ET0350G0DH6 320 x 240 display.
775                  * 70.08 mm x 52.56 mm display area.
776                  */
777                 .name           = "ET0350",
778                 .refresh        = 60,
779                 .xres           = 320,
780                 .yres           = 240,
781                 .pixclock       = KHZ2PICOS(6500),
782                 .left_margin    = 68 - 34,
783                 .hsync_len      = 34,
784                 .right_margin   = 20,
785                 .upper_margin   = 18 - 3,
786                 .vsync_len      = 3,
787                 .lower_margin   = 4,
788                 .sync           = FB_SYNC_CLK_LAT_FALL,
789         },
790         {
791                 /* Emerging ET0430G0DH6 480 x 272 display.
792                  * 95.04 mm x 53.856 mm display area.
793                  */
794                 .name           = "ET0430",
795                 .refresh        = 60,
796                 .xres           = 480,
797                 .yres           = 272,
798                 .pixclock       = KHZ2PICOS(9000),
799                 .left_margin    = 2,
800                 .hsync_len      = 41,
801                 .right_margin   = 2,
802                 .upper_margin   = 2,
803                 .vsync_len      = 10,
804                 .lower_margin   = 2,
805         },
806         {
807                 /* Emerging ET0500G0DH6 800 x 480 display.
808                  * 109.6 mm x 66.4 mm display area.
809                  */
810                 .name           = "ET0500",
811                 .refresh        = 60,
812                 .xres           = 800,
813                 .yres           = 480,
814                 .pixclock       = KHZ2PICOS(33260),
815                 .left_margin    = 216 - 128,
816                 .hsync_len      = 128,
817                 .right_margin   = 1056 - 800 - 216,
818                 .upper_margin   = 35 - 2,
819                 .vsync_len      = 2,
820                 .lower_margin   = 525 - 480 - 35,
821                 .sync           = FB_SYNC_CLK_LAT_FALL,
822         },
823         {
824                 /* Emerging ETQ570G0DH6 320 x 240 display.
825                  * 115.2 mm x 86.4 mm display area.
826                  */
827                 .name           = "ETQ570",
828                 .refresh        = 60,
829                 .xres           = 320,
830                 .yres           = 240,
831                 .pixclock       = KHZ2PICOS(6400),
832                 .left_margin    = 38,
833                 .hsync_len      = 30,
834                 .right_margin   = 30,
835                 .upper_margin   = 16, /* 15 according to datasheet */
836                 .vsync_len      = 3, /* TVP -> 1>x>5 */
837                 .lower_margin   = 4, /* 4.5 according to datasheet */
838                 .sync           = FB_SYNC_CLK_LAT_FALL,
839         },
840         {
841                 /* Emerging ET0700G0DH6 800 x 480 display.
842                  * 152.4 mm x 91.44 mm display area.
843                  */
844                 .name           = "ET0700",
845                 .refresh        = 60,
846                 .xres           = 800,
847                 .yres           = 480,
848                 .pixclock       = KHZ2PICOS(33260),
849                 .left_margin    = 216 - 128,
850                 .hsync_len      = 128,
851                 .right_margin   = 1056 - 800 - 216,
852                 .upper_margin   = 35 - 2,
853                 .vsync_len      = 2,
854                 .lower_margin   = 525 - 480 - 35,
855                 .sync           = FB_SYNC_CLK_LAT_FALL,
856         },
857         {
858                 /* Emerging ET070001DM6 800 x 480 display.
859                  * 152.4 mm x 91.44 mm display area.
860                  */
861                 .name           = "ET070001DM6",
862                 .refresh        = 60,
863                 .xres           = 800,
864                 .yres           = 480,
865                 .pixclock       = KHZ2PICOS(33260),
866                 .left_margin    = 216 - 128,
867                 .hsync_len      = 128,
868                 .right_margin   = 1056 - 800 - 216,
869                 .upper_margin   = 35 - 2,
870                 .vsync_len      = 2,
871                 .lower_margin   = 525 - 480 - 35,
872                 .sync           = 0,
873         },
874 #else
875         {
876                 /* HannStar HSD100PXN1
877                  * 202.7m mm x 152.06 mm display area.
878                  */
879                 .name           = "HSD100PXN1",
880                 .refresh        = 60,
881                 .xres           = 1024,
882                 .yres           = 768,
883                 .pixclock       = KHZ2PICOS(65000),
884                 .left_margin    = 0,
885                 .hsync_len      = 0,
886                 .right_margin   = 320,
887                 .upper_margin   = 0,
888                 .vsync_len      = 0,
889                 .lower_margin   = 38,
890                 .sync           = FB_SYNC_CLK_LAT_FALL,
891         },
892 #endif
893         {
894                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
895                 .refresh        = 60,
896                 .left_margin    = 48,
897                 .hsync_len      = 96,
898                 .right_margin   = 16,
899                 .upper_margin   = 31,
900                 .vsync_len      = 2,
901                 .lower_margin   = 12,
902                 .sync           = FB_SYNC_CLK_LAT_FALL,
903         },
904 };
905
906 static int lcd_enabled = 1;
907 static int lcd_bl_polarity;
908
909 static int lcd_backlight_polarity(void)
910 {
911         return lcd_bl_polarity;
912 }
913
914 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
915 #ifdef CONFIG_LCD
916         /* LCD RESET */
917         MX6_PAD_LCD_RESET__GPIO3_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
918         /* LCD POWER_ENABLE */
919         MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
920         /* LCD Backlight (PWM) */
921         MX6_PAD_NAND_DQS__GPIO4_IO16 | TX6UL_GPIO_OUT_PAD_CTRL,
922         /* Display */
923         MX6_PAD_LCD_DATA00__LCDIF_DATA00,
924         MX6_PAD_LCD_DATA01__LCDIF_DATA01,
925         MX6_PAD_LCD_DATA02__LCDIF_DATA02,
926         MX6_PAD_LCD_DATA03__LCDIF_DATA03,
927         MX6_PAD_LCD_DATA04__LCDIF_DATA04,
928         MX6_PAD_LCD_DATA05__LCDIF_DATA05,
929         MX6_PAD_LCD_DATA06__LCDIF_DATA06,
930         MX6_PAD_LCD_DATA07__LCDIF_DATA07,
931         MX6_PAD_LCD_DATA08__LCDIF_DATA08,
932         MX6_PAD_LCD_DATA09__LCDIF_DATA09,
933         MX6_PAD_LCD_DATA10__LCDIF_DATA10,
934         MX6_PAD_LCD_DATA11__LCDIF_DATA11,
935         MX6_PAD_LCD_DATA12__LCDIF_DATA12,
936         MX6_PAD_LCD_DATA13__LCDIF_DATA13,
937         MX6_PAD_LCD_DATA14__LCDIF_DATA14,
938         MX6_PAD_LCD_DATA15__LCDIF_DATA15,
939         MX6_PAD_LCD_DATA16__LCDIF_DATA16,
940         MX6_PAD_LCD_DATA17__LCDIF_DATA17,
941         MX6_PAD_LCD_DATA18__LCDIF_DATA18,
942         MX6_PAD_LCD_DATA19__LCDIF_DATA19,
943         MX6_PAD_LCD_DATA20__LCDIF_DATA20,
944         MX6_PAD_LCD_DATA21__LCDIF_DATA21,
945         MX6_PAD_LCD_DATA22__LCDIF_DATA22,
946         MX6_PAD_LCD_DATA23__LCDIF_DATA23,
947         MX6_PAD_LCD_HSYNC__LCDIF_HSYNC, /* HSYNC */
948         MX6_PAD_LCD_VSYNC__LCDIF_VSYNC, /* VSYNC */
949         MX6_PAD_LCD_ENABLE__LCDIF_ENABLE, /* OE_ACD */
950         MX6_PAD_LCD_CLK__LCDIF_CLK, /* LSCLK */
951 #endif
952 };
953
954 static const struct gpio stk5_lcd_gpios[] = {
955         { TX6UL_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
956         { TX6UL_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
957         { TX6UL_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
958 };
959
960 /* run with valid env from NAND/eMMC */
961 void lcd_enable(void)
962 {
963         /* HACK ALERT:
964          * global variable from common/lcd.c
965          * Set to 0 here to prevent messages from going to LCD
966          * rather than serial console
967          */
968         lcd_is_enabled = 0;
969
970         if (lcd_enabled) {
971                 karo_load_splashimage(1);
972
973                 debug("Switching LCD on\n");
974                 gpio_set_value(TX6UL_LCD_PWR_GPIO, 1);
975                 udelay(100);
976                 gpio_set_value(TX6UL_LCD_RST_GPIO, 1);
977                 udelay(300000);
978                 gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
979                         lcd_backlight_polarity());
980         }
981 }
982
983 static void lcd_disable(void)
984 {
985         if (lcd_enabled) {
986                 printf("Disabling LCD\n");
987                 panel_info.vl_row = 0;
988                 lcd_enabled = 0;
989         }
990 }
991
992 void lcd_ctrl_init(void *lcdbase)
993 {
994         int color_depth = 24;
995         const char *video_mode = karo_get_vmode(getenv("video_mode"));
996         const char *vm;
997         unsigned long val;
998         int refresh = 60;
999         struct fb_videomode *p = &tx6_fb_modes[0];
1000         struct fb_videomode fb_mode;
1001         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1002
1003         if (!lcd_enabled) {
1004                 debug("LCD disabled\n");
1005                 return;
1006         }
1007
1008         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1009                 lcd_disable();
1010                 setenv("splashimage", NULL);
1011                 return;
1012         }
1013
1014         karo_fdt_move_fdt();
1015         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1016
1017         if (video_mode == NULL) {
1018                 lcd_disable();
1019                 return;
1020         }
1021         vm = video_mode;
1022         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1023                 p = &fb_mode;
1024                 debug("Using video mode from FDT\n");
1025                 vm += strlen(vm);
1026                 if (fb_mode.xres > panel_info.vl_col ||
1027                         fb_mode.yres > panel_info.vl_row) {
1028                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1029                                 fb_mode.xres, fb_mode.yres,
1030                                 panel_info.vl_col, panel_info.vl_row);
1031                         lcd_enabled = 0;
1032                         return;
1033                 }
1034         }
1035         if (p->name != NULL)
1036                 debug("Trying compiled-in video modes\n");
1037         while (p->name != NULL) {
1038                 if (strcmp(p->name, vm) == 0) {
1039                         debug("Using video mode: '%s'\n", p->name);
1040                         vm += strlen(vm);
1041                         break;
1042                 }
1043                 p++;
1044         }
1045         if (*vm != '\0')
1046                 debug("Trying to decode video_mode: '%s'\n", vm);
1047         while (*vm != '\0') {
1048                 if (*vm >= '0' && *vm <= '9') {
1049                         char *end;
1050
1051                         val = simple_strtoul(vm, &end, 0);
1052                         if (end > vm) {
1053                                 if (!xres_set) {
1054                                         if (val > panel_info.vl_col)
1055                                                 val = panel_info.vl_col;
1056                                         p->xres = val;
1057                                         panel_info.vl_col = val;
1058                                         xres_set = 1;
1059                                 } else if (!yres_set) {
1060                                         if (val > panel_info.vl_row)
1061                                                 val = panel_info.vl_row;
1062                                         p->yres = val;
1063                                         panel_info.vl_row = val;
1064                                         yres_set = 1;
1065                                 } else if (!bpp_set) {
1066                                         switch (val) {
1067                                         case 8:
1068                                         case 16:
1069                                         case 18:
1070                                         case 24:
1071                                         case 32:
1072                                                 color_depth = val;
1073                                                 break;
1074
1075                                         default:
1076                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1077                                                         end - vm, vm, color_depth);
1078                                         }
1079                                         bpp_set = 1;
1080                                 } else if (!refresh_set) {
1081                                         refresh = val;
1082                                         refresh_set = 1;
1083                                 }
1084                         }
1085                         vm = end;
1086                 }
1087                 switch (*vm) {
1088                 case '@':
1089                         bpp_set = 1;
1090                         /* fallthru */
1091                 case '-':
1092                         yres_set = 1;
1093                         /* fallthru */
1094                 case 'x':
1095                         xres_set = 1;
1096                         /* fallthru */
1097                 case 'M':
1098                 case 'R':
1099                         vm++;
1100                         break;
1101
1102                 default:
1103                         if (*vm != '\0')
1104                                 vm++;
1105                 }
1106         }
1107         if (p->xres == 0 || p->yres == 0) {
1108                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1109                 lcd_enabled = 0;
1110                 printf("Supported video modes are:");
1111                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1112                         printf(" %s", p->name);
1113                 }
1114                 printf("\n");
1115                 return;
1116         }
1117         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1118                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1119                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1120                 lcd_enabled = 0;
1121                 return;
1122         }
1123         panel_info.vl_col = p->xres;
1124         panel_info.vl_row = p->yres;
1125
1126         switch (color_depth) {
1127         case 8:
1128                 panel_info.vl_bpix = LCD_COLOR8;
1129                 break;
1130         case 16:
1131                 panel_info.vl_bpix = LCD_COLOR16;
1132                 break;
1133         default:
1134                 panel_info.vl_bpix = LCD_COLOR32;
1135         }
1136
1137         p->pixclock = KHZ2PICOS(refresh *
1138                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1139                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1140                                 1000);
1141         debug("Pixel clock set to %lu.%03lu MHz\n",
1142                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1143
1144         if (p != &fb_mode) {
1145                 int ret;
1146
1147                 debug("Creating new display-timing node from '%s'\n",
1148                         video_mode);
1149                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1150                 if (ret)
1151                         printf("Failed to create new display-timing node from '%s': %d\n",
1152                                 video_mode, ret);
1153         }
1154
1155         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1156         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1157                                         ARRAY_SIZE(stk5_lcd_pads));
1158
1159         debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
1160                 color_depth, refresh);
1161
1162         if (karo_load_splashimage(0) == 0) {
1163                 char vmode[128];
1164
1165                 /* setup env variable for mxsfb display driver */
1166                 snprintf(vmode, sizeof(vmode),
1167                         "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
1168                         p->xres, p->yres, p->left_margin, p->right_margin,
1169                         p->upper_margin, p->lower_margin, p->hsync_len,
1170                         p->vsync_len, p->sync, p->pixclock, color_depth);
1171                 setenv("videomode", vmode);
1172
1173                 debug("Initializing LCD controller\n");
1174                 lcdif_clk_enable();
1175                 video_hw_init();
1176                 setenv("videomode", NULL);
1177         } else {
1178                 debug("Skipping initialization of LCD controller\n");
1179         }
1180 }
1181 #else
1182 #define lcd_enabled 0
1183 #endif /* CONFIG_LCD */
1184
1185 #ifndef CONFIG_ENV_IS_IN_MMC
1186 static void tx6_mmc_init(void)
1187 {
1188         puts("MMC:   ");
1189         if (board_mmc_init(gd->bd) < 0)
1190                 cpu_mmc_init(gd->bd);
1191         print_mmc_devices(',');
1192 }
1193 #else
1194 static inline void tx6_mmc_init(void)
1195 {
1196 }
1197 #endif
1198
1199 static void stk5_board_init(void)
1200 {
1201         int ret;
1202
1203         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1204         if (ret < 0) {
1205                 printf("Failed to request stk5_gpios: %d\n", ret);
1206                 return;
1207         }
1208         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1209         if (getenv_yesno("jtag_enable") != 0) {
1210                 /* true if unset or set to one of: 'yYtT1' */
1211                 imx_iomux_v3_setup_multiple_pads(stk5_jtag_pads, ARRAY_SIZE(stk5_jtag_pads));
1212         }
1213         debug("%s@%d: \n", __func__, __LINE__);
1214 }
1215
1216 static void stk5v3_board_init(void)
1217 {
1218         debug("%s@%d: \n", __func__, __LINE__);
1219         stk5_board_init();
1220         debug("%s@%d: \n", __func__, __LINE__);
1221         tx6_mmc_init();
1222 }
1223
1224 static void stk5v5_board_init(void)
1225 {
1226         int ret;
1227
1228         stk5_board_init();
1229         tx6_mmc_init();
1230
1231         ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
1232                         "Flexcan Transceiver");
1233         if (ret) {
1234                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1235                 return;
1236         }
1237
1238         imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 |
1239                         TX6UL_GPIO_OUT_PAD_CTRL);
1240 }
1241
1242 static void tx6ul_set_cpu_clock(void)
1243 {
1244         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1245
1246         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1247                 return;
1248
1249         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1250                 printf("%s detected; skipping cpu clock change\n",
1251                         (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1252                 return;
1253         }
1254         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1255                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1256                 printf("CPU clock set to %lu.%03lu MHz\n",
1257                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1258         } else {
1259                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1260         }
1261 }
1262
1263 int board_late_init(void)
1264 {
1265         const char *baseboard;
1266
1267         debug("%s@%d: \n", __func__, __LINE__);
1268
1269         env_cleanup();
1270
1271         if (tx6_temp_check_enabled)
1272                 check_cpu_temperature(1);
1273
1274         tx6ul_set_cpu_clock();
1275
1276         if (had_ctrlc())
1277                 setenv_ulong("safeboot", 1);
1278         else if (wrsr & WRSR_TOUT)
1279                 setenv_ulong("wdreset", 1);
1280         else
1281                 karo_fdt_move_fdt();
1282
1283         baseboard = getenv("baseboard");
1284         if (!baseboard)
1285                 goto exit;
1286
1287         printf("Baseboard: %s\n", baseboard);
1288
1289         if (strncmp(baseboard, "stk5", 4) == 0) {
1290                 if ((strlen(baseboard) == 4) ||
1291                         strcmp(baseboard, "stk5-v3") == 0) {
1292                         stk5v3_board_init();
1293                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1294                         const char *otg_mode = getenv("otg_mode");
1295
1296                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1297                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1298                                         otg_mode, baseboard);
1299                                 setenv("otg_mode", "none");
1300                         }
1301                         stk5v5_board_init();
1302                 } else {
1303                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1304                                 baseboard + 4);
1305                 }
1306         } else if (strncmp(baseboard, "ulmb-", 5) == 0) {
1307                         const char *otg_mode = getenv("otg_mode");
1308
1309                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1310                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1311                                         otg_mode, baseboard);
1312                                 setenv("otg_mode", "none");
1313                         }
1314                         stk5_board_init();
1315         } else {
1316                 printf("WARNING: Unsupported baseboard: '%s'\n",
1317                         baseboard);
1318                 if (!had_ctrlc())
1319                         return -EINVAL;
1320         }
1321
1322 exit:
1323         debug("%s@%d: \n", __func__, __LINE__);
1324
1325         clear_ctrlc();
1326         return 0;
1327 }
1328
1329 #ifdef CONFIG_FEC_MXC
1330
1331 #ifndef ETH_ALEN
1332 #define ETH_ALEN 6
1333 #endif
1334
1335 static void tx6_init_mac(void)
1336 {
1337         u8 mac[ETH_ALEN];
1338         const char *baseboard = getenv("baseboard");
1339
1340         imx_get_mac_from_fuse(0, mac);
1341         if (!is_valid_ethaddr(mac)) {
1342                 printf("No valid MAC address programmed\n");
1343                 return;
1344         }
1345         printf("MAC addr from fuse: %pM\n", mac);
1346         if (!getenv("ethaddr"))
1347                 eth_setenv_enetaddr("ethaddr", mac);
1348
1349         if (!baseboard || strncmp(baseboard, "stk5", 4) == 0) {
1350                 setenv("eth1addr", NULL);
1351                 return;
1352         }
1353         if (getenv("eth1addr"))
1354                 return;
1355         imx_get_mac_from_fuse(1, mac);
1356         eth_setenv_enetaddr("eth1addr", mac);
1357 }
1358
1359 int board_eth_init(bd_t *bis)
1360 {
1361         int ret;
1362
1363         tx6_init_mac();
1364
1365         /* delay at least 21ms for the PHY internal POR signal to deassert */
1366         udelay(22000);
1367
1368         imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads,
1369                                         ARRAY_SIZE(tx6ul_enet1_pads));
1370
1371         /* Deassert RESET to the external phys */
1372         gpio_set_value(TX6UL_FEC_RST_GPIO, 1);
1373
1374         if (getenv("ethaddr")) {
1375                 ret = fecmxc_initialize_multi(bis, 0, 0, ENET_BASE_ADDR);
1376                 if (ret) {
1377                         printf("failed to initialize FEC0: %d\n", ret);
1378                         return ret;
1379                 }
1380         }
1381         if (getenv("eth1addr")) {
1382                 ret = gpio_request_array(tx6ul_fec2_gpios,
1383                                         ARRAY_SIZE(tx6ul_fec2_gpios));
1384                 if (ret < 0) {
1385                         printf("Failed to request tx6ul_fec2_gpios: %d\n", ret);
1386                 }
1387                 imx_iomux_v3_setup_multiple_pads(tx6ul_enet2_pads,
1388                                                 ARRAY_SIZE(tx6ul_enet2_pads));
1389
1390                 writel(0x00100000, 0x020c80e4); /* assert ENET2_125M_EN */
1391
1392                 /* Minimum PHY reset duration */
1393                 udelay(100);
1394                 gpio_set_value(TX6UL_FEC2_RST_GPIO, 1);
1395                 /* Wait for PHY internal POR to finish */
1396                 udelay(22000);
1397
1398                 ret = fecmxc_initialize_multi(bis, 1, 2, ENET2_BASE_ADDR);
1399                 if (ret) {
1400                         printf("failed to initialize FEC1: %d\n", ret);
1401                         return ret;
1402                 }
1403         }
1404         return 0;
1405 }
1406 #endif /* CONFIG_FEC_MXC */
1407
1408 #ifdef CONFIG_SERIAL_TAG
1409 void get_board_serial(struct tag_serialnr *serialnr)
1410 {
1411         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1412         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1413
1414         serialnr->low = readl(&fuse->cfg0);
1415         serialnr->high = readl(&fuse->cfg1);
1416 }
1417 #endif
1418
1419 #if defined(CONFIG_OF_BOARD_SETUP)
1420 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1421 #include <jffs2/jffs2.h>
1422 #include <mtd_node.h>
1423 static struct node_info nodes[] = {
1424         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1425 };
1426 #else
1427 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1428 #endif
1429
1430 static const char *tx6_touchpanels[] = {
1431         "ti,tsc2007",
1432         "edt,edt-ft5x06",
1433         "eeti,egalax_ts",
1434 };
1435
1436 int ft_board_setup(void *blob, bd_t *bd)
1437 {
1438         const char *baseboard = getenv("baseboard");
1439         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1440         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1441         int ret;
1442
1443         ret = fdt_increase_size(blob, 4096);
1444         if (ret) {
1445                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1446                 return ret;
1447         }
1448         if (stk5_v5)
1449                 karo_fdt_enable_node(blob, "stk5led", 0);
1450
1451         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1452
1453         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1454                                 ARRAY_SIZE(tx6_touchpanels));
1455         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1456         karo_fdt_fixup_flexcan(blob, stk5_v5);
1457
1458         karo_fdt_update_fb_mode(blob, video_mode);
1459
1460         return 0;
1461 }
1462 #endif /* CONFIG_OF_BOARD_SETUP */