karo: tx6: replace open coded interpretation of cpurev by calls to is_cpu_type()
[karo-tx-uboot.git] / board / karo / tx6 / tx6ul.c
1 /*
2  * Copyright (C) 2015 Lothar WaƟmann <LW@KARO-electronics.de>
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  *
6  */
7 #include <common.h>
8 #include <errno.h>
9 #include <libfdt.h>
10 #include <fdt_support.h>
11 #include <lcd.h>
12 #include <netdev.h>
13 #include <mmc.h>
14 #include <fsl_esdhc.h>
15 #include <video_fb.h>
16 #include <ipu.h>
17 #include <mxcfb.h>
18 #include <i2c.h>
19 #include <linux/fb.h>
20 #include <asm/io.h>
21 #include <asm/gpio.h>
22 #include <asm/arch/mx6-pins.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/hab.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/crm_regs.h>
27 #include <asm/arch/sys_proto.h>
28
29 #include "../common/karo.h"
30 #include "pmic.h"
31
32 #define __data __attribute__((section(".data")))
33
34 #define TX6UL_FEC_RST_GPIO              IMX_GPIO_NR(5, 6)
35 #define TX6UL_FEC_PWR_GPIO              IMX_GPIO_NR(5, 7)
36 #define TX6UL_FEC_INT_GPIO              IMX_GPIO_NR(5, 5)
37
38 #define TX6UL_FEC2_RST_GPIO             IMX_GPIO_NR(4, 28)
39 #define TX6UL_FEC2_INT_GPIO             IMX_GPIO_NR(4, 27)
40
41 #define TX6UL_LED_GPIO                  IMX_GPIO_NR(5, 9)
42
43 #define TX6UL_LCD_PWR_GPIO              IMX_GPIO_NR(5, 4)
44 #define TX6UL_LCD_RST_GPIO              IMX_GPIO_NR(3, 4)
45 #define TX6UL_LCD_BACKLIGHT_GPIO        IMX_GPIO_NR(4, 16)
46
47 #define TX6UL_I2C1_SCL_GPIO             CONFIG_SOFT_I2C_GPIO_SCL
48 #define TX6UL_I2C1_SDA_GPIO             CONFIG_SOFT_I2C_GPIO_SDA
49
50 #define TX6UL_SD1_CD_GPIO               IMX_GPIO_NR(4, 14)
51
52 #ifdef CONFIG_MX6_TEMPERATURE_MIN
53 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
54 #else
55 #define TEMPERATURE_MIN                 (-40)
56 #endif
57 #ifdef CONFIG_MX6_TEMPERATURE_HOT
58 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
59 #else
60 #define TEMPERATURE_HOT                 80
61 #endif
62
63 DECLARE_GLOBAL_DATA_PTR;
64
65 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
66
67 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
68 #ifdef CONFIG_SECURE_BOOT
69 char __csf_data[0] __attribute__((section(".__csf_data")));
70 #endif
71
72 static const iomux_v3_cfg_t const tx6ul_pads[] = {
73         /* UART pads */
74 #if CONFIG_MXC_UART_BASE == UART1_BASE
75         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX,
76         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX,
77         MX6_PAD_UART1_RTS_B__UART1_DCE_RTS,
78         MX6_PAD_UART1_CTS_B__UART1_DCE_CTS,
79 #endif
80 #if CONFIG_MXC_UART_BASE == UART2_BASE
81         MX6_PAD_UART2_TX_DATA__UART2_DCE_TX,
82         MX6_PAD_UART2_RX_DATA__UART2_DCE_RX,
83         MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS,
84         MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS,
85 #endif
86 #if CONFIG_MXC_UART_BASE == UART5_BASE
87         MX6_PAD_GPIO1_IO04__UART5_DCE_TX,
88         MX6_PAD_GPIO1_IO05__UART5_DCE_RX,
89         MX6_PAD_GPIO1_IO08__UART5_DCE_RTS,
90         MX6_PAD_GPIO1_IO09__UART5_DCE_CTS,
91 #endif
92         /* internal I2C */
93         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
94                         MUX_PAD_CTRL(PAD_CTL_DSE_240ohm), /* I2C SCL */
95         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
96                         MUX_PAD_CTRL(PAD_CTL_DSE_240ohm | PAD_CTL_HYS |
97                         PAD_CTL_ODE), /* I2C SDA */
98
99         /* FEC PHY GPIO functions */
100         MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_CFG_SION, /* PHY POWER */
101         MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | MUX_CFG_SION, /* PHY RESET */
102         MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
103                                                         PAD_CTL_DSE_40ohm), /* PHY INT */
104 };
105
106 #define TX6_ENET_PAD_CTRL       (PAD_CTL_SPEED_HIGH |   \
107                                 PAD_CTL_DSE_48ohm |     \
108                                 PAD_CTL_PUS_100K_UP |   \
109                                 PAD_CTL_SRE_FAST)
110 #define TX6_GPIO_OUT_PAD_CTRL   (PAD_CTL_SPEED_LOW |    \
111                                 PAD_CTL_DSE_60ohm |     \
112                                 PAD_CTL_SRE_SLOW)
113 #define TX6_GPIO_IN_PAD_CTRL    (PAD_CTL_SPEED_LOW |    \
114                                 PAD_CTL_PUS_47K_UP)
115
116 static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = {
117         /* FEC functions */
118         MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_48ohm |
119                                 PAD_CTL_SPEED_MED),
120         MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
121                                 PAD_CTL_DSE_48ohm |
122                                 PAD_CTL_SPEED_MED),
123         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_CFG_SION |
124                                 MUX_PAD_CTRL(PAD_CTL_SPEED_MED |
125                                 PAD_CTL_DSE_40ohm |
126                                 PAD_CTL_SRE_FAST),
127         MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
128         MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
129         MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
130         MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
131         MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
132         MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
133         MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
134 };
135
136 static const iomux_v3_cfg_t const tx6ul_enet2_pads[] = {
137         MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_CFG_SION |
138                                 MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |
139                                 PAD_CTL_DSE_48ohm |
140                                 PAD_CTL_SRE_FAST),
141         MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
142         MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
143         MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
144         MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
145         MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
146         MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
147         MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
148 };
149
150 #define TX6_I2C_PAD_CTRL        (PAD_CTL_PUS_22K_UP |   \
151                                 PAD_CTL_SPEED_MED |     \
152                                 PAD_CTL_DSE_34ohm |     \
153                                 PAD_CTL_SRE_FAST)
154
155 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
156         /* internal I2C */
157         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
158                         MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
159         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
160                         MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
161 };
162
163 static const struct gpio const tx6ul_gpios[] = {
164         /* These two entries are used to forcefully reinitialize the I2C bus */
165         { TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
166         { TX6UL_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
167
168         { TX6UL_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
169         { TX6UL_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
170         { TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
171 };
172
173 static const struct gpio const tx6ul_fec2_gpios[] = {
174         { TX6UL_FEC2_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC2 PHY RESET", },
175         { TX6UL_FEC2_INT_GPIO, GPIOFLAG_INPUT, "FEC2 PHY INT", },
176 };
177
178 #define GPIO_DR 0
179 #define GPIO_DIR 4
180 #define GPIO_PSR 8
181
182 /* run with default environment */
183 static void tx6_i2c_recover(void)
184 {
185         int i;
186         int bad = 0;
187 #define SCL_BIT         (1 << (TX6UL_I2C1_SCL_GPIO % 32))
188 #define SDA_BIT         (1 << (TX6UL_I2C1_SDA_GPIO % 32))
189 #define I2C_GPIO_BASE   (GPIO1_BASE_ADDR + TX6UL_I2C1_SCL_GPIO / 32 * 0x4000)
190
191         if ((readl(I2C_GPIO_BASE + GPIO_PSR) &
192                         (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
193                 return;
194
195         debug("Clearing I2C bus\n");
196         if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SCL_BIT)) {
197                 printf("I2C SCL stuck LOW\n");
198                 bad++;
199
200                 writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
201                         I2C_GPIO_BASE + GPIO_DR);
202                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
203                         I2C_GPIO_BASE + GPIO_DIR);
204         }
205         if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)) {
206                 printf("I2C SDA stuck LOW\n");
207                 bad++;
208
209                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) & ~SDA_BIT,
210                         I2C_GPIO_BASE + GPIO_DIR);
211                 writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
212                         I2C_GPIO_BASE + GPIO_DR);
213                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
214                         I2C_GPIO_BASE + GPIO_DIR);
215
216                 imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
217                                                 ARRAY_SIZE(tx6_i2c_gpio_pads));
218                 udelay(10);
219
220                 for (i = 0; i < 18; i++) {
221                         u32 reg = readl(I2C_GPIO_BASE + GPIO_DR) ^ SCL_BIT;
222
223                         debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
224                         writel(reg, I2C_GPIO_BASE + GPIO_DR);
225                         udelay(10);
226                         if (reg & SCL_BIT &&
227                                 readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)
228                                 break;
229                 }
230         }
231         if (bad) {
232                 u32 reg = readl(I2C_GPIO_BASE + GPIO_PSR);
233
234                 if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
235                         printf("I2C bus recovery succeeded\n");
236                 } else {
237                         printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
238                                 SCL_BIT | SDA_BIT);
239                 }
240         }
241 }
242
243 /* placed in section '.data' to prevent overwriting relocation info
244  * overlayed with bss
245  */
246 static u32 wrsr __data;
247
248 #define WRSR_POR                        (1 << 4)
249 #define WRSR_TOUT                       (1 << 1)
250 #define WRSR_SFTW                       (1 << 0)
251
252 static void print_reset_cause(void)
253 {
254         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
255         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
256         u32 srsr;
257         char *dlm = "";
258
259         printf("Reset cause: ");
260
261         srsr = readl(&src_regs->srsr);
262         wrsr = readw(wdt_base + 4);
263
264         if (wrsr & WRSR_POR) {
265                 printf("%sPOR", dlm);
266                 dlm = " | ";
267         }
268         if (srsr & 0x00004) {
269                 printf("%sCSU", dlm);
270                 dlm = " | ";
271         }
272         if (srsr & 0x00008) {
273                 printf("%sIPP USER", dlm);
274                 dlm = " | ";
275         }
276         if (srsr & 0x00010) {
277                 if (wrsr & WRSR_SFTW) {
278                         printf("%sSOFT", dlm);
279                         dlm = " | ";
280                 }
281                 if (wrsr & WRSR_TOUT) {
282                         printf("%sWDOG", dlm);
283                         dlm = " | ";
284                 }
285         }
286         if (srsr & 0x00020) {
287                 printf("%sJTAG HIGH-Z", dlm);
288                 dlm = " | ";
289         }
290         if (srsr & 0x00040) {
291                 printf("%sJTAG SW", dlm);
292                 dlm = " | ";
293         }
294         if (srsr & 0x10000) {
295                 printf("%sWARM BOOT", dlm);
296                 dlm = " | ";
297         }
298         if (dlm[0] == '\0')
299                 printf("unknown");
300
301         printf("\n");
302 }
303
304 #ifdef CONFIG_IMX6_THERMAL
305 #include <thermal.h>
306 #include <imx_thermal.h>
307 #include <fuse.h>
308
309 static void print_temperature(void)
310 {
311         struct udevice *thermal_dev;
312         int cpu_tmp, minc, maxc, ret;
313         char const *grade_str;
314         static u32 __data thermal_calib;
315
316         puts("Temperature: ");
317         switch (get_cpu_temp_grade(&minc, &maxc)) {
318         case TEMP_AUTOMOTIVE:
319                 grade_str = "Automotive";
320                 break;
321         case TEMP_INDUSTRIAL:
322                 grade_str = "Industrial";
323                 break;
324         case TEMP_EXTCOMMERCIAL:
325                 grade_str = "Extended Commercial";
326                 break;
327         default:
328                 grade_str = "Commercial";
329         }
330         printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
331         ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
332         if (ret == 0) {
333                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
334
335                 if (ret == 0)
336                         printf(" at %dC", cpu_tmp);
337                 else
338                         puts(" - failed to read sensor data");
339         } else {
340                 puts(" - no sensor device found");
341         }
342
343         if (fuse_read(1, 6, &thermal_calib) == 0) {
344                 printf(" - calibration data 0x%08x\n", thermal_calib);
345         } else {
346                 puts(" - Failed to read thermal calib fuse\n");
347         }
348 }
349 #else
350 static inline void print_temperature(void)
351 {
352 }
353 #endif
354
355 int checkboard(void)
356 {
357         u32 cpurev = get_cpu_rev();
358         char *cpu_str = "?";
359
360         if (is_cpu_type(MXC_CPU_MX6SL))
361                 cpu_str = "SL";
362         else if (is_cpu_type(MXC_CPU_MX6DL))
363                 cpu_str = "DL";
364         else if (is_cpu_type(MXC_CPU_MX6SOLO))
365                 cpu_str = "SOLO";
366         else if (is_cpu_type(MXC_CPU_MX6Q))
367                 cpu_str = "Q";
368         else if (is_cpu_type(MXC_CPU_MX6UL))
369                 cpu_str = "UL";
370
371         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
372                 cpu_str,
373                 (cpurev & 0x000F0) >> 4,
374                 (cpurev & 0x0000F) >> 0,
375                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
376
377         print_temperature();
378         print_reset_cause();
379 #ifdef CONFIG_MX6_TEMPERATURE_HOT
380         check_cpu_temperature(1);
381 #endif
382         tx6_i2c_recover();
383         return 0;
384 }
385
386 /* serial port not initialized at this point */
387 int board_early_init_f(void)
388 {
389         return 0;
390 }
391
392 #ifndef CONFIG_MX6_TEMPERATURE_HOT
393 static bool tx6_temp_check_enabled = true;
394 #else
395 #define tx6_temp_check_enabled  0
396 #endif
397
398 static inline u8 tx6ul_mem_suffix(void)
399 {
400 #ifdef CONFIG_TX6_NAND
401         return '0';
402 #else
403         return '1';
404 #endif
405 }
406
407 /* PMIC settings */
408 #define VDD_RTC_VAL             rn5t_mV_to_regval_rtc(3000)
409 #define VDD_CORE_VAL            rn5t_mV_to_regval(1300)         /* DCDC1 */
410 #define VDD_CORE_VAL_LP         rn5t_mV_to_regval(900)
411 #define VDD_DDR_VAL             rn5t_mV_to_regval(1350)         /* DCDC3 */
412 #define VDD_DDR_VAL_LP          rn5t_mV_to_regval(1350)
413 #define VDD_HIGH_VAL            rn5t_mV_to_regval(3300)         /* DCDC4 */
414 #define VDD_HIGH_VAL_LP         rn5t_mV_to_regval(3300)
415 #define VDD_CSI_VAL             rn5t_mV_to_regval2(3300)        /* LDO4 */
416 #define VDD_CSI_VAL_LP          rn5t_mV_to_regval2(3300)
417
418 static struct pmic_regs rn5t567_regs[] = {
419         { RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, },
420         { RN5T567_DC2CTL, DC2_DC2DIS, },
421         { RN5T567_DC1DAC, VDD_CORE_VAL, },
422         { RN5T567_DC3DAC, VDD_DDR_VAL, },
423         { RN5T567_DC4DAC, VDD_HIGH_VAL, },
424         { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
425         { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
426         { RN5T567_DC4DAC_SLP, VDD_HIGH_VAL_LP, },
427         { RN5T567_LDOEN1, 0x01f, ~0x1f, },
428         { RN5T567_LDOEN2, 0x10, ~0x30, },
429         { RN5T567_LDODIS, 0x00, },
430         { RN5T567_LDO4DAC, VDD_CSI_VAL, },
431         { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
432         { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
433 };
434
435 static int pmic_addr __maybe_unused = 0x33;
436
437 int board_init(void)
438 {
439         int ret;
440
441         debug("%s@%d: \n", __func__, __LINE__);
442
443         printf("Board: Ka-Ro TXUL-001%c\n",
444                 tx6ul_mem_suffix());
445
446         get_hab_status();
447
448         ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios));
449         if (ret < 0) {
450                 printf("Failed to request tx6ul_gpios: %d\n", ret);
451         }
452         imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads));
453
454         /* Address of boot parameters */
455         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
456         gd->bd->bi_arch_number = -1;
457
458         if (ctrlc() || (wrsr & WRSR_TOUT)) {
459                 if (wrsr & WRSR_TOUT)
460                         printf("WDOG RESET detected; Skipping PMIC setup\n");
461                 else
462                         printf("<CTRL-C> detected; safeboot enabled\n");
463 #ifndef CONFIG_MX6_TEMPERATURE_HOT
464                 tx6_temp_check_enabled = false;
465 #endif
466                 return 0;
467         }
468
469         ret = tx6_pmic_init(pmic_addr, rn5t567_regs, ARRAY_SIZE(rn5t567_regs));
470         if (ret) {
471                 printf("Failed to setup PMIC voltages: %d\n", ret);
472                 hang();
473         }
474         return 0;
475 }
476
477 int dram_init(void)
478 {
479         debug("%s@%d: \n", __func__, __LINE__);
480
481         /* dram_init must store complete ramsize in gd->ram_size */
482         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
483                                 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
484         return 0;
485 }
486
487 void dram_init_banksize(void)
488 {
489         debug("%s@%d: \n", __func__, __LINE__);
490
491         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
492         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
493                         PHYS_SDRAM_1_SIZE);
494 #if CONFIG_NR_DRAM_BANKS > 1
495         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
496         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
497                         PHYS_SDRAM_2_SIZE);
498 #endif
499 }
500
501 #ifdef  CONFIG_FSL_ESDHC
502 #define TX6_SD_PAD_CTRL         (PAD_CTL_PUS_47K_UP |   \
503                                 PAD_CTL_SPEED_MED |     \
504                                 PAD_CTL_DSE_40ohm |     \
505                                 PAD_CTL_SRE_FAST)
506
507 static const iomux_v3_cfg_t mmc0_pads[] = {
508         MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
509         MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
510         MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
511         MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
512         MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
513         MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
514         /* SD1 CD */
515         MX6_PAD_NAND_CE1_B__GPIO4_IO14 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
516 };
517
518 #ifdef CONFIG_TX6_EMMC
519 static const iomux_v3_cfg_t mmc1_pads[] = {
520         MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
521         MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
522         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
523         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
524         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
525         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
526         /* eMMC RESET */
527         MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
528                                                 PAD_CTL_DSE_40ohm),
529 };
530 #endif
531
532 static struct tx6_esdhc_cfg {
533         const iomux_v3_cfg_t *pads;
534         int num_pads;
535         enum mxc_clock clkid;
536         struct fsl_esdhc_cfg cfg;
537         int cd_gpio;
538 } tx6ul_esdhc_cfg[] = {
539 #ifdef CONFIG_TX6_EMMC
540         {
541                 .pads = mmc1_pads,
542                 .num_pads = ARRAY_SIZE(mmc1_pads),
543                 .clkid = MXC_ESDHC2_CLK,
544                 .cfg = {
545                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
546                         .max_bus_width = 4,
547                 },
548                 .cd_gpio = -EINVAL,
549         },
550 #endif
551         {
552                 .pads = mmc0_pads,
553                 .num_pads = ARRAY_SIZE(mmc0_pads),
554                 .clkid = MXC_ESDHC_CLK,
555                 .cfg = {
556                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
557                         .max_bus_width = 4,
558                 },
559                 .cd_gpio = TX6UL_SD1_CD_GPIO,
560         },
561 };
562
563 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
564 {
565         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
566 }
567
568 int board_mmc_getcd(struct mmc *mmc)
569 {
570         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
571
572         if (cfg->cd_gpio < 0)
573                 return 1;
574
575         debug("SD card %d is %spresent (GPIO %d)\n",
576                 cfg - tx6ul_esdhc_cfg,
577                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
578                 cfg->cd_gpio);
579         return !gpio_get_value(cfg->cd_gpio);
580 }
581
582 int board_mmc_init(bd_t *bis)
583 {
584         int i;
585
586         debug("%s@%d: \n", __func__, __LINE__);
587
588 #ifndef CONFIG_ENV_IS_IN_MMC
589         if (!(gd->flags & GD_FLG_ENV_READY)) {
590                 printf("deferred ...");
591                 return 0;
592         }
593 #endif
594         for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) {
595                 struct mmc *mmc;
596                 struct tx6_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
597                 int ret;
598
599                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
600                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
601
602                 if (cfg->cd_gpio >= 0) {
603                         ret = gpio_request_one(cfg->cd_gpio,
604                                         GPIOFLAG_INPUT, "MMC CD");
605                         if (ret) {
606                                 printf("Error %d requesting GPIO%d_%d\n",
607                                         ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
608                                 continue;
609                         }
610                 }
611
612                 debug("%s: Initializing MMC slot %d\n", __func__, i);
613                 fsl_esdhc_initialize(bis, &cfg->cfg);
614
615                 mmc = find_mmc_device(i);
616                 if (mmc == NULL)
617                         continue;
618                 if (board_mmc_getcd(mmc))
619                         mmc_init(mmc);
620         }
621         return 0;
622 }
623 #endif /* CONFIG_CMD_MMC */
624
625 enum {
626         LED_STATE_INIT = -1,
627         LED_STATE_OFF,
628         LED_STATE_ON,
629         LED_STATE_ERR,
630 };
631
632 static inline int calc_blink_rate(void)
633 {
634         if (!tx6_temp_check_enabled)
635                 return CONFIG_SYS_HZ;
636
637         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
638                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
639                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
640 }
641
642 void show_activity(int arg)
643 {
644         static int led_state = LED_STATE_INIT;
645         static int blink_rate;
646         static ulong last;
647         int ret;
648
649         switch (led_state) {
650         case LED_STATE_ERR:
651                 return;
652
653         case LED_STATE_INIT:
654                 last = get_timer(0);
655                 ret = gpio_set_value(TX6UL_LED_GPIO, 1);
656                 if (ret)
657                         led_state = LED_STATE_ERR;
658                 else
659                         led_state = LED_STATE_ON;
660                 blink_rate = calc_blink_rate();
661                 break;
662
663         case LED_STATE_ON:
664         case LED_STATE_OFF:
665                 if (get_timer(last) > blink_rate) {
666                         blink_rate = calc_blink_rate();
667                         last = get_timer_masked();
668                         if (led_state == LED_STATE_ON) {
669                                 gpio_set_value(TX6UL_LED_GPIO, 0);
670                         } else {
671                                 gpio_set_value(TX6UL_LED_GPIO, 1);
672                         }
673                         led_state = 1 - led_state;
674                 }
675                 break;
676         }
677 }
678
679 static const iomux_v3_cfg_t stk5_pads[] = {
680         /* SW controlled LED on STK5 baseboard */
681         MX6_PAD_SNVS_TAMPER9__GPIO5_IO09,
682
683         /* I2C bus on DIMM pins 40/41 */
684         MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
685         MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
686
687         /* TSC200x PEN IRQ */
688         MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL),
689
690         /* EDT-FT5x06 Polytouch panel */
691         MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* IRQ */
692         MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* RESET */
693         MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* WAKE */
694
695         /* USBH1 */
696         MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
697         MX6_PAD_GPIO1_IO03__USB_OTG2_OC | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
698
699         /* USBOTG */
700         MX6_PAD_UART3_CTS_B__GPIO1_IO26 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
701         MX6_PAD_UART3_RTS_B__GPIO1_IO27 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
702 };
703
704 static const struct gpio stk5_gpios[] = {
705         { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
706
707         { IMX_GPIO_NR(1, 27), GPIOFLAG_INPUT, "USBOTG OC", },
708         { IMX_GPIO_NR(1, 26), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
709 };
710
711 #ifdef CONFIG_LCD
712 vidinfo_t panel_info = {
713         /* set to max. size supported by SoC */
714         .vl_col = 4096,
715         .vl_row = 1024,
716
717         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
718 };
719
720 static struct fb_videomode tx6_fb_modes[] = {
721 #ifndef CONFIG_SYS_LVDS_IF
722         {
723                 /* Standard VGA timing */
724                 .name           = "VGA",
725                 .refresh        = 60,
726                 .xres           = 640,
727                 .yres           = 480,
728                 .pixclock       = KHZ2PICOS(25175),
729                 .left_margin    = 48,
730                 .hsync_len      = 96,
731                 .right_margin   = 16,
732                 .upper_margin   = 31,
733                 .vsync_len      = 2,
734                 .lower_margin   = 12,
735                 .sync           = FB_SYNC_CLK_LAT_FALL,
736         },
737         {
738                 /* Emerging ETV570 640 x 480 display. Syncs low active,
739                  * DE high active, 115.2 mm x 86.4 mm display area
740                  * VGA compatible timing
741                  */
742                 .name           = "ETV570",
743                 .refresh        = 60,
744                 .xres           = 640,
745                 .yres           = 480,
746                 .pixclock       = KHZ2PICOS(25175),
747                 .left_margin    = 114,
748                 .hsync_len      = 30,
749                 .right_margin   = 16,
750                 .upper_margin   = 32,
751                 .vsync_len      = 3,
752                 .lower_margin   = 10,
753                 .sync           = FB_SYNC_CLK_LAT_FALL,
754         },
755         {
756                 /* Emerging ET0350G0DH6 320 x 240 display.
757                  * 70.08 mm x 52.56 mm display area.
758                  */
759                 .name           = "ET0350",
760                 .refresh        = 60,
761                 .xres           = 320,
762                 .yres           = 240,
763                 .pixclock       = KHZ2PICOS(6500),
764                 .left_margin    = 68 - 34,
765                 .hsync_len      = 34,
766                 .right_margin   = 20,
767                 .upper_margin   = 18 - 3,
768                 .vsync_len      = 3,
769                 .lower_margin   = 4,
770                 .sync           = FB_SYNC_CLK_LAT_FALL,
771         },
772         {
773                 /* Emerging ET0430G0DH6 480 x 272 display.
774                  * 95.04 mm x 53.856 mm display area.
775                  */
776                 .name           = "ET0430",
777                 .refresh        = 60,
778                 .xres           = 480,
779                 .yres           = 272,
780                 .pixclock       = KHZ2PICOS(9000),
781                 .left_margin    = 2,
782                 .hsync_len      = 41,
783                 .right_margin   = 2,
784                 .upper_margin   = 2,
785                 .vsync_len      = 10,
786                 .lower_margin   = 2,
787         },
788         {
789                 /* Emerging ET0500G0DH6 800 x 480 display.
790                  * 109.6 mm x 66.4 mm display area.
791                  */
792                 .name           = "ET0500",
793                 .refresh        = 60,
794                 .xres           = 800,
795                 .yres           = 480,
796                 .pixclock       = KHZ2PICOS(33260),
797                 .left_margin    = 216 - 128,
798                 .hsync_len      = 128,
799                 .right_margin   = 1056 - 800 - 216,
800                 .upper_margin   = 35 - 2,
801                 .vsync_len      = 2,
802                 .lower_margin   = 525 - 480 - 35,
803                 .sync           = FB_SYNC_CLK_LAT_FALL,
804         },
805         {
806                 /* Emerging ETQ570G0DH6 320 x 240 display.
807                  * 115.2 mm x 86.4 mm display area.
808                  */
809                 .name           = "ETQ570",
810                 .refresh        = 60,
811                 .xres           = 320,
812                 .yres           = 240,
813                 .pixclock       = KHZ2PICOS(6400),
814                 .left_margin    = 38,
815                 .hsync_len      = 30,
816                 .right_margin   = 30,
817                 .upper_margin   = 16, /* 15 according to datasheet */
818                 .vsync_len      = 3, /* TVP -> 1>x>5 */
819                 .lower_margin   = 4, /* 4.5 according to datasheet */
820                 .sync           = FB_SYNC_CLK_LAT_FALL,
821         },
822         {
823                 /* Emerging ET0700G0DH6 800 x 480 display.
824                  * 152.4 mm x 91.44 mm display area.
825                  */
826                 .name           = "ET0700",
827                 .refresh        = 60,
828                 .xres           = 800,
829                 .yres           = 480,
830                 .pixclock       = KHZ2PICOS(33260),
831                 .left_margin    = 216 - 128,
832                 .hsync_len      = 128,
833                 .right_margin   = 1056 - 800 - 216,
834                 .upper_margin   = 35 - 2,
835                 .vsync_len      = 2,
836                 .lower_margin   = 525 - 480 - 35,
837                 .sync           = FB_SYNC_CLK_LAT_FALL,
838         },
839         {
840                 /* Emerging ET070001DM6 800 x 480 display.
841                  * 152.4 mm x 91.44 mm display area.
842                  */
843                 .name           = "ET070001DM6",
844                 .refresh        = 60,
845                 .xres           = 800,
846                 .yres           = 480,
847                 .pixclock       = KHZ2PICOS(33260),
848                 .left_margin    = 216 - 128,
849                 .hsync_len      = 128,
850                 .right_margin   = 1056 - 800 - 216,
851                 .upper_margin   = 35 - 2,
852                 .vsync_len      = 2,
853                 .lower_margin   = 525 - 480 - 35,
854                 .sync           = 0,
855         },
856 #else
857         {
858                 /* HannStar HSD100PXN1
859                  * 202.7m mm x 152.06 mm display area.
860                  */
861                 .name           = "HSD100PXN1",
862                 .refresh        = 60,
863                 .xres           = 1024,
864                 .yres           = 768,
865                 .pixclock       = KHZ2PICOS(65000),
866                 .left_margin    = 0,
867                 .hsync_len      = 0,
868                 .right_margin   = 320,
869                 .upper_margin   = 0,
870                 .vsync_len      = 0,
871                 .lower_margin   = 38,
872                 .sync           = FB_SYNC_CLK_LAT_FALL,
873         },
874 #endif
875         {
876                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
877                 .refresh        = 60,
878                 .left_margin    = 48,
879                 .hsync_len      = 96,
880                 .right_margin   = 16,
881                 .upper_margin   = 31,
882                 .vsync_len      = 2,
883                 .lower_margin   = 12,
884                 .sync           = FB_SYNC_CLK_LAT_FALL,
885         },
886 };
887
888 static int lcd_enabled = 1;
889 static int lcd_bl_polarity;
890
891 static int lcd_backlight_polarity(void)
892 {
893         return lcd_bl_polarity;
894 }
895
896 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
897 #ifdef CONFIG_LCD
898         /* LCD RESET */
899         MX6_PAD_LCD_RESET__GPIO3_IO04 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
900         /* LCD POWER_ENABLE */
901         MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
902         /* LCD Backlight (PWM) */
903         MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
904         /* Display */
905         MX6_PAD_LCD_DATA00__LCDIF_DATA00,
906         MX6_PAD_LCD_DATA01__LCDIF_DATA01,
907         MX6_PAD_LCD_DATA02__LCDIF_DATA02,
908         MX6_PAD_LCD_DATA03__LCDIF_DATA03,
909         MX6_PAD_LCD_DATA04__LCDIF_DATA04,
910         MX6_PAD_LCD_DATA05__LCDIF_DATA05,
911         MX6_PAD_LCD_DATA06__LCDIF_DATA06,
912         MX6_PAD_LCD_DATA07__LCDIF_DATA07,
913         MX6_PAD_LCD_DATA08__LCDIF_DATA08,
914         MX6_PAD_LCD_DATA09__LCDIF_DATA09,
915         MX6_PAD_LCD_DATA10__LCDIF_DATA10,
916         MX6_PAD_LCD_DATA11__LCDIF_DATA11,
917         MX6_PAD_LCD_DATA12__LCDIF_DATA12,
918         MX6_PAD_LCD_DATA13__LCDIF_DATA13,
919         MX6_PAD_LCD_DATA14__LCDIF_DATA14,
920         MX6_PAD_LCD_DATA15__LCDIF_DATA15,
921         MX6_PAD_LCD_DATA16__LCDIF_DATA16,
922         MX6_PAD_LCD_DATA17__LCDIF_DATA17,
923         MX6_PAD_LCD_DATA18__LCDIF_DATA18,
924         MX6_PAD_LCD_DATA19__LCDIF_DATA19,
925         MX6_PAD_LCD_DATA20__LCDIF_DATA20,
926         MX6_PAD_LCD_DATA21__LCDIF_DATA21,
927         MX6_PAD_LCD_DATA22__LCDIF_DATA22,
928         MX6_PAD_LCD_DATA23__LCDIF_DATA23,
929         MX6_PAD_LCD_HSYNC__LCDIF_HSYNC, /* HSYNC */
930         MX6_PAD_LCD_VSYNC__LCDIF_VSYNC, /* VSYNC */
931         MX6_PAD_LCD_ENABLE__LCDIF_ENABLE, /* OE_ACD */
932         MX6_PAD_LCD_CLK__LCDIF_CLK, /* LSCLK */
933 #endif
934 };
935
936 static const struct gpio stk5_lcd_gpios[] = {
937         { TX6UL_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
938         { TX6UL_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
939         { TX6UL_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
940 };
941
942 /* run with valid env from NAND/eMMC */
943 void lcd_enable(void)
944 {
945         /* HACK ALERT:
946          * global variable from common/lcd.c
947          * Set to 0 here to prevent messages from going to LCD
948          * rather than serial console
949          */
950         lcd_is_enabled = 0;
951
952         if (lcd_enabled) {
953                 karo_load_splashimage(1);
954
955                 debug("Switching LCD on\n");
956                 gpio_set_value(TX6UL_LCD_PWR_GPIO, 1);
957                 udelay(100);
958                 gpio_set_value(TX6UL_LCD_RST_GPIO, 1);
959                 udelay(300000);
960                 gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
961                         lcd_backlight_polarity());
962         }
963 }
964
965 static void lcd_disable(void)
966 {
967         if (lcd_enabled) {
968                 printf("Disabling LCD\n");
969                 panel_info.vl_row = 0;
970                 lcd_enabled = 0;
971         }
972 }
973
974 void lcd_ctrl_init(void *lcdbase)
975 {
976         int color_depth = 24;
977         const char *video_mode = karo_get_vmode(getenv("video_mode"));
978         const char *vm;
979         unsigned long val;
980         int refresh = 60;
981         struct fb_videomode *p = &tx6_fb_modes[0];
982         struct fb_videomode fb_mode;
983         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
984
985         if (!lcd_enabled) {
986                 debug("LCD disabled\n");
987                 return;
988         }
989
990         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
991                 lcd_disable();
992                 setenv("splashimage", NULL);
993                 return;
994         }
995
996         karo_fdt_move_fdt();
997         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
998
999         if (video_mode == NULL) {
1000                 lcd_disable();
1001                 return;
1002         }
1003         vm = video_mode;
1004         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1005                 p = &fb_mode;
1006                 debug("Using video mode from FDT\n");
1007                 vm += strlen(vm);
1008                 if (fb_mode.xres > panel_info.vl_col ||
1009                         fb_mode.yres > panel_info.vl_row) {
1010                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1011                                 fb_mode.xres, fb_mode.yres,
1012                                 panel_info.vl_col, panel_info.vl_row);
1013                         lcd_enabled = 0;
1014                         return;
1015                 }
1016         }
1017         if (p->name != NULL)
1018                 debug("Trying compiled-in video modes\n");
1019         while (p->name != NULL) {
1020                 if (strcmp(p->name, vm) == 0) {
1021                         debug("Using video mode: '%s'\n", p->name);
1022                         vm += strlen(vm);
1023                         break;
1024                 }
1025                 p++;
1026         }
1027         if (*vm != '\0')
1028                 debug("Trying to decode video_mode: '%s'\n", vm);
1029         while (*vm != '\0') {
1030                 if (*vm >= '0' && *vm <= '9') {
1031                         char *end;
1032
1033                         val = simple_strtoul(vm, &end, 0);
1034                         if (end > vm) {
1035                                 if (!xres_set) {
1036                                         if (val > panel_info.vl_col)
1037                                                 val = panel_info.vl_col;
1038                                         p->xres = val;
1039                                         panel_info.vl_col = val;
1040                                         xres_set = 1;
1041                                 } else if (!yres_set) {
1042                                         if (val > panel_info.vl_row)
1043                                                 val = panel_info.vl_row;
1044                                         p->yres = val;
1045                                         panel_info.vl_row = val;
1046                                         yres_set = 1;
1047                                 } else if (!bpp_set) {
1048                                         switch (val) {
1049                                         case 8:
1050                                         case 16:
1051                                         case 18:
1052                                         case 24:
1053                                         case 32:
1054                                                 color_depth = val;
1055                                                 break;
1056
1057                                         default:
1058                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1059                                                         end - vm, vm, color_depth);
1060                                         }
1061                                         bpp_set = 1;
1062                                 } else if (!refresh_set) {
1063                                         refresh = val;
1064                                         refresh_set = 1;
1065                                 }
1066                         }
1067                         vm = end;
1068                 }
1069                 switch (*vm) {
1070                 case '@':
1071                         bpp_set = 1;
1072                         /* fallthru */
1073                 case '-':
1074                         yres_set = 1;
1075                         /* fallthru */
1076                 case 'x':
1077                         xres_set = 1;
1078                         /* fallthru */
1079                 case 'M':
1080                 case 'R':
1081                         vm++;
1082                         break;
1083
1084                 default:
1085                         if (*vm != '\0')
1086                                 vm++;
1087                 }
1088         }
1089         if (p->xres == 0 || p->yres == 0) {
1090                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1091                 lcd_enabled = 0;
1092                 printf("Supported video modes are:");
1093                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1094                         printf(" %s", p->name);
1095                 }
1096                 printf("\n");
1097                 return;
1098         }
1099         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1100                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1101                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1102                 lcd_enabled = 0;
1103                 return;
1104         }
1105         panel_info.vl_col = p->xres;
1106         panel_info.vl_row = p->yres;
1107
1108         switch (color_depth) {
1109         case 8:
1110                 panel_info.vl_bpix = LCD_COLOR8;
1111                 break;
1112         case 16:
1113                 panel_info.vl_bpix = LCD_COLOR16;
1114                 break;
1115         default:
1116                 panel_info.vl_bpix = LCD_COLOR32;
1117         }
1118
1119         p->pixclock = KHZ2PICOS(refresh *
1120                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1121                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1122                                 1000);
1123         debug("Pixel clock set to %lu.%03lu MHz\n",
1124                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1125
1126         if (p != &fb_mode) {
1127                 int ret;
1128
1129                 debug("Creating new display-timing node from '%s'\n",
1130                         video_mode);
1131                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1132                 if (ret)
1133                         printf("Failed to create new display-timing node from '%s': %d\n",
1134                                 video_mode, ret);
1135         }
1136
1137         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1138         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1139                                         ARRAY_SIZE(stk5_lcd_pads));
1140
1141         debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
1142                 color_depth, refresh);
1143
1144         if (karo_load_splashimage(0) == 0) {
1145                 char vmode[128];
1146
1147                 /* setup env variable for mxsfb display driver */
1148                 snprintf(vmode, sizeof(vmode),
1149                         "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
1150                         p->xres, p->yres, p->left_margin, p->right_margin,
1151                         p->upper_margin, p->lower_margin, p->hsync_len,
1152                         p->vsync_len, p->sync, p->pixclock, color_depth);
1153                 setenv("videomode", vmode);
1154
1155                 debug("Initializing LCD controller\n");
1156                 lcdif_clk_enable();
1157                 video_hw_init();
1158                 setenv("videomode", NULL);
1159         } else {
1160                 debug("Skipping initialization of LCD controller\n");
1161         }
1162 }
1163 #else
1164 #define lcd_enabled 0
1165 #endif /* CONFIG_LCD */
1166
1167 #ifndef CONFIG_ENV_IS_IN_MMC
1168 static void tx6_mmc_init(void)
1169 {
1170         puts("MMC:   ");
1171         if (board_mmc_init(gd->bd) < 0)
1172                 cpu_mmc_init(gd->bd);
1173         print_mmc_devices(',');
1174 }
1175 #else
1176 static inline void tx6_mmc_init(void)
1177 {
1178 }
1179 #endif
1180
1181 static void stk5_board_init(void)
1182 {
1183         int ret;
1184
1185         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1186         if (ret < 0) {
1187                 printf("Failed to request stk5_gpios: %d\n", ret);
1188                 return;
1189         }
1190         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1191         debug("%s@%d: \n", __func__, __LINE__);
1192 }
1193
1194 static void stk5v3_board_init(void)
1195 {
1196         debug("%s@%d: \n", __func__, __LINE__);
1197         stk5_board_init();
1198         debug("%s@%d: \n", __func__, __LINE__);
1199         tx6_mmc_init();
1200 }
1201
1202 static void stk5v5_board_init(void)
1203 {
1204         int ret;
1205
1206         stk5_board_init();
1207         tx6_mmc_init();
1208
1209         ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
1210                         "Flexcan Transceiver");
1211         if (ret) {
1212                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1213                 return;
1214         }
1215
1216         imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 |
1217                         MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL));
1218 }
1219
1220 static void tx6ul_set_cpu_clock(void)
1221 {
1222         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1223
1224         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1225                 return;
1226
1227         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1228                 printf("%s detected; skipping cpu clock change\n",
1229                         (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1230                 return;
1231         }
1232         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1233                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1234                 printf("CPU clock set to %lu.%03lu MHz\n",
1235                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1236         } else {
1237                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1238         }
1239 }
1240
1241 int board_late_init(void)
1242 {
1243         const char *baseboard;
1244
1245         debug("%s@%d: \n", __func__, __LINE__);
1246
1247         env_cleanup();
1248
1249         if (tx6_temp_check_enabled)
1250                 check_cpu_temperature(1);
1251
1252         tx6ul_set_cpu_clock();
1253
1254         if (had_ctrlc())
1255                 setenv_ulong("safeboot", 1);
1256         else if (wrsr & WRSR_TOUT)
1257                 setenv_ulong("wdreset", 1);
1258         else
1259                 karo_fdt_move_fdt();
1260
1261         baseboard = getenv("baseboard");
1262         if (!baseboard)
1263                 goto exit;
1264
1265         printf("Baseboard: %s\n", baseboard);
1266
1267         if (strncmp(baseboard, "stk5", 4) == 0) {
1268                 if ((strlen(baseboard) == 4) ||
1269                         strcmp(baseboard, "stk5-v3") == 0) {
1270                         stk5v3_board_init();
1271                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1272                         const char *otg_mode = getenv("otg_mode");
1273
1274                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1275                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1276                                         otg_mode, baseboard);
1277                                 setenv("otg_mode", "none");
1278                         }
1279                         stk5v5_board_init();
1280                 } else {
1281                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1282                                 baseboard + 4);
1283                 }
1284         } else if (strncmp(baseboard, "ulmb-", 5) == 0) {
1285                         const char *otg_mode = getenv("otg_mode");
1286
1287                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1288                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1289                                         otg_mode, baseboard);
1290                                 setenv("otg_mode", "none");
1291                         }
1292                         stk5_board_init();
1293         } else {
1294                 printf("WARNING: Unsupported baseboard: '%s'\n",
1295                         baseboard);
1296                 if (!had_ctrlc())
1297                         return -EINVAL;
1298         }
1299
1300 exit:
1301         debug("%s@%d: \n", __func__, __LINE__);
1302
1303         clear_ctrlc();
1304         return 0;
1305 }
1306
1307 #ifdef CONFIG_FEC_MXC
1308
1309 #ifndef ETH_ALEN
1310 #define ETH_ALEN 6
1311 #endif
1312
1313 static void tx6_init_mac(void)
1314 {
1315         u8 mac[ETH_ALEN];
1316         const char *baseboard = getenv("baseboard");
1317
1318         imx_get_mac_from_fuse(0, mac);
1319         if (!is_valid_ethaddr(mac)) {
1320                 printf("No valid MAC address programmed\n");
1321                 return;
1322         }
1323         printf("MAC addr from fuse: %pM\n", mac);
1324         if (!getenv("ethaddr"))
1325                 eth_setenv_enetaddr("ethaddr", mac);
1326
1327         if (!baseboard || strncmp(baseboard, "stk5", 4) == 0) {
1328                 setenv("eth1addr", NULL);
1329                 return;
1330         }
1331         if (getenv("eth1addr"))
1332                 return;
1333         imx_get_mac_from_fuse(1, mac);
1334         eth_setenv_enetaddr("eth1addr", mac);
1335 }
1336
1337 int board_eth_init(bd_t *bis)
1338 {
1339         int ret;
1340
1341         tx6_init_mac();
1342
1343         /* delay at least 21ms for the PHY internal POR signal to deassert */
1344         udelay(22000);
1345
1346         imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads,
1347                                         ARRAY_SIZE(tx6ul_enet1_pads));
1348
1349         /* Deassert RESET to the external phys */
1350         gpio_set_value(TX6UL_FEC_RST_GPIO, 1);
1351
1352         if (getenv("ethaddr")) {
1353                 ret = fecmxc_initialize_multi(bis, 0, 0, ENET_BASE_ADDR);
1354                 if (ret) {
1355                         printf("failed to initialize FEC0: %d\n", ret);
1356                         return ret;
1357                 }
1358         }
1359         if (getenv("eth1addr")) {
1360                 ret = gpio_request_array(tx6ul_fec2_gpios,
1361                                         ARRAY_SIZE(tx6ul_fec2_gpios));
1362                 if (ret < 0) {
1363                         printf("Failed to request tx6ul_fec2_gpios: %d\n", ret);
1364                 }
1365                 imx_iomux_v3_setup_multiple_pads(tx6ul_enet2_pads,
1366                                                 ARRAY_SIZE(tx6ul_enet2_pads));
1367
1368                 writel(0x00100000, 0x020c80e4); /* assert ENET2_125M_EN */
1369
1370                 /* Minimum PHY reset duration */
1371                 udelay(100);
1372                 gpio_set_value(TX6UL_FEC2_RST_GPIO, 1);
1373                 /* Wait for PHY internal POR to finish */
1374                 udelay(22000);
1375
1376                 ret = fecmxc_initialize_multi(bis, 1, 2, ENET2_BASE_ADDR);
1377                 if (ret) {
1378                         printf("failed to initialize FEC1: %d\n", ret);
1379                         return ret;
1380                 }
1381         }
1382         return 0;
1383 }
1384 #endif /* CONFIG_FEC_MXC */
1385
1386 #ifdef CONFIG_SERIAL_TAG
1387 void get_board_serial(struct tag_serialnr *serialnr)
1388 {
1389         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1390         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1391
1392         serialnr->low = readl(&fuse->cfg0);
1393         serialnr->high = readl(&fuse->cfg1);
1394 }
1395 #endif
1396
1397 #if defined(CONFIG_OF_BOARD_SETUP)
1398 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1399 #include <jffs2/jffs2.h>
1400 #include <mtd_node.h>
1401 static struct node_info nodes[] = {
1402         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1403 };
1404 #else
1405 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1406 #endif
1407
1408 static const char *tx6_touchpanels[] = {
1409         "ti,tsc2007",
1410         "edt,edt-ft5x06",
1411         "eeti,egalax_ts",
1412 };
1413
1414 int ft_board_setup(void *blob, bd_t *bd)
1415 {
1416         const char *baseboard = getenv("baseboard");
1417         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1418         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1419         int ret;
1420
1421         ret = fdt_increase_size(blob, 4096);
1422         if (ret) {
1423                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1424                 return ret;
1425         }
1426         if (stk5_v5)
1427                 karo_fdt_enable_node(blob, "stk5led", 0);
1428
1429         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1430
1431         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1432                                 ARRAY_SIZE(tx6_touchpanels));
1433         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1434         karo_fdt_fixup_flexcan(blob, stk5_v5);
1435
1436         karo_fdt_update_fb_mode(blob, video_mode);
1437
1438         return 0;
1439 }
1440 #endif /* CONFIG_OF_BOARD_SETUP */