2 * Copyright (C) 2015 Lothar Waßmann <LW@KARO-electronics.de>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <fdt_support.h>
14 #include <fsl_esdhc.h>
22 #include <asm/arch/mx6-pins.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/hab.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/crm_regs.h>
27 #include <asm/arch/sys_proto.h>
29 #include "../common/karo.h"
32 #define __data __attribute__((section(".data")))
34 #define TX6UL_FEC_RST_GPIO IMX_GPIO_NR(5, 6)
35 #define TX6UL_FEC_PWR_GPIO IMX_GPIO_NR(5, 7)
36 #define TX6UL_FEC_INT_GPIO IMX_GPIO_NR(5, 5)
38 #define TX6UL_FEC2_RST_GPIO IMX_GPIO_NR(4, 28)
39 #define TX6UL_FEC2_INT_GPIO IMX_GPIO_NR(4, 27)
41 #define TX6UL_LED_GPIO IMX_GPIO_NR(5, 9)
43 #define TX6UL_LCD_PWR_GPIO IMX_GPIO_NR(5, 4)
44 #define TX6UL_LCD_RST_GPIO IMX_GPIO_NR(3, 4)
45 #define TX6UL_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(4, 16)
47 #define TX6UL_I2C1_SCL_GPIO CONFIG_SOFT_I2C_GPIO_SCL
48 #define TX6UL_I2C1_SDA_GPIO CONFIG_SOFT_I2C_GPIO_SDA
50 #define TX6UL_SD1_CD_GPIO IMX_GPIO_NR(4, 14)
52 #ifdef CONFIG_MX6_TEMPERATURE_MIN
53 #define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN
55 #define TEMPERATURE_MIN (-40)
57 #ifdef CONFIG_MX6_TEMPERATURE_HOT
58 #define TEMPERATURE_HOT CONFIG_MX6_TEMPERATURE_HOT
60 #define TEMPERATURE_HOT 80
63 DECLARE_GLOBAL_DATA_PTR;
65 #define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
67 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
68 #ifdef CONFIG_SECURE_BOOT
69 char __csf_data[0] __attribute__((section(".__csf_data")));
72 static const iomux_v3_cfg_t const tx6ul_pads[] = {
74 #if CONFIG_MXC_UART_BASE == UART1_BASE
75 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX,
76 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX,
77 MX6_PAD_UART1_RTS_B__UART1_DCE_RTS,
78 MX6_PAD_UART1_CTS_B__UART1_DCE_CTS,
80 #if CONFIG_MXC_UART_BASE == UART2_BASE
81 MX6_PAD_UART2_TX_DATA__UART2_DCE_TX,
82 MX6_PAD_UART2_RX_DATA__UART2_DCE_RX,
83 MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS,
84 MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS,
86 #if CONFIG_MXC_UART_BASE == UART5_BASE
87 MX6_PAD_GPIO1_IO04__UART5_DCE_TX,
88 MX6_PAD_GPIO1_IO05__UART5_DCE_RX,
89 MX6_PAD_GPIO1_IO08__UART5_DCE_RTS,
90 MX6_PAD_GPIO1_IO09__UART5_DCE_CTS,
93 MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
94 MUX_PAD_CTRL(PAD_CTL_DSE_240ohm), /* I2C SCL */
95 MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
96 MUX_PAD_CTRL(PAD_CTL_DSE_240ohm | PAD_CTL_HYS |
97 PAD_CTL_ODE), /* I2C SDA */
99 /* FEC PHY GPIO functions */
100 MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_CFG_SION, /* PHY POWER */
101 MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | MUX_CFG_SION, /* PHY RESET */
102 MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
103 PAD_CTL_DSE_40ohm), /* PHY INT */
106 #define TX6_ENET_PAD_CTRL (PAD_CTL_SPEED_HIGH | \
107 PAD_CTL_DSE_48ohm | \
108 PAD_CTL_PUS_100K_UP | \
110 #define TX6_GPIO_OUT_PAD_CTRL (PAD_CTL_SPEED_LOW | \
111 PAD_CTL_DSE_60ohm | \
113 #define TX6_GPIO_IN_PAD_CTRL (PAD_CTL_SPEED_LOW | \
116 static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = {
118 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_48ohm |
120 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
123 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_CFG_SION |
124 MUX_PAD_CTRL(PAD_CTL_SPEED_MED |
127 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
128 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
129 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
130 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
131 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
132 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
133 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
136 static const iomux_v3_cfg_t const tx6ul_enet2_pads[] = {
137 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_CFG_SION |
138 MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |
141 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
142 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
143 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
144 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
145 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
146 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
147 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
150 #define TX6_I2C_PAD_CTRL (PAD_CTL_PUS_22K_UP | \
151 PAD_CTL_SPEED_MED | \
152 PAD_CTL_DSE_34ohm | \
155 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
157 MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
158 MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
159 MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
160 MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
163 static const struct gpio const tx6ul_gpios[] = {
164 /* These two entries are used to forcefully reinitialize the I2C bus */
165 { TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
166 { TX6UL_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
168 { TX6UL_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
169 { TX6UL_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
170 { TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
173 static const struct gpio const tx6ul_fec2_gpios[] = {
174 { TX6UL_FEC2_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC2 PHY RESET", },
175 { TX6UL_FEC2_INT_GPIO, GPIOFLAG_INPUT, "FEC2 PHY INT", },
182 /* run with default environment */
183 static void tx6_i2c_recover(void)
187 #define SCL_BIT (1 << (TX6UL_I2C1_SCL_GPIO % 32))
188 #define SDA_BIT (1 << (TX6UL_I2C1_SDA_GPIO % 32))
189 #define I2C_GPIO_BASE (GPIO1_BASE_ADDR + TX6UL_I2C1_SCL_GPIO / 32 * 0x4000)
191 if ((readl(I2C_GPIO_BASE + GPIO_PSR) &
192 (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
195 debug("Clearing I2C bus\n");
196 if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SCL_BIT)) {
197 printf("I2C SCL stuck LOW\n");
200 writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
201 I2C_GPIO_BASE + GPIO_DR);
202 writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
203 I2C_GPIO_BASE + GPIO_DIR);
205 if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)) {
206 printf("I2C SDA stuck LOW\n");
209 writel(readl(I2C_GPIO_BASE + GPIO_DIR) & ~SDA_BIT,
210 I2C_GPIO_BASE + GPIO_DIR);
211 writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
212 I2C_GPIO_BASE + GPIO_DR);
213 writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
214 I2C_GPIO_BASE + GPIO_DIR);
216 imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
217 ARRAY_SIZE(tx6_i2c_gpio_pads));
220 for (i = 0; i < 18; i++) {
221 u32 reg = readl(I2C_GPIO_BASE + GPIO_DR) ^ SCL_BIT;
223 debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
224 writel(reg, I2C_GPIO_BASE + GPIO_DR);
227 readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)
232 u32 reg = readl(I2C_GPIO_BASE + GPIO_PSR);
234 if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
235 printf("I2C bus recovery succeeded\n");
237 printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
243 /* placed in section '.data' to prevent overwriting relocation info
246 static u32 wrsr __data;
248 #define WRSR_POR (1 << 4)
249 #define WRSR_TOUT (1 << 1)
250 #define WRSR_SFTW (1 << 0)
252 static void print_reset_cause(void)
254 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
255 void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
259 printf("Reset cause: ");
261 srsr = readl(&src_regs->srsr);
262 wrsr = readw(wdt_base + 4);
264 if (wrsr & WRSR_POR) {
265 printf("%sPOR", dlm);
268 if (srsr & 0x00004) {
269 printf("%sCSU", dlm);
272 if (srsr & 0x00008) {
273 printf("%sIPP USER", dlm);
276 if (srsr & 0x00010) {
277 if (wrsr & WRSR_SFTW) {
278 printf("%sSOFT", dlm);
281 if (wrsr & WRSR_TOUT) {
282 printf("%sWDOG", dlm);
286 if (srsr & 0x00020) {
287 printf("%sJTAG HIGH-Z", dlm);
290 if (srsr & 0x00040) {
291 printf("%sJTAG SW", dlm);
294 if (srsr & 0x10000) {
295 printf("%sWARM BOOT", dlm);
304 #ifdef CONFIG_IMX6_THERMAL
306 #include <imx_thermal.h>
309 static void print_temperature(void)
311 struct udevice *thermal_dev;
312 int cpu_tmp, minc, maxc, ret;
313 char const *grade_str;
314 static u32 __data thermal_calib;
316 puts("Temperature: ");
317 switch (get_cpu_temp_grade(&minc, &maxc)) {
318 case TEMP_AUTOMOTIVE:
319 grade_str = "Automotive";
321 case TEMP_INDUSTRIAL:
322 grade_str = "Industrial";
324 case TEMP_EXTCOMMERCIAL:
325 grade_str = "Extended Commercial";
328 grade_str = "Commercial";
330 printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
331 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
333 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
336 printf(" at %dC", cpu_tmp);
338 puts(" - failed to read sensor data");
340 puts(" - no sensor device found");
343 if (fuse_read(1, 6, &thermal_calib) == 0) {
344 printf(" - calibration data 0x%08x\n", thermal_calib);
346 puts(" - Failed to read thermal calib fuse\n");
350 static inline void print_temperature(void)
357 u32 cpurev = get_cpu_rev();
360 if (is_cpu_type(MXC_CPU_MX6SL))
362 else if (is_cpu_type(MXC_CPU_MX6DL))
364 else if (is_cpu_type(MXC_CPU_MX6SOLO))
366 else if (is_cpu_type(MXC_CPU_MX6Q))
368 else if (is_cpu_type(MXC_CPU_MX6UL))
371 printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n",
373 (cpurev & 0x000F0) >> 4,
374 (cpurev & 0x0000F) >> 0,
375 mxc_get_clock(MXC_ARM_CLK) / 1000000);
379 #ifdef CONFIG_MX6_TEMPERATURE_HOT
380 check_cpu_temperature(1);
386 /* serial port not initialized at this point */
387 int board_early_init_f(void)
392 #ifndef CONFIG_MX6_TEMPERATURE_HOT
393 static bool tx6_temp_check_enabled = true;
395 #define tx6_temp_check_enabled 0
398 static inline u8 tx6ul_mem_suffix(void)
400 #ifdef CONFIG_TX6_NAND
408 #define VDD_RTC_VAL rn5t_mV_to_regval_rtc(3000)
409 #define VDD_CORE_VAL rn5t_mV_to_regval(1300) /* DCDC1 */
410 #define VDD_CORE_VAL_LP rn5t_mV_to_regval(900)
411 #define VDD_DDR_VAL rn5t_mV_to_regval(1350) /* DCDC3 */
412 #define VDD_DDR_VAL_LP rn5t_mV_to_regval(1350)
413 #define VDD_HIGH_VAL rn5t_mV_to_regval(3300) /* DCDC4 */
414 #define VDD_HIGH_VAL_LP rn5t_mV_to_regval(3300)
415 #define VDD_CSI_VAL rn5t_mV_to_regval2(3300) /* LDO4 */
416 #define VDD_CSI_VAL_LP rn5t_mV_to_regval2(3300)
418 static struct pmic_regs rn5t567_regs[] = {
419 { RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, },
420 { RN5T567_DC2CTL, DC2_DC2DIS, },
421 { RN5T567_DC1DAC, VDD_CORE_VAL, },
422 { RN5T567_DC3DAC, VDD_DDR_VAL, },
423 { RN5T567_DC4DAC, VDD_HIGH_VAL, },
424 { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
425 { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
426 { RN5T567_DC4DAC_SLP, VDD_HIGH_VAL_LP, },
427 { RN5T567_LDOEN1, 0x01f, ~0x1f, },
428 { RN5T567_LDOEN2, 0x10, ~0x30, },
429 { RN5T567_LDODIS, 0x00, },
430 { RN5T567_LDO4DAC, VDD_CSI_VAL, },
431 { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
432 { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
435 static int pmic_addr __maybe_unused = 0x33;
441 debug("%s@%d: \n", __func__, __LINE__);
443 printf("Board: Ka-Ro TXUL-001%c\n",
448 ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios));
450 printf("Failed to request tx6ul_gpios: %d\n", ret);
452 imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads));
454 /* Address of boot parameters */
455 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
456 gd->bd->bi_arch_number = -1;
458 if (ctrlc() || (wrsr & WRSR_TOUT)) {
459 if (wrsr & WRSR_TOUT)
460 printf("WDOG RESET detected; Skipping PMIC setup\n");
462 printf("<CTRL-C> detected; safeboot enabled\n");
463 #ifndef CONFIG_MX6_TEMPERATURE_HOT
464 tx6_temp_check_enabled = false;
469 ret = tx6_pmic_init(pmic_addr, rn5t567_regs, ARRAY_SIZE(rn5t567_regs));
471 printf("Failed to setup PMIC voltages: %d\n", ret);
479 debug("%s@%d: \n", __func__, __LINE__);
481 /* dram_init must store complete ramsize in gd->ram_size */
482 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
483 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
487 void dram_init_banksize(void)
489 debug("%s@%d: \n", __func__, __LINE__);
491 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
492 gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
494 #if CONFIG_NR_DRAM_BANKS > 1
495 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
496 gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
501 #ifdef CONFIG_FSL_ESDHC
502 #define TX6_SD_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
503 PAD_CTL_SPEED_MED | \
504 PAD_CTL_DSE_40ohm | \
507 static const iomux_v3_cfg_t mmc0_pads[] = {
508 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
509 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
510 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
511 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
512 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
513 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
515 MX6_PAD_NAND_CE1_B__GPIO4_IO14 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
518 #ifdef CONFIG_TX6_EMMC
519 static const iomux_v3_cfg_t mmc1_pads[] = {
520 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
521 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
522 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
523 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
524 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
525 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
527 MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
532 static struct tx6_esdhc_cfg {
533 const iomux_v3_cfg_t *pads;
535 enum mxc_clock clkid;
536 struct fsl_esdhc_cfg cfg;
538 } tx6ul_esdhc_cfg[] = {
539 #ifdef CONFIG_TX6_EMMC
542 .num_pads = ARRAY_SIZE(mmc1_pads),
543 .clkid = MXC_ESDHC2_CLK,
545 .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
553 .num_pads = ARRAY_SIZE(mmc0_pads),
554 .clkid = MXC_ESDHC_CLK,
556 .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
559 .cd_gpio = TX6UL_SD1_CD_GPIO,
563 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
565 return container_of(cfg, struct tx6_esdhc_cfg, cfg);
568 int board_mmc_getcd(struct mmc *mmc)
570 struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
572 if (cfg->cd_gpio < 0)
575 debug("SD card %d is %spresent (GPIO %d)\n",
576 cfg - tx6ul_esdhc_cfg,
577 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
579 return !gpio_get_value(cfg->cd_gpio);
582 int board_mmc_init(bd_t *bis)
586 debug("%s@%d: \n", __func__, __LINE__);
588 #ifndef CONFIG_ENV_IS_IN_MMC
589 if (!(gd->flags & GD_FLG_ENV_READY)) {
590 printf("deferred ...");
594 for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) {
596 struct tx6_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
599 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
600 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
602 if (cfg->cd_gpio >= 0) {
603 ret = gpio_request_one(cfg->cd_gpio,
604 GPIOFLAG_INPUT, "MMC CD");
606 printf("Error %d requesting GPIO%d_%d\n",
607 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
612 debug("%s: Initializing MMC slot %d\n", __func__, i);
613 fsl_esdhc_initialize(bis, &cfg->cfg);
615 mmc = find_mmc_device(i);
618 if (board_mmc_getcd(mmc))
623 #endif /* CONFIG_CMD_MMC */
632 static inline int calc_blink_rate(void)
634 if (!tx6_temp_check_enabled)
635 return CONFIG_SYS_HZ;
637 return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
638 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
639 (TEMPERATURE_HOT - TEMPERATURE_MIN);
642 void show_activity(int arg)
644 static int led_state = LED_STATE_INIT;
645 static int blink_rate;
655 ret = gpio_set_value(TX6UL_LED_GPIO, 1);
657 led_state = LED_STATE_ERR;
659 led_state = LED_STATE_ON;
660 blink_rate = calc_blink_rate();
665 if (get_timer(last) > blink_rate) {
666 blink_rate = calc_blink_rate();
667 last = get_timer_masked();
668 if (led_state == LED_STATE_ON) {
669 gpio_set_value(TX6UL_LED_GPIO, 0);
671 gpio_set_value(TX6UL_LED_GPIO, 1);
673 led_state = 1 - led_state;
679 static const iomux_v3_cfg_t stk5_pads[] = {
680 /* SW controlled LED on STK5 baseboard */
681 MX6_PAD_SNVS_TAMPER9__GPIO5_IO09,
683 /* I2C bus on DIMM pins 40/41 */
684 MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
685 MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
687 /* TSC200x PEN IRQ */
688 MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL),
690 /* EDT-FT5x06 Polytouch panel */
691 MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* IRQ */
692 MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* RESET */
693 MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* WAKE */
696 MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
697 MX6_PAD_GPIO1_IO03__USB_OTG2_OC | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
700 MX6_PAD_UART3_CTS_B__GPIO1_IO26 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
701 MX6_PAD_UART3_RTS_B__GPIO1_IO27 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
704 static const struct gpio stk5_gpios[] = {
705 { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
707 { IMX_GPIO_NR(1, 27), GPIOFLAG_INPUT, "USBOTG OC", },
708 { IMX_GPIO_NR(1, 26), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
712 vidinfo_t panel_info = {
713 /* set to max. size supported by SoC */
717 .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
720 static struct fb_videomode tx6_fb_modes[] = {
721 #ifndef CONFIG_SYS_LVDS_IF
723 /* Standard VGA timing */
728 .pixclock = KHZ2PICOS(25175),
735 .sync = FB_SYNC_CLK_LAT_FALL,
738 /* Emerging ETV570 640 x 480 display. Syncs low active,
739 * DE high active, 115.2 mm x 86.4 mm display area
740 * VGA compatible timing
746 .pixclock = KHZ2PICOS(25175),
753 .sync = FB_SYNC_CLK_LAT_FALL,
756 /* Emerging ET0350G0DH6 320 x 240 display.
757 * 70.08 mm x 52.56 mm display area.
763 .pixclock = KHZ2PICOS(6500),
764 .left_margin = 68 - 34,
767 .upper_margin = 18 - 3,
770 .sync = FB_SYNC_CLK_LAT_FALL,
773 /* Emerging ET0430G0DH6 480 x 272 display.
774 * 95.04 mm x 53.856 mm display area.
780 .pixclock = KHZ2PICOS(9000),
789 /* Emerging ET0500G0DH6 800 x 480 display.
790 * 109.6 mm x 66.4 mm display area.
796 .pixclock = KHZ2PICOS(33260),
797 .left_margin = 216 - 128,
799 .right_margin = 1056 - 800 - 216,
800 .upper_margin = 35 - 2,
802 .lower_margin = 525 - 480 - 35,
803 .sync = FB_SYNC_CLK_LAT_FALL,
806 /* Emerging ETQ570G0DH6 320 x 240 display.
807 * 115.2 mm x 86.4 mm display area.
813 .pixclock = KHZ2PICOS(6400),
817 .upper_margin = 16, /* 15 according to datasheet */
818 .vsync_len = 3, /* TVP -> 1>x>5 */
819 .lower_margin = 4, /* 4.5 according to datasheet */
820 .sync = FB_SYNC_CLK_LAT_FALL,
823 /* Emerging ET0700G0DH6 800 x 480 display.
824 * 152.4 mm x 91.44 mm display area.
830 .pixclock = KHZ2PICOS(33260),
831 .left_margin = 216 - 128,
833 .right_margin = 1056 - 800 - 216,
834 .upper_margin = 35 - 2,
836 .lower_margin = 525 - 480 - 35,
837 .sync = FB_SYNC_CLK_LAT_FALL,
840 /* Emerging ET070001DM6 800 x 480 display.
841 * 152.4 mm x 91.44 mm display area.
843 .name = "ET070001DM6",
847 .pixclock = KHZ2PICOS(33260),
848 .left_margin = 216 - 128,
850 .right_margin = 1056 - 800 - 216,
851 .upper_margin = 35 - 2,
853 .lower_margin = 525 - 480 - 35,
858 /* HannStar HSD100PXN1
859 * 202.7m mm x 152.06 mm display area.
861 .name = "HSD100PXN1",
865 .pixclock = KHZ2PICOS(65000),
872 .sync = FB_SYNC_CLK_LAT_FALL,
876 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
884 .sync = FB_SYNC_CLK_LAT_FALL,
888 static int lcd_enabled = 1;
889 static int lcd_bl_polarity;
891 static int lcd_backlight_polarity(void)
893 return lcd_bl_polarity;
896 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
899 MX6_PAD_LCD_RESET__GPIO3_IO04 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
900 /* LCD POWER_ENABLE */
901 MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
902 /* LCD Backlight (PWM) */
903 MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
905 MX6_PAD_LCD_DATA00__LCDIF_DATA00,
906 MX6_PAD_LCD_DATA01__LCDIF_DATA01,
907 MX6_PAD_LCD_DATA02__LCDIF_DATA02,
908 MX6_PAD_LCD_DATA03__LCDIF_DATA03,
909 MX6_PAD_LCD_DATA04__LCDIF_DATA04,
910 MX6_PAD_LCD_DATA05__LCDIF_DATA05,
911 MX6_PAD_LCD_DATA06__LCDIF_DATA06,
912 MX6_PAD_LCD_DATA07__LCDIF_DATA07,
913 MX6_PAD_LCD_DATA08__LCDIF_DATA08,
914 MX6_PAD_LCD_DATA09__LCDIF_DATA09,
915 MX6_PAD_LCD_DATA10__LCDIF_DATA10,
916 MX6_PAD_LCD_DATA11__LCDIF_DATA11,
917 MX6_PAD_LCD_DATA12__LCDIF_DATA12,
918 MX6_PAD_LCD_DATA13__LCDIF_DATA13,
919 MX6_PAD_LCD_DATA14__LCDIF_DATA14,
920 MX6_PAD_LCD_DATA15__LCDIF_DATA15,
921 MX6_PAD_LCD_DATA16__LCDIF_DATA16,
922 MX6_PAD_LCD_DATA17__LCDIF_DATA17,
923 MX6_PAD_LCD_DATA18__LCDIF_DATA18,
924 MX6_PAD_LCD_DATA19__LCDIF_DATA19,
925 MX6_PAD_LCD_DATA20__LCDIF_DATA20,
926 MX6_PAD_LCD_DATA21__LCDIF_DATA21,
927 MX6_PAD_LCD_DATA22__LCDIF_DATA22,
928 MX6_PAD_LCD_DATA23__LCDIF_DATA23,
929 MX6_PAD_LCD_HSYNC__LCDIF_HSYNC, /* HSYNC */
930 MX6_PAD_LCD_VSYNC__LCDIF_VSYNC, /* VSYNC */
931 MX6_PAD_LCD_ENABLE__LCDIF_ENABLE, /* OE_ACD */
932 MX6_PAD_LCD_CLK__LCDIF_CLK, /* LSCLK */
936 static const struct gpio stk5_lcd_gpios[] = {
937 { TX6UL_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
938 { TX6UL_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
939 { TX6UL_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
942 /* run with valid env from NAND/eMMC */
943 void lcd_enable(void)
946 * global variable from common/lcd.c
947 * Set to 0 here to prevent messages from going to LCD
948 * rather than serial console
953 karo_load_splashimage(1);
955 debug("Switching LCD on\n");
956 gpio_set_value(TX6UL_LCD_PWR_GPIO, 1);
958 gpio_set_value(TX6UL_LCD_RST_GPIO, 1);
960 gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
961 lcd_backlight_polarity());
965 static void lcd_disable(void)
968 printf("Disabling LCD\n");
969 panel_info.vl_row = 0;
974 void lcd_ctrl_init(void *lcdbase)
976 int color_depth = 24;
977 const char *video_mode = karo_get_vmode(getenv("video_mode"));
981 struct fb_videomode *p = &tx6_fb_modes[0];
982 struct fb_videomode fb_mode;
983 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
986 debug("LCD disabled\n");
990 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
992 setenv("splashimage", NULL);
997 lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
999 if (video_mode == NULL) {
1004 if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1006 debug("Using video mode from FDT\n");
1008 if (fb_mode.xres > panel_info.vl_col ||
1009 fb_mode.yres > panel_info.vl_row) {
1010 printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1011 fb_mode.xres, fb_mode.yres,
1012 panel_info.vl_col, panel_info.vl_row);
1017 if (p->name != NULL)
1018 debug("Trying compiled-in video modes\n");
1019 while (p->name != NULL) {
1020 if (strcmp(p->name, vm) == 0) {
1021 debug("Using video mode: '%s'\n", p->name);
1028 debug("Trying to decode video_mode: '%s'\n", vm);
1029 while (*vm != '\0') {
1030 if (*vm >= '0' && *vm <= '9') {
1033 val = simple_strtoul(vm, &end, 0);
1036 if (val > panel_info.vl_col)
1037 val = panel_info.vl_col;
1039 panel_info.vl_col = val;
1041 } else if (!yres_set) {
1042 if (val > panel_info.vl_row)
1043 val = panel_info.vl_row;
1045 panel_info.vl_row = val;
1047 } else if (!bpp_set) {
1058 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1059 end - vm, vm, color_depth);
1062 } else if (!refresh_set) {
1089 if (p->xres == 0 || p->yres == 0) {
1090 printf("Invalid video mode: %s\n", getenv("video_mode"));
1092 printf("Supported video modes are:");
1093 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1094 printf(" %s", p->name);
1099 if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1100 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1101 p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1105 panel_info.vl_col = p->xres;
1106 panel_info.vl_row = p->yres;
1108 switch (color_depth) {
1110 panel_info.vl_bpix = LCD_COLOR8;
1113 panel_info.vl_bpix = LCD_COLOR16;
1116 panel_info.vl_bpix = LCD_COLOR32;
1119 p->pixclock = KHZ2PICOS(refresh *
1120 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1121 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1123 debug("Pixel clock set to %lu.%03lu MHz\n",
1124 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1126 if (p != &fb_mode) {
1129 debug("Creating new display-timing node from '%s'\n",
1131 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1133 printf("Failed to create new display-timing node from '%s': %d\n",
1137 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1138 imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1139 ARRAY_SIZE(stk5_lcd_pads));
1141 debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
1142 color_depth, refresh);
1144 if (karo_load_splashimage(0) == 0) {
1147 /* setup env variable for mxsfb display driver */
1148 snprintf(vmode, sizeof(vmode),
1149 "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
1150 p->xres, p->yres, p->left_margin, p->right_margin,
1151 p->upper_margin, p->lower_margin, p->hsync_len,
1152 p->vsync_len, p->sync, p->pixclock, color_depth);
1153 setenv("videomode", vmode);
1155 debug("Initializing LCD controller\n");
1158 setenv("videomode", NULL);
1160 debug("Skipping initialization of LCD controller\n");
1164 #define lcd_enabled 0
1165 #endif /* CONFIG_LCD */
1167 #ifndef CONFIG_ENV_IS_IN_MMC
1168 static void tx6_mmc_init(void)
1171 if (board_mmc_init(gd->bd) < 0)
1172 cpu_mmc_init(gd->bd);
1173 print_mmc_devices(',');
1176 static inline void tx6_mmc_init(void)
1181 static void stk5_board_init(void)
1185 ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1187 printf("Failed to request stk5_gpios: %d\n", ret);
1190 imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1191 debug("%s@%d: \n", __func__, __LINE__);
1194 static void stk5v3_board_init(void)
1196 debug("%s@%d: \n", __func__, __LINE__);
1198 debug("%s@%d: \n", __func__, __LINE__);
1202 static void stk5v5_board_init(void)
1209 ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
1210 "Flexcan Transceiver");
1212 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1216 imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 |
1217 MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL));
1220 static void tx6ul_set_cpu_clock(void)
1222 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1224 if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1227 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1228 printf("%s detected; skipping cpu clock change\n",
1229 (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1232 if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1233 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1234 printf("CPU clock set to %lu.%03lu MHz\n",
1235 cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1237 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1241 int board_late_init(void)
1243 const char *baseboard;
1245 debug("%s@%d: \n", __func__, __LINE__);
1249 if (tx6_temp_check_enabled)
1250 check_cpu_temperature(1);
1252 tx6ul_set_cpu_clock();
1255 setenv_ulong("safeboot", 1);
1256 else if (wrsr & WRSR_TOUT)
1257 setenv_ulong("wdreset", 1);
1259 karo_fdt_move_fdt();
1261 baseboard = getenv("baseboard");
1265 printf("Baseboard: %s\n", baseboard);
1267 if (strncmp(baseboard, "stk5", 4) == 0) {
1268 if ((strlen(baseboard) == 4) ||
1269 strcmp(baseboard, "stk5-v3") == 0) {
1270 stk5v3_board_init();
1271 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1272 const char *otg_mode = getenv("otg_mode");
1274 if (otg_mode && strcmp(otg_mode, "host") == 0) {
1275 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1276 otg_mode, baseboard);
1277 setenv("otg_mode", "none");
1279 stk5v5_board_init();
1281 printf("WARNING: Unsupported STK5 board rev.: %s\n",
1284 } else if (strncmp(baseboard, "ulmb-", 5) == 0) {
1285 const char *otg_mode = getenv("otg_mode");
1287 if (otg_mode && strcmp(otg_mode, "host") == 0) {
1288 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1289 otg_mode, baseboard);
1290 setenv("otg_mode", "none");
1294 printf("WARNING: Unsupported baseboard: '%s'\n",
1301 debug("%s@%d: \n", __func__, __LINE__);
1307 #ifdef CONFIG_FEC_MXC
1313 static void tx6_init_mac(void)
1316 const char *baseboard = getenv("baseboard");
1318 imx_get_mac_from_fuse(0, mac);
1319 if (!is_valid_ethaddr(mac)) {
1320 printf("No valid MAC address programmed\n");
1323 printf("MAC addr from fuse: %pM\n", mac);
1324 if (!getenv("ethaddr"))
1325 eth_setenv_enetaddr("ethaddr", mac);
1327 if (!baseboard || strncmp(baseboard, "stk5", 4) == 0) {
1328 setenv("eth1addr", NULL);
1331 if (getenv("eth1addr"))
1333 imx_get_mac_from_fuse(1, mac);
1334 eth_setenv_enetaddr("eth1addr", mac);
1337 int board_eth_init(bd_t *bis)
1343 /* delay at least 21ms for the PHY internal POR signal to deassert */
1346 imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads,
1347 ARRAY_SIZE(tx6ul_enet1_pads));
1349 /* Deassert RESET to the external phys */
1350 gpio_set_value(TX6UL_FEC_RST_GPIO, 1);
1352 if (getenv("ethaddr")) {
1353 ret = fecmxc_initialize_multi(bis, 0, 0, ENET_BASE_ADDR);
1355 printf("failed to initialize FEC0: %d\n", ret);
1359 if (getenv("eth1addr")) {
1360 ret = gpio_request_array(tx6ul_fec2_gpios,
1361 ARRAY_SIZE(tx6ul_fec2_gpios));
1363 printf("Failed to request tx6ul_fec2_gpios: %d\n", ret);
1365 imx_iomux_v3_setup_multiple_pads(tx6ul_enet2_pads,
1366 ARRAY_SIZE(tx6ul_enet2_pads));
1368 writel(0x00100000, 0x020c80e4); /* assert ENET2_125M_EN */
1370 /* Minimum PHY reset duration */
1372 gpio_set_value(TX6UL_FEC2_RST_GPIO, 1);
1373 /* Wait for PHY internal POR to finish */
1376 ret = fecmxc_initialize_multi(bis, 1, 2, ENET2_BASE_ADDR);
1378 printf("failed to initialize FEC1: %d\n", ret);
1384 #endif /* CONFIG_FEC_MXC */
1386 #ifdef CONFIG_SERIAL_TAG
1387 void get_board_serial(struct tag_serialnr *serialnr)
1389 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1390 struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1392 serialnr->low = readl(&fuse->cfg0);
1393 serialnr->high = readl(&fuse->cfg1);
1397 #if defined(CONFIG_OF_BOARD_SETUP)
1398 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1399 #include <jffs2/jffs2.h>
1400 #include <mtd_node.h>
1401 static struct node_info nodes[] = {
1402 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1405 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1408 static const char *tx6_touchpanels[] = {
1414 int ft_board_setup(void *blob, bd_t *bd)
1416 const char *baseboard = getenv("baseboard");
1417 int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1418 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1421 ret = fdt_increase_size(blob, 4096);
1423 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1427 karo_fdt_enable_node(blob, "stk5led", 0);
1429 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1431 karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1432 ARRAY_SIZE(tx6_touchpanels));
1433 karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1434 karo_fdt_fixup_flexcan(blob, stk5_v5);
1436 karo_fdt_update_fb_mode(blob, video_mode);
1440 #endif /* CONFIG_OF_BOARD_SETUP */