board/karo/tx6/tx6ul.c

   1 /*
   2  * Copyright (C) 2015 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  *
   6  */
   7 #include <common.h>
   8 #include <errno.h>
   9 #include <libfdt.h>
  10 #include <fdt_support.h>
  11 #include <lcd.h>
  12 #include <netdev.h>
  13 #include <mmc.h>
  14 #include <fsl_esdhc.h>
  15 #include <video_fb.h>
  16 #include <ipu.h>
  17 #include <mxcfb.h>
  18 #include <i2c.h>
  19 #include <linux/fb.h>
  20 #include <asm/io.h>
  21 #include <asm/gpio.h>
  22 #include <asm/arch/mx6-pins.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/hab.h>
  25 #include <asm/arch/imx-regs.h>
  26 #include <asm/arch/crm_regs.h>
  27 #include <asm/arch/sys_proto.h>
  28
  29 #include "../common/karo.h"
  30 #include "pmic.h"
  31
  32 #define __data __attribute__((section(".data")))
  33
  34 #define TX6UL_FEC_RST_GPIO              IMX_GPIO_NR(5, 6)
  35 #define TX6UL_FEC_PWR_GPIO              IMX_GPIO_NR(5, 7)
  36 #define TX6UL_FEC_INT_GPIO              IMX_GPIO_NR(5, 5)
  37
  38 #define TX6UL_FEC2_RST_GPIO             IMX_GPIO_NR(4, 28)
  39 #define TX6UL_FEC2_INT_GPIO             IMX_GPIO_NR(4, 27)
  40
  41 #define TX6UL_LED_GPIO                  IMX_GPIO_NR(5, 9)
  42
  43 #define TX6UL_LCD_PWR_GPIO              IMX_GPIO_NR(5, 4)
  44 #define TX6UL_LCD_RST_GPIO              IMX_GPIO_NR(3, 4)
  45 #define TX6UL_LCD_BACKLIGHT_GPIO        IMX_GPIO_NR(4, 16)
  46
  47 #ifdef CONFIG_SYS_I2C_SOFT
  48 #define TX6UL_I2C1_SCL_GPIO             CONFIG_SOFT_I2C_GPIO_SCL
  49 #define TX6UL_I2C1_SDA_GPIO             CONFIG_SOFT_I2C_GPIO_SDA
  50 #endif
  51
  52 #define TX6UL_SD1_CD_GPIO               IMX_GPIO_NR(4, 14)
  53
  54 #ifdef CONFIG_MX6_TEMPERATURE_MIN
  55 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
  56 #else
  57 #define TEMPERATURE_MIN                 (-40)
  58 #endif
  59 #ifdef CONFIG_MX6_TEMPERATURE_HOT
  60 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
  61 #else
  62 #define TEMPERATURE_HOT                 80
  63 #endif
  64
  65 DECLARE_GLOBAL_DATA_PTR;
  66
  67 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  68
  69 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
  70 #ifdef CONFIG_SECURE_BOOT
  71 char __csf_data[0] __attribute__((section(".__csf_data")));
  72 #endif
  73
  74 #define TX6UL_DEFAULT_PAD_CTRL  MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |      \
  75                                         PAD_CTL_SPEED_MED |             \
  76                                         PAD_CTL_DSE_40ohm |             \
  77                                         PAD_CTL_SRE_FAST)
  78 #define TX6UL_I2C_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |       \
  79                                         PAD_CTL_ODE |                   \
  80                                         PAD_CTL_HYS |                   \
  81                                         PAD_CTL_SPEED_LOW |             \
  82                                         PAD_CTL_DSE_34ohm |             \
  83                                         PAD_CTL_SRE_FAST)
  84 #define TX6UL_ENET_PAD_CTRL     MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |       \
  85                                         PAD_CTL_DSE_120ohm |            \
  86                                         PAD_CTL_PUS_100K_UP |           \
  87                                         PAD_CTL_SRE_FAST)
  88 #define TX6UL_GPIO_OUT_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |        \
  89                                         PAD_CTL_DSE_60ohm |             \
  90                                         PAD_CTL_SRE_SLOW)
  91 #define TX6UL_GPIO_IN_PAD_CTRL  MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |        \
  92                                         PAD_CTL_PUS_47K_UP)
  93
  94
  95 static const iomux_v3_cfg_t const tx6ul_pads[] = {
  96         /* UART pads */
  97 #if CONFIG_MXC_UART_BASE == UART1_BASE
  98         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
  99         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
 100         MX6_PAD_UART1_RTS_B__UART1_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
 101         MX6_PAD_UART1_CTS_B__UART1_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
 102 #endif
 103 #if CONFIG_MXC_UART_BASE == UART2_BASE
 104         MX6_PAD_UART2_TX_DATA__UART2_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
 105         MX6_PAD_UART2_RX_DATA__UART2_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
 106         MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
 107         MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
 108 #endif
 109 #if CONFIG_MXC_UART_BASE == UART5_BASE
 110         MX6_PAD_GPIO1_IO04__UART5_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
 111         MX6_PAD_GPIO1_IO05__UART5_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
 112         MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
 113         MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
 114 #endif
 115         /* FEC PHY GPIO functions */
 116         MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY POWER */
 117         MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY RESET */
 118         MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | TX6UL_GPIO_IN_PAD_CTRL, /* PHY INT */
 119 };
 120
 121 static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = {
 122         /* FEC functions */
 123         MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm |
 124                                                      PAD_CTL_SPEED_LOW),
 125         MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
 126                                                       PAD_CTL_DSE_120ohm |
 127                                                       PAD_CTL_SPEED_LOW),
 128         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |
 129                                                      PAD_CTL_DSE_80ohm |
 130                                                      PAD_CTL_SRE_SLOW),
 131
 132         MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | TX6UL_ENET_PAD_CTRL,
 133         MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | TX6UL_ENET_PAD_CTRL,
 134         MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | TX6UL_ENET_PAD_CTRL,
 135         MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | TX6UL_ENET_PAD_CTRL,
 136         MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | TX6UL_ENET_PAD_CTRL,
 137         MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | TX6UL_ENET_PAD_CTRL,
 138         MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | TX6UL_ENET_PAD_CTRL,
 139 };
 140
 141 static const iomux_v3_cfg_t const tx6ul_enet2_pads[] = {
 142         MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |
 143                                                             PAD_CTL_DSE_80ohm |
 144                                                             PAD_CTL_SRE_SLOW),
 145         MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | TX6UL_ENET_PAD_CTRL,
 146         MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | TX6UL_ENET_PAD_CTRL,
 147         MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | TX6UL_ENET_PAD_CTRL,
 148         MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | TX6UL_ENET_PAD_CTRL,
 149         MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | TX6UL_ENET_PAD_CTRL,
 150         MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | TX6UL_ENET_PAD_CTRL,
 151         MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | TX6UL_ENET_PAD_CTRL,
 152 };
 153
 154 static const iomux_v3_cfg_t const tx6ul_i2c_pads[] = {
 155         /* internal I2C */
 156         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
 157                         TX6UL_I2C_PAD_CTRL, /* I2C SCL */
 158         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
 159                         TX6UL_I2C_PAD_CTRL, /* I2C SDA */
 160 };
 161
 162 static const struct gpio const tx6ul_gpios[] = {
 163 #ifdef CONFIG_SYS_I2C_SOFT
 164         /* These two entries are used to forcefully reinitialize the I2C bus */
 165         { TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
 166         { TX6UL_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
 167 #endif
 168         { TX6UL_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 169         { TX6UL_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 170         { TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
 171 };
 172
 173 static const struct gpio const tx6ul_fec2_gpios[] = {
 174         { TX6UL_FEC2_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC2 PHY RESET", },
 175         { TX6UL_FEC2_INT_GPIO, GPIOFLAG_INPUT, "FEC2 PHY INT", },
 176 };
 177
 178 #define GPIO_DR 0
 179 #define GPIO_DIR 4
 180 #define GPIO_PSR 8
 181
 182 /* run with default environment */
 183 #if defined(TX6UL_I2C1_SCL_GPIO) && defined(TX6UL_I2C1_SDA_GPIO)
 184 #define SCL_BANK        (TX6UL_I2C1_SCL_GPIO / 32)
 185 #define SDA_BANK        (TX6UL_I2C1_SDA_GPIO / 32)
 186 #define SCL_BIT         (1 << (TX6UL_I2C1_SCL_GPIO % 32))
 187 #define SDA_BIT         (1 << (TX6UL_I2C1_SDA_GPIO % 32))
 188
 189 static void * const gpio_ports[] = {
 190         (void *)GPIO1_BASE_ADDR,
 191         (void *)GPIO2_BASE_ADDR,
 192         (void *)GPIO3_BASE_ADDR,
 193         (void *)GPIO4_BASE_ADDR,
 194         (void *)GPIO5_BASE_ADDR,
 195 };
 196
 197 static void tx6ul_i2c_recover(void)
 198 {
 199         int i;
 200         int bad = 0;
 201         struct gpio_regs *scl_regs = gpio_ports[SCL_BANK];
 202         struct gpio_regs *sda_regs = gpio_ports[SDA_BANK];
 203
 204         if ((readl(&scl_regs->gpio_psr) & SCL_BIT) &&
 205             (readl(&sda_regs->gpio_psr) & SDA_BIT))
 206                 return;
 207
 208         debug("Clearing I2C bus\n");
 209         if (!(readl(&scl_regs->gpio_psr) & SCL_BIT)) {
 210                 printf("I2C SCL stuck LOW\n");
 211                 bad++;
 212
 213                 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
 214                 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
 215
 216                 imx_iomux_v3_setup_pad(MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 |
 217                                        MUX_CFG_SION | TX6UL_GPIO_OUT_PAD_CTRL);
 218         }
 219         if (!(readl(&sda_regs->gpio_psr) & SDA_BIT)) {
 220                 printf("I2C SDA stuck LOW\n");
 221                 bad++;
 222
 223                 clrbits_le32(&sda_regs->gpio_dir, SDA_BIT);
 224                 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
 225                 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
 226
 227                 udelay(5);
 228
 229                 for (i = 0; i < 18; i++) {
 230                         u32 reg = readl(&scl_regs->gpio_dr) ^ SCL_BIT;
 231
 232                         debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
 233                         writel(reg, &scl_regs->gpio_dr);
 234                         udelay(5);
 235                         if (reg & SCL_BIT) {
 236                                 if (readl(&sda_regs->gpio_psr) & SDA_BIT)
 237                                         break;
 238                                 if (!(readl(&scl_regs->gpio_psr) & SCL_BIT))
 239                                         break;
 240                                 break;
 241                         }
 242                 }
 243         }
 244         if (bad) {
 245                 bool scl = !!(readl(&scl_regs->gpio_psr) & SCL_BIT);
 246                 bool sda = !!(readl(&sda_regs->gpio_psr) & SDA_BIT);
 247
 248                 if (scl && sda) {
 249                         printf("I2C bus recovery succeeded\n");
 250                 } else {
 251                         printf("I2C bus recovery FAILED: SCL: %d SDA: %d\n",
 252                                scl, sda);
 253                 }
 254                 imx_iomux_v3_setup_multiple_pads(tx6ul_i2c_pads,
 255                                                  ARRAY_SIZE(tx6ul_i2c_pads));
 256         }
 257 }
 258 #else
 259 static inline void tx6ul_i2c_recover(void)
 260 {
 261 }
 262 #endif
 263
 264 /* placed in section '.data' to prevent overwriting relocation info
 265  * overlayed with bss
 266  */
 267 static u32 wrsr __data;
 268
 269 #define WRSR_POR                        (1 << 4)
 270 #define WRSR_TOUT                       (1 << 1)
 271 #define WRSR_SFTW                       (1 << 0)
 272
 273 static void print_reset_cause(void)
 274 {
 275         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 276         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 277         u32 srsr;
 278         char *dlm = "";
 279
 280         printf("Reset cause: ");
 281
 282         srsr = readl(&src_regs->srsr);
 283         wrsr = readw(wdt_base + 4);
 284
 285         if (wrsr & WRSR_POR) {
 286                 printf("%sPOR", dlm);
 287                 dlm = " | ";
 288         }
 289         if (srsr & 0x00004) {
 290                 printf("%sCSU", dlm);
 291                 dlm = " | ";
 292         }
 293         if (srsr & 0x00008) {
 294                 printf("%sIPP USER", dlm);
 295                 dlm = " | ";
 296         }
 297         if (srsr & 0x00010) {
 298                 if (wrsr & WRSR_SFTW) {
 299                         printf("%sSOFT", dlm);
 300                         dlm = " | ";
 301                 }
 302                 if (wrsr & WRSR_TOUT) {
 303                         printf("%sWDOG", dlm);
 304                         dlm = " | ";
 305                 }
 306         }
 307         if (srsr & 0x00020) {
 308                 printf("%sJTAG HIGH-Z", dlm);
 309                 dlm = " | ";
 310         }
 311         if (srsr & 0x00040) {
 312                 printf("%sJTAG SW", dlm);
 313                 dlm = " | ";
 314         }
 315         if (srsr & 0x10000) {
 316                 printf("%sWARM BOOT", dlm);
 317                 dlm = " | ";
 318         }
 319         if (dlm[0] == '\0')
 320                 printf("unknown");
 321
 322         printf("\n");
 323 }
 324
 325 #ifdef CONFIG_IMX6_THERMAL
 326 #include <thermal.h>
 327 #include <imx_thermal.h>
 328 #include <fuse.h>
 329
 330 static void print_temperature(void)
 331 {
 332         struct udevice *thermal_dev;
 333         int cpu_tmp, minc, maxc, ret;
 334         char const *grade_str;
 335         static u32 __data thermal_calib;
 336
 337         puts("Temperature: ");
 338         switch (get_cpu_temp_grade(&minc, &maxc)) {
 339         case TEMP_AUTOMOTIVE:
 340                 grade_str = "Automotive";
 341                 break;
 342         case TEMP_INDUSTRIAL:
 343                 grade_str = "Industrial";
 344                 break;
 345         case TEMP_EXTCOMMERCIAL:
 346                 grade_str = "Extended Commercial";
 347                 break;
 348         default:
 349                 grade_str = "Commercial";
 350         }
 351         printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
 352         ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
 353         if (ret == 0) {
 354                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
 355
 356                 if (ret == 0)
 357                         printf(" at %dC", cpu_tmp);
 358                 else
 359                         puts(" - failed to read sensor data");
 360         } else {
 361                 puts(" - no sensor device found");
 362         }
 363
 364         if (fuse_read(1, 6, &thermal_calib) == 0) {
 365                 printf(" - calibration data 0x%08x\n", thermal_calib);
 366         } else {
 367                 puts(" - Failed to read thermal calib fuse\n");
 368         }
 369 }
 370 #else
 371 static inline void print_temperature(void)
 372 {
 373 }
 374 #endif
 375
 376 int checkboard(void)
 377 {
 378         u32 cpurev = get_cpu_rev();
 379         char *cpu_str = "?";
 380
 381         if (is_cpu_type(MXC_CPU_MX6SL))
 382                 cpu_str = "SL";
 383         else if (is_cpu_type(MXC_CPU_MX6DL))
 384                 cpu_str = "DL";
 385         else if (is_cpu_type(MXC_CPU_MX6SOLO))
 386                 cpu_str = "SOLO";
 387         else if (is_cpu_type(MXC_CPU_MX6Q))
 388                 cpu_str = "Q";
 389         else if (is_cpu_type(MXC_CPU_MX6UL))
 390                 cpu_str = "UL";
 391         else if (is_cpu_type(MXC_CPU_MX6ULL))
 392                 cpu_str = "ULL";
 393
 394         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
 395                 cpu_str,
 396                 (cpurev & 0x000F0) >> 4,
 397                 (cpurev & 0x0000F) >> 0,
 398                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 399
 400         print_temperature();
 401         print_reset_cause();
 402 #ifdef CONFIG_MX6_TEMPERATURE_HOT
 403         check_cpu_temperature(1);
 404 #endif
 405         tx6ul_i2c_recover();
 406         return 0;
 407 }
 408
 409 /* serial port not initialized at this point */
 410 int board_early_init_f(void)
 411 {
 412         return 0;
 413 }
 414
 415 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 416 static bool tx6ul_temp_check_enabled = true;
 417 #else
 418 #define tx6ul_temp_check_enabled        0
 419 #endif
 420
 421 static inline u8 tx6ul_mem_suffix(void)
 422 {
 423         return '0' + CONFIG_SYS_SDRAM_CHIP_SIZE / 1024 * 2 +
 424                 IS_ENABLED(CONFIG_TX6_EMMC);
 425 }
 426
 427 #ifdef CONFIG_RN5T567
 428 /* PMIC settings */
 429 #define VDD_RTC_VAL             rn5t_mV_to_regval_rtc(3000)
 430 #define VDD_CORE_VAL            rn5t_mV_to_regval(1300)         /* DCDC1 */
 431 #define VDD_CORE_VAL_LP         rn5t_mV_to_regval(900)
 432 #define VDD_DDR_VAL             rn5t_mV_to_regval(1350)         /* DCDC3 SDRAM 1.35V */
 433 #define VDD_DDR_VAL_LP          rn5t_mV_to_regval(1350)
 434 #define VDD_IO_EXT_VAL          rn5t_mV_to_regval(3300)         /* DCDC4 eMMC/NAND,VDDIO_EXT 3.0V */
 435 #define VDD_IO_EXT_VAL_LP       rn5t_mV_to_regval(3300)
 436 #define VDD_IO_INT_VAL          rn5t_mV_to_regval2(3300)        /* LDO1 ENET,GPIO,LCD,SD1,UART,3.3V */
 437 #define VDD_IO_INT_VAL_LP       rn5t_mV_to_regval2(3300)
 438 #define VDD_ADC_VAL             rn5t_mV_to_regval2(3300)        /* LDO2 ADC */
 439 #define VDD_ADC_VAL_LP          rn5t_mV_to_regval2(3300)
 440 #define VDD_PMIC_VAL            rn5t_mV_to_regval2(2500)        /* LDO3 PMIC */
 441 #define VDD_PMIC_VAL_LP         rn5t_mV_to_regval2(2500)
 442 #define VDD_CSI_VAL             rn5t_mV_to_regval2(3300)        /* LDO4 CSI */
 443 #define VDD_CSI_VAL_LP          rn5t_mV_to_regval2(3300)
 444 #define VDD_LDO5_VAL            rn5t_mV_to_regval2(1200)        /* LDO5 1.2V */
 445 #define LDOEN1_LDO1EN           (1 << 0)
 446 #define LDOEN1_LDO2EN           (1 << 1)
 447 #define LDOEN1_LDO3EN           (1 << 2)
 448 #define LDOEN1_LDO4EN           (1 << 3)
 449 #define LDOEN1_LDO5EN           (1 << 4)
 450 #define LDOEN1_VAL              (LDOEN1_LDO1EN | LDOEN1_LDO2EN | LDOEN1_LDO3EN | LDOEN1_LDO4EN)
 451 #define LDOEN1_MASK             0x1f
 452 #define LDOEN2_LDORTC1EN        (1 << 4)
 453 #define LDOEN2_LDORTC2EN        (1 << 5)
 454 #define LDOEN2_VAL              LDOEN2_LDORTC1EN
 455 #define LDOEN2_MASK             0x30
 456
 457 static struct pmic_regs rn5t567_regs[] = {
 458         { RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, },
 459         { RN5T567_SLPCNT, 0, },
 460         { RN5T567_REPCNT, (3 << 4) | (0 << 1), },
 461         { RN5T567_DC1DAC, VDD_CORE_VAL, },
 462         { RN5T567_DC3DAC, VDD_DDR_VAL, },
 463         { RN5T567_DC4DAC, VDD_IO_EXT_VAL, },
 464         { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
 465         { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
 466         { RN5T567_DC4DAC_SLP, VDD_IO_EXT_VAL_LP, },
 467         { RN5T567_DC1CTL, DCnCTL_EN | DCnCTL_DIS | DCnMODE_SLP(MODE_PSM), },
 468         { RN5T567_DC2CTL, DCnCTL_DIS, },
 469         { RN5T567_DC3CTL, DCnCTL_EN | DCnCTL_DIS | DCnMODE_SLP(MODE_PSM), },
 470         { RN5T567_DC4CTL, DCnCTL_EN | DCnCTL_DIS | DCnMODE_SLP(MODE_PSM), },
 471         { RN5T567_DC1CTL2, DCnCTL2_LIMSDEN | DCnCTL2_LIM_HIGH | DCnCTL2_SR_HIGH | DCnCTL2_OSC_LOW, },
 472         { RN5T567_DC2CTL2, DCnCTL2_LIMSDEN | DCnCTL2_LIM_HIGH | DCnCTL2_SR_HIGH | DCnCTL2_OSC_LOW, },
 473         { RN5T567_DC3CTL2, DCnCTL2_LIMSDEN | DCnCTL2_LIM_HIGH | DCnCTL2_SR_HIGH | DCnCTL2_OSC_LOW, },
 474         { RN5T567_DC4CTL2, DCnCTL2_LIMSDEN | DCnCTL2_LIM_HIGH | DCnCTL2_SR_HIGH | DCnCTL2_OSC_LOW, },
 475         { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
 476         { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
 477         { RN5T567_LDO1DAC, VDD_IO_INT_VAL, },
 478         { RN5T567_LDO2DAC, VDD_ADC_VAL, },
 479         { RN5T567_LDO3DAC, VDD_PMIC_VAL, },
 480         { RN5T567_LDO4DAC, VDD_CSI_VAL, },
 481         { RN5T567_LDO1DAC_SLP, VDD_IO_INT_VAL_LP, },
 482         { RN5T567_LDO2DAC_SLP, VDD_ADC_VAL_LP, },
 483         { RN5T567_LDO3DAC_SLP, VDD_PMIC_VAL_LP, },
 484         { RN5T567_LDO4DAC_SLP, VDD_CSI_VAL_LP, },
 485         { RN5T567_LDO5DAC, VDD_LDO5_VAL, },
 486         { RN5T567_LDO1DAC_SLP, VDD_IO_INT_VAL_LP, },
 487         { RN5T567_LDO2DAC_SLP, VDD_ADC_VAL_LP, },
 488         { RN5T567_LDO3DAC_SLP, VDD_PMIC_VAL_LP, },
 489         { RN5T567_LDO4DAC_SLP, VDD_CSI_VAL_LP, },
 490         { RN5T567_LDOEN1, LDOEN1_VAL, ~LDOEN1_MASK, },
 491         { RN5T567_LDOEN2, LDOEN2_VAL, ~LDOEN2_MASK, },
 492         { RN5T567_LDODIS, 0x1f, ~0x1f, },
 493         { RN5T567_INTPOL, 0, },
 494         { RN5T567_INTEN, 0x3, },
 495         { RN5T567_DCIREN, 0xf, },
 496         { RN5T567_EN_GPIR, 0, },
 497 };
 498
 499 static int pmic_addr = 0x33;
 500 #endif
 501
 502 int board_init(void)
 503 {
 504         int ret;
 505         u32 cpurev = get_cpu_rev();
 506         char f = '?';
 507
 508         if (is_cpu_type(MXC_CPU_MX6UL))
 509                 f = ((cpurev & 0xff) > 0x10) ? '5' : '0';
 510         else if (is_cpu_type(MXC_CPU_MX6ULL))
 511                 f = '8';
 512
 513         debug("%s@%d: cpurev=%08x\n", __func__, __LINE__, cpurev);
 514
 515         printf("Board: Ka-Ro TXUL-%c01%c\n", f, tx6ul_mem_suffix());
 516
 517         get_hab_status();
 518
 519         ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios));
 520         if (ret < 0)
 521                 printf("Failed to request tx6ul_gpios: %d\n", ret);
 522
 523         imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads));
 524
 525         /* Address of boot parameters */
 526         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 527         gd->bd->bi_arch_number = -1;
 528
 529         if (ctrlc() || (wrsr & WRSR_TOUT)) {
 530                 if (wrsr & WRSR_TOUT)
 531                         printf("WDOG RESET detected; Skipping PMIC setup\n");
 532                 else
 533                         printf("<CTRL-C> detected; safeboot enabled\n");
 534 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 535                 tx6ul_temp_check_enabled = false;
 536 #endif
 537                 return 0;
 538         }
 539
 540         ret = tx6_pmic_init(pmic_addr, rn5t567_regs, ARRAY_SIZE(rn5t567_regs));
 541         if (ret) {
 542                 printf("Failed to setup PMIC voltages: %d\n", ret);
 543                 hang();
 544         }
 545         return 0;
 546 }
 547
 548 int dram_init(void)
 549 {
 550         debug("%s@%d: \n", __func__, __LINE__);
 551
 552         /* dram_init must store complete ramsize in gd->ram_size */
 553         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 554                                     PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
 555         return 0;
 556 }
 557
 558 void dram_init_banksize(void)
 559 {
 560         debug("%s@%d: \n", __func__, __LINE__);
 561
 562         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 563         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 564                                                PHYS_SDRAM_1_SIZE);
 565 #if CONFIG_NR_DRAM_BANKS > 1
 566         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 567         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 568                                                PHYS_SDRAM_2_SIZE);
 569 #endif
 570 }
 571
 572 #ifdef  CONFIG_FSL_ESDHC
 573 #define TX6UL_SD_PAD_CTRL       MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |       \
 574                                         PAD_CTL_SPEED_MED |             \
 575                                         PAD_CTL_DSE_40ohm |             \
 576                                         PAD_CTL_SRE_FAST)
 577
 578 static const iomux_v3_cfg_t mmc0_pads[] = {
 579         MX6_PAD_SD1_CMD__USDHC1_CMD | TX6UL_SD_PAD_CTRL,
 580         MX6_PAD_SD1_CLK__USDHC1_CLK | TX6UL_SD_PAD_CTRL,
 581         MX6_PAD_SD1_DATA0__USDHC1_DATA0 | TX6UL_SD_PAD_CTRL,
 582         MX6_PAD_SD1_DATA1__USDHC1_DATA1 | TX6UL_SD_PAD_CTRL,
 583         MX6_PAD_SD1_DATA2__USDHC1_DATA2 | TX6UL_SD_PAD_CTRL,
 584         MX6_PAD_SD1_DATA3__USDHC1_DATA3 | TX6UL_SD_PAD_CTRL,
 585         /* SD1 CD */
 586         MX6_PAD_NAND_CE1_B__GPIO4_IO14 | TX6UL_SD_PAD_CTRL,
 587 };
 588
 589 #ifdef CONFIG_TX6_EMMC
 590 static const iomux_v3_cfg_t mmc1_pads[] = {
 591         MX6_PAD_NAND_WE_B__USDHC2_CMD | TX6UL_SD_PAD_CTRL,
 592         MX6_PAD_NAND_RE_B__USDHC2_CLK | TX6UL_SD_PAD_CTRL,
 593         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | TX6UL_SD_PAD_CTRL,
 594         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | TX6UL_SD_PAD_CTRL,
 595         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | TX6UL_SD_PAD_CTRL,
 596         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | TX6UL_SD_PAD_CTRL,
 597         /* eMMC RESET */
 598         MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
 599                                                         PAD_CTL_DSE_40ohm),
 600 };
 601 #endif
 602
 603 static struct tx6ul_esdhc_cfg {
 604         const iomux_v3_cfg_t *pads;
 605         int num_pads;
 606         enum mxc_clock clkid;
 607         struct fsl_esdhc_cfg cfg;
 608         int cd_gpio;
 609 } tx6ul_esdhc_cfg[] = {
 610 #ifdef CONFIG_TX6_EMMC
 611         {
 612                 .pads = mmc1_pads,
 613                 .num_pads = ARRAY_SIZE(mmc1_pads),
 614                 .clkid = MXC_ESDHC2_CLK,
 615                 .cfg = {
 616                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
 617                         .max_bus_width = 4,
 618                 },
 619                 .cd_gpio = -EINVAL,
 620         },
 621 #endif
 622         {
 623                 .pads = mmc0_pads,
 624                 .num_pads = ARRAY_SIZE(mmc0_pads),
 625                 .clkid = MXC_ESDHC_CLK,
 626                 .cfg = {
 627                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
 628                         .max_bus_width = 4,
 629                 },
 630                 .cd_gpio = TX6UL_SD1_CD_GPIO,
 631         },
 632 };
 633
 634 static inline struct tx6ul_esdhc_cfg *to_tx6ul_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 635 {
 636         return container_of(cfg, struct tx6ul_esdhc_cfg, cfg);
 637 }
 638
 639 int board_mmc_getcd(struct mmc *mmc)
 640 {
 641         struct tx6ul_esdhc_cfg *cfg = to_tx6ul_esdhc_cfg(mmc->priv);
 642
 643         if (cfg->cd_gpio < 0)
 644                 return 1;
 645
 646         debug("SD card %d is %spresent (GPIO %d)\n",
 647               cfg - tx6ul_esdhc_cfg,
 648               gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
 649               cfg->cd_gpio);
 650         return !gpio_get_value(cfg->cd_gpio);
 651 }
 652
 653 int board_mmc_init(bd_t *bis)
 654 {
 655         int i;
 656
 657         debug("%s@%d: \n", __func__, __LINE__);
 658
 659 #ifndef CONFIG_ENV_IS_IN_MMC
 660         if (!(gd->flags & GD_FLG_ENV_READY)) {
 661                 printf("deferred ...");
 662                 return 0;
 663         }
 664 #endif
 665         for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) {
 666                 struct mmc *mmc;
 667                 struct tx6ul_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
 668                 int ret;
 669
 670                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
 671                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
 672
 673                 if (cfg->cd_gpio >= 0) {
 674                         ret = gpio_request_one(cfg->cd_gpio,
 675                                                GPIOFLAG_INPUT, "MMC CD");
 676                         if (ret) {
 677                                 printf("Error %d requesting GPIO%d_%d\n",
 678                                        ret, cfg->cd_gpio / 32,
 679                                        cfg->cd_gpio % 32);
 680                                 continue;
 681                         }
 682                 }
 683
 684                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 685                 fsl_esdhc_initialize(bis, &cfg->cfg);
 686
 687                 mmc = find_mmc_device(i);
 688                 if (mmc == NULL)
 689                         continue;
 690                 if (board_mmc_getcd(mmc))
 691                         mmc_init(mmc);
 692         }
 693         return 0;
 694 }
 695 #endif /* CONFIG_FSL_ESDHC */
 696
 697 enum {
 698         LED_STATE_INIT = -1,
 699         LED_STATE_OFF,
 700         LED_STATE_ON,
 701         LED_STATE_ERR,
 702 };
 703
 704 static inline int calc_blink_rate(void)
 705 {
 706         if (!tx6ul_temp_check_enabled)
 707                 return CONFIG_SYS_HZ;
 708
 709         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
 710                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
 711                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
 712 }
 713
 714 void show_activity(int arg)
 715 {
 716         static int led_state = LED_STATE_INIT;
 717         static int blink_rate;
 718         static ulong last;
 719         int ret;
 720
 721         switch (led_state) {
 722         case LED_STATE_ERR:
 723                 return;
 724
 725         case LED_STATE_INIT:
 726                 last = get_timer(0);
 727                 ret = gpio_set_value(TX6UL_LED_GPIO, 1);
 728                 if (ret)
 729                         led_state = LED_STATE_ERR;
 730                 else
 731                         led_state = LED_STATE_ON;
 732                 blink_rate = calc_blink_rate();
 733                 break;
 734
 735         case LED_STATE_ON:
 736         case LED_STATE_OFF:
 737                 if (get_timer(last) > blink_rate) {
 738                         blink_rate = calc_blink_rate();
 739                         last = get_timer_masked();
 740                         if (led_state == LED_STATE_ON) {
 741                                 gpio_set_value(TX6UL_LED_GPIO, 0);
 742                         } else {
 743                                 gpio_set_value(TX6UL_LED_GPIO, 1);
 744                         }
 745                         led_state = 1 - led_state;
 746                 }
 747                 break;
 748         }
 749 }
 750
 751 static const iomux_v3_cfg_t stk5_jtag_pads[] = {
 752         MX6_PAD_JTAG_MOD__SJC_MOD | TX6UL_GPIO_IN_PAD_CTRL,
 753         MX6_PAD_JTAG_TCK__SJC_TCK | TX6UL_GPIO_IN_PAD_CTRL,
 754         MX6_PAD_JTAG_TRST_B__SJC_TRSTB | TX6UL_GPIO_IN_PAD_CTRL,
 755         MX6_PAD_JTAG_TDI__SJC_TDI | TX6UL_GPIO_IN_PAD_CTRL,
 756         MX6_PAD_JTAG_TDO__SJC_TDO | TX6UL_GPIO_OUT_PAD_CTRL,
 757         MX6_PAD_JTAG_TMS__SJC_TMS | TX6UL_GPIO_IN_PAD_CTRL,
 758 };
 759
 760 static const iomux_v3_cfg_t stk5_pads[] = {
 761         /* SW controlled LED on STK5 baseboard */
 762         MX6_PAD_SNVS_TAMPER9__GPIO5_IO09,
 763
 764         /* I2C bus on DIMM pins 40/41 */
 765         MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
 766         MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
 767
 768         /* TSC200x PEN IRQ */
 769         MX6_PAD_JTAG_TMS__GPIO1_IO11 | TX6UL_GPIO_IN_PAD_CTRL,
 770
 771         /* EDT-FT5x06 Polytouch panel */
 772         MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | TX6UL_GPIO_IN_PAD_CTRL, /* IRQ */
 773         MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 | TX6UL_GPIO_OUT_PAD_CTRL, /* RESET */
 774         MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | TX6UL_GPIO_OUT_PAD_CTRL, /* WAKE */
 775
 776         /* USBH1 */
 777         MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
 778         MX6_PAD_GPIO1_IO03__USB_OTG2_OC | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
 779
 780         /* USBOTG */
 781         MX6_PAD_UART3_CTS_B__GPIO1_IO26 | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
 782         MX6_PAD_UART3_RTS_B__GPIO1_IO27 | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
 783 };
 784
 785 static const struct gpio stk5_gpios[] = {
 786         { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 787
 788         { IMX_GPIO_NR(1, 27), GPIOFLAG_INPUT, "USBOTG OC", },
 789         { IMX_GPIO_NR(1, 26), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 790 };
 791
 792 static const iomux_v3_cfg_t tx_tester_pads[] = {
 793         /* SW controlled LEDs on TX-TESTER-V5 baseboard */
 794         MX6_PAD_SNVS_TAMPER4__GPIO5_IO04, /* red LED */
 795         MX6_PAD_SNVS_TAMPER9__GPIO5_IO09, /* yellow LED */
 796         MX6_PAD_SNVS_TAMPER8__GPIO5_IO08, /* green LED */
 797
 798         MX6_PAD_LCD_DATA04__GPIO3_IO09, /* IO_RESET */
 799
 800         /* I2C bus on DIMM pins 40/41 */
 801         MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
 802         MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
 803
 804         /* USBH1 */
 805         MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
 806         MX6_PAD_GPIO1_IO03__USB_OTG2_OC | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
 807
 808         /* USBOTG */
 809         MX6_PAD_UART3_CTS_B__GPIO1_IO26 | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
 810         MX6_PAD_UART3_RTS_B__GPIO1_IO27 | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
 811
 812         MX6_PAD_LCD_DATA08__GPIO3_IO13 | TX6UL_GPIO_OUT_PAD_CTRL,
 813         MX6_PAD_LCD_DATA09__GPIO3_IO14 | TX6UL_GPIO_OUT_PAD_CTRL,
 814         MX6_PAD_LCD_DATA10__GPIO3_IO15 | TX6UL_GPIO_OUT_PAD_CTRL,
 815
 816         /* USBH_VBUSEN */
 817         MX6_PAD_LCD_DATA11__GPIO3_IO16 | TX6UL_GPIO_OUT_PAD_CTRL,
 818
 819         /*
 820          * no drive capability for DUT_ETN_LINKLED, DUT_ETN_ACTLED
 821          * to not interfere whith the DUT ETN PHY strap pins
 822          */
 823         MX6_PAD_SNVS_TAMPER2__GPIO5_IO02, MUX_PAD_CTRL(PAD_CTL_HYS |
 824                                                        PAD_CTL_DSE_DISABLE |
 825                                                        PAD_CTL_SPEED_LOW),
 826         MX6_PAD_SNVS_TAMPER3__GPIO5_IO03, MUX_PAD_CTRL(PAD_CTL_HYS |
 827                                                        PAD_CTL_DSE_DISABLE |
 828                                                        PAD_CTL_SPEED_LOW),
 829 };
 830
 831 static const struct gpio tx_tester_gpios[] = {
 832         { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LEDGE#", },
 833         { IMX_GPIO_NR(5, 4), GPIOFLAG_OUTPUT_INIT_LOW, "LEDRT#", },
 834         { IMX_GPIO_NR(5, 8), GPIOFLAG_OUTPUT_INIT_LOW, "LEDGN#", },
 835
 836         { IMX_GPIO_NR(1, 26), GPIOFLAG_OUTPUT_INIT_HIGH, "PMIC PWR_ON", },
 837
 838         { IMX_GPIO_NR(3, 5), GPIOFLAG_INPUT, "TSTART#", },
 839         { IMX_GPIO_NR(3, 6), GPIOFLAG_INPUT, "STARTED", },
 840         { IMX_GPIO_NR(3, 7), GPIOFLAG_INPUT, "TSTOP#", },
 841         { IMX_GPIO_NR(3, 8), GPIOFLAG_OUTPUT_INIT_LOW, "STOP#", },
 842
 843         { IMX_GPIO_NR(3, 10), GPIOFLAG_INPUT, "DUT_PGOOD", },
 844
 845         { IMX_GPIO_NR(3, 11), GPIOFLAG_OUTPUT_INIT_HIGH, "VBACKUP_OFF", },
 846         { IMX_GPIO_NR(3, 12), GPIOFLAG_OUTPUT_INIT_LOW, "VBACKUP_LOAD", },
 847
 848         { IMX_GPIO_NR(1, 10), GPIOFLAG_OUTPUT_INIT_LOW, "VOUTLOAD1", },
 849         { IMX_GPIO_NR(3, 30), GPIOFLAG_OUTPUT_INIT_LOW, "VOUTLOAD2", },
 850         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "VOUTLOAD3", },
 851
 852         { IMX_GPIO_NR(3, 13), GPIOFLAG_OUTPUT_INIT_LOW, "VIOLOAD1", },
 853         { IMX_GPIO_NR(3, 14), GPIOFLAG_OUTPUT_INIT_LOW, "VIOLOAD2", },
 854         { IMX_GPIO_NR(3, 15), GPIOFLAG_OUTPUT_INIT_LOW, "VIOLOAD3", },
 855 };
 856
 857 #ifdef CONFIG_LCD
 858 vidinfo_t panel_info = {
 859         /* set to max. size supported by SoC */
 860         .vl_col = 4096,
 861         .vl_row = 1024,
 862
 863         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 864 };
 865
 866 static struct fb_videomode tx6ul_fb_modes[] = {
 867 #ifndef CONFIG_SYS_LVDS_IF
 868         {
 869                 /* Standard VGA timing */
 870                 .name           = "VGA",
 871                 .refresh        = 60,
 872                 .xres           = 640,
 873                 .yres           = 480,
 874                 .pixclock       = KHZ2PICOS(25175),
 875                 .left_margin    = 48,
 876                 .hsync_len      = 96,
 877                 .right_margin   = 16,
 878                 .upper_margin   = 31,
 879                 .vsync_len      = 2,
 880                 .lower_margin   = 12,
 881                 .sync           = FB_SYNC_CLK_LAT_FALL,
 882         },
 883         {
 884                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 885                  * DE high active, 115.2 mm x 86.4 mm display area
 886                  * VGA compatible timing
 887                  */
 888                 .name           = "ETV570",
 889                 .refresh        = 60,
 890                 .xres           = 640,
 891                 .yres           = 480,
 892                 .pixclock       = KHZ2PICOS(25175),
 893                 .left_margin    = 114,
 894                 .hsync_len      = 30,
 895                 .right_margin   = 16,
 896                 .upper_margin   = 32,
 897                 .vsync_len      = 3,
 898                 .lower_margin   = 10,
 899                 .sync           = FB_SYNC_CLK_LAT_FALL,
 900         },
 901         {
 902                 /* Emerging ET0350G0DH6 320 x 240 display.
 903                  * 70.08 mm x 52.56 mm display area.
 904                  */
 905                 .name           = "ET0350",
 906                 .refresh        = 60,
 907                 .xres           = 320,
 908                 .yres           = 240,
 909                 .pixclock       = KHZ2PICOS(6500),
 910                 .left_margin    = 68 - 34,
 911                 .hsync_len      = 34,
 912                 .right_margin   = 20,
 913                 .upper_margin   = 18 - 3,
 914                 .vsync_len      = 3,
 915                 .lower_margin   = 4,
 916                 .sync           = FB_SYNC_CLK_LAT_FALL,
 917         },
 918         {
 919                 /* Emerging ET0430G0DH6 480 x 272 display.
 920                  * 95.04 mm x 53.856 mm display area.
 921                  */
 922                 .name           = "ET0430",
 923                 .refresh        = 60,
 924                 .xres           = 480,
 925                 .yres           = 272,
 926                 .pixclock       = KHZ2PICOS(9000),
 927                 .left_margin    = 2,
 928                 .hsync_len      = 41,
 929                 .right_margin   = 2,
 930                 .upper_margin   = 2,
 931                 .vsync_len      = 10,
 932                 .lower_margin   = 2,
 933         },
 934         {
 935                 /* Emerging ET0500G0DH6 800 x 480 display.
 936                  * 109.6 mm x 66.4 mm display area.
 937                  */
 938                 .name           = "ET0500",
 939                 .refresh        = 60,
 940                 .xres           = 800,
 941                 .yres           = 480,
 942                 .pixclock       = KHZ2PICOS(33260),
 943                 .left_margin    = 216 - 128,
 944                 .hsync_len      = 128,
 945                 .right_margin   = 1056 - 800 - 216,
 946                 .upper_margin   = 35 - 2,
 947                 .vsync_len      = 2,
 948                 .lower_margin   = 525 - 480 - 35,
 949                 .sync           = FB_SYNC_CLK_LAT_FALL,
 950         },
 951         {
 952                 /* Emerging ETQ570G0DH6 320 x 240 display.
 953                  * 115.2 mm x 86.4 mm display area.
 954                  */
 955                 .name           = "ETQ570",
 956                 .refresh        = 60,
 957                 .xres           = 320,
 958                 .yres           = 240,
 959                 .pixclock       = KHZ2PICOS(6400),
 960                 .left_margin    = 38,
 961                 .hsync_len      = 30,
 962                 .right_margin   = 30,
 963                 .upper_margin   = 16, /* 15 according to datasheet */
 964                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 965                 .lower_margin   = 4, /* 4.5 according to datasheet */
 966                 .sync           = FB_SYNC_CLK_LAT_FALL,
 967         },
 968         {
 969                 /* Emerging ET0700G0DH6 800 x 480 display.
 970                  * 152.4 mm x 91.44 mm display area.
 971                  */
 972                 .name           = "ET0700",
 973                 .refresh        = 60,
 974                 .xres           = 800,
 975                 .yres           = 480,
 976                 .pixclock       = KHZ2PICOS(33260),
 977                 .left_margin    = 216 - 128,
 978                 .hsync_len      = 128,
 979                 .right_margin   = 1056 - 800 - 216,
 980                 .upper_margin   = 35 - 2,
 981                 .vsync_len      = 2,
 982                 .lower_margin   = 525 - 480 - 35,
 983                 .sync           = FB_SYNC_CLK_LAT_FALL,
 984         },
 985         {
 986                 /* Emerging ET070001DM6 800 x 480 display.
 987                  * 152.4 mm x 91.44 mm display area.
 988                  */
 989                 .name           = "ET070001DM6",
 990                 .refresh        = 60,
 991                 .xres           = 800,
 992                 .yres           = 480,
 993                 .pixclock       = KHZ2PICOS(33260),
 994                 .left_margin    = 216 - 128,
 995                 .hsync_len      = 128,
 996                 .right_margin   = 1056 - 800 - 216,
 997                 .upper_margin   = 35 - 2,
 998                 .vsync_len      = 2,
 999                 .lower_margin   = 525 - 480 - 35,
1000                 .sync           = 0,
1001         },
1002 #else
1003         {
1004                 /* HannStar HSD100PXN1
1005                  * 202.7m mm x 152.06 mm display area.
1006                  */
1007                 .name           = "HSD100PXN1",
1008                 .refresh        = 60,
1009                 .xres           = 1024,
1010                 .yres           = 768,
1011                 .pixclock       = KHZ2PICOS(65000),
1012                 .left_margin    = 0,
1013                 .hsync_len      = 0,
1014                 .right_margin   = 320,
1015                 .upper_margin   = 0,
1016                 .vsync_len      = 0,
1017                 .lower_margin   = 38,
1018                 .sync           = FB_SYNC_CLK_LAT_FALL,
1019         },
1020 #endif
1021         {
1022                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
1023                 .refresh        = 60,
1024                 .left_margin    = 48,
1025                 .hsync_len      = 96,
1026                 .right_margin   = 16,
1027                 .upper_margin   = 31,
1028                 .vsync_len      = 2,
1029                 .lower_margin   = 12,
1030                 .sync           = FB_SYNC_CLK_LAT_FALL,
1031         },
1032 };
1033
1034 static int lcd_enabled = 1;
1035 static int lcd_bl_polarity;
1036
1037 static int lcd_backlight_polarity(void)
1038 {
1039         return lcd_bl_polarity;
1040 }
1041
1042 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
1043 #ifdef CONFIG_LCD
1044         /* LCD RESET */
1045         MX6_PAD_LCD_RESET__GPIO3_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
1046         /* LCD POWER_ENABLE */
1047         MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
1048         /* LCD Backlight (PWM) */
1049         MX6_PAD_NAND_DQS__GPIO4_IO16 | TX6UL_GPIO_OUT_PAD_CTRL,
1050         /* Display */
1051         MX6_PAD_LCD_DATA00__LCDIF_DATA00,
1052         MX6_PAD_LCD_DATA01__LCDIF_DATA01,
1053         MX6_PAD_LCD_DATA02__LCDIF_DATA02,
1054         MX6_PAD_LCD_DATA03__LCDIF_DATA03,
1055         MX6_PAD_LCD_DATA04__LCDIF_DATA04,
1056         MX6_PAD_LCD_DATA05__LCDIF_DATA05,
1057         MX6_PAD_LCD_DATA06__LCDIF_DATA06,
1058         MX6_PAD_LCD_DATA07__LCDIF_DATA07,
1059         MX6_PAD_LCD_DATA08__LCDIF_DATA08,
1060         MX6_PAD_LCD_DATA09__LCDIF_DATA09,
1061         MX6_PAD_LCD_DATA10__LCDIF_DATA10,
1062         MX6_PAD_LCD_DATA11__LCDIF_DATA11,
1063         MX6_PAD_LCD_DATA12__LCDIF_DATA12,
1064         MX6_PAD_LCD_DATA13__LCDIF_DATA13,
1065         MX6_PAD_LCD_DATA14__LCDIF_DATA14,
1066         MX6_PAD_LCD_DATA15__LCDIF_DATA15,
1067         MX6_PAD_LCD_DATA16__LCDIF_DATA16,
1068         MX6_PAD_LCD_DATA17__LCDIF_DATA17,
1069         MX6_PAD_LCD_DATA18__LCDIF_DATA18,
1070         MX6_PAD_LCD_DATA19__LCDIF_DATA19,
1071         MX6_PAD_LCD_DATA20__LCDIF_DATA20,
1072         MX6_PAD_LCD_DATA21__LCDIF_DATA21,
1073         MX6_PAD_LCD_DATA22__LCDIF_DATA22,
1074         MX6_PAD_LCD_DATA23__LCDIF_DATA23,
1075         MX6_PAD_LCD_HSYNC__LCDIF_HSYNC, /* HSYNC */
1076         MX6_PAD_LCD_VSYNC__LCDIF_VSYNC, /* VSYNC */
1077         MX6_PAD_LCD_ENABLE__LCDIF_ENABLE, /* OE_ACD */
1078         MX6_PAD_LCD_CLK__LCDIF_CLK, /* LSCLK */
1079 #endif
1080 };
1081
1082 static const struct gpio stk5_lcd_gpios[] = {
1083         { TX6UL_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1084         { TX6UL_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1085         { TX6UL_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1086 };
1087
1088 /* run with valid env from NAND/eMMC */
1089 void lcd_enable(void)
1090 {
1091         /* HACK ALERT:
1092          * global variable from common/lcd.c
1093          * Set to 0 here to prevent messages from going to LCD
1094          * rather than serial console
1095          */
1096         lcd_is_enabled = 0;
1097
1098         if (lcd_enabled) {
1099                 karo_load_splashimage(1);
1100
1101                 debug("Switching LCD on\n");
1102                 gpio_set_value(TX6UL_LCD_PWR_GPIO, 1);
1103                 udelay(100);
1104                 gpio_set_value(TX6UL_LCD_RST_GPIO, 1);
1105                 udelay(300000);
1106                 gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
1107                                lcd_backlight_polarity());
1108         }
1109 }
1110
1111 static void lcd_disable(void)
1112 {
1113         if (lcd_enabled) {
1114                 printf("Disabling LCD\n");
1115                 panel_info.vl_row = 0;
1116                 lcd_enabled = 0;
1117         }
1118 }
1119
1120 void lcd_ctrl_init(void *lcdbase)
1121 {
1122         int color_depth = 24;
1123         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1124         const char *vm;
1125         unsigned long val;
1126         int refresh = 60;
1127         struct fb_videomode *p = &tx6ul_fb_modes[0];
1128         struct fb_videomode fb_mode;
1129         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1130
1131         if (!lcd_enabled) {
1132                 debug("LCD disabled\n");
1133                 return;
1134         }
1135
1136         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1137                 lcd_disable();
1138                 setenv("splashimage", NULL);
1139                 return;
1140         }
1141
1142         karo_fdt_move_fdt();
1143         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1144
1145         if (video_mode == NULL) {
1146                 lcd_disable();
1147                 return;
1148         }
1149         vm = video_mode;
1150         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1151                 p = &fb_mode;
1152                 debug("Using video mode from FDT\n");
1153                 vm += strlen(vm);
1154                 if (fb_mode.xres > panel_info.vl_col ||
1155                         fb_mode.yres > panel_info.vl_row) {
1156                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1157                                fb_mode.xres, fb_mode.yres,
1158                                panel_info.vl_col, panel_info.vl_row);
1159                         lcd_enabled = 0;
1160                         return;
1161                 }
1162         }
1163         if (p->name != NULL)
1164                 debug("Trying compiled-in video modes\n");
1165         while (p->name != NULL) {
1166                 if (strcmp(p->name, vm) == 0) {
1167                         debug("Using video mode: '%s'\n", p->name);
1168                         vm += strlen(vm);
1169                         break;
1170                 }
1171                 p++;
1172         }
1173         if (*vm != '\0')
1174                 debug("Trying to decode video_mode: '%s'\n", vm);
1175         while (*vm != '\0') {
1176                 if (*vm >= '0' && *vm <= '9') {
1177                         char *end;
1178
1179                         val = simple_strtoul(vm, &end, 0);
1180                         if (end > vm) {
1181                                 if (!xres_set) {
1182                                         if (val > panel_info.vl_col)
1183                                                 val = panel_info.vl_col;
1184                                         p->xres = val;
1185                                         panel_info.vl_col = val;
1186                                         xres_set = 1;
1187                                 } else if (!yres_set) {
1188                                         if (val > panel_info.vl_row)
1189                                                 val = panel_info.vl_row;
1190                                         p->yres = val;
1191                                         panel_info.vl_row = val;
1192                                         yres_set = 1;
1193                                 } else if (!bpp_set) {
1194                                         switch (val) {
1195                                         case 8:
1196                                         case 16:
1197                                         case 18:
1198                                         case 24:
1199                                         case 32:
1200                                                 color_depth = val;
1201                                                 break;
1202
1203                                         default:
1204                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1205                                                        end - vm, vm,
1206                                                        color_depth);
1207                                         }
1208                                         bpp_set = 1;
1209                                 } else if (!refresh_set) {
1210                                         refresh = val;
1211                                         refresh_set = 1;
1212                                 }
1213                         }
1214                         vm = end;
1215                 }
1216                 switch (*vm) {
1217                 case '@':
1218                         bpp_set = 1;
1219                         /* fallthru */
1220                 case '-':
1221                         yres_set = 1;
1222                         /* fallthru */
1223                 case 'x':
1224                         xres_set = 1;
1225                         /* fallthru */
1226                 case 'M':
1227                 case 'R':
1228                         vm++;
1229                         break;
1230
1231                 default:
1232                         if (*vm != '\0')
1233                                 vm++;
1234                 }
1235         }
1236         if (p->xres == 0 || p->yres == 0) {
1237                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1238                 lcd_enabled = 0;
1239                 printf("Supported video modes are:");
1240                 for (p = &tx6ul_fb_modes[0]; p->name != NULL; p++) {
1241                         printf(" %s", p->name);
1242                 }
1243                 printf("\n");
1244                 return;
1245         }
1246         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1247                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1248                        p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1249                 lcd_enabled = 0;
1250                 return;
1251         }
1252         panel_info.vl_col = p->xres;
1253         panel_info.vl_row = p->yres;
1254
1255         switch (color_depth) {
1256         case 8:
1257                 panel_info.vl_bpix = LCD_COLOR8;
1258                 break;
1259         case 16:
1260                 panel_info.vl_bpix = LCD_COLOR16;
1261                 break;
1262         default:
1263                 panel_info.vl_bpix = LCD_COLOR32;
1264         }
1265
1266         if (refresh_set || p->pixclock == 0)
1267                 p->pixclock = KHZ2PICOS(refresh *
1268                                         (p->xres + p->left_margin +
1269                                          p->right_margin + p->hsync_len) *
1270                                         (p->yres + p->upper_margin +
1271                                          p->lower_margin + p->vsync_len) /
1272                                         1000);
1273         debug("Pixel clock set to %lu.%03lu MHz\n",
1274               PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1275
1276         if (p != &fb_mode) {
1277                 int ret;
1278
1279                 debug("Creating new display-timing node from '%s'\n",
1280                       video_mode);
1281                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1282                 if (ret)
1283                         printf("Failed to create new display-timing node from '%s': %d\n",
1284                                video_mode, ret);
1285         }
1286
1287         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1288         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1289                                          ARRAY_SIZE(stk5_lcd_pads));
1290
1291         debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
1292               color_depth, refresh);
1293
1294         if (karo_load_splashimage(0) == 0) {
1295                 char vmode[128];
1296
1297                 /* setup env variable for mxsfb display driver */
1298                 snprintf(vmode, sizeof(vmode),
1299                          "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
1300                          p->xres, p->yres, p->left_margin, p->right_margin,
1301                          p->upper_margin, p->lower_margin, p->hsync_len,
1302                          p->vsync_len, p->sync, p->pixclock, color_depth);
1303                 setenv("videomode", vmode);
1304
1305                 debug("Initializing LCD controller\n");
1306                 lcdif_clk_enable();
1307                 video_hw_init();
1308                 setenv("videomode", NULL);
1309         } else {
1310                 debug("Skipping initialization of LCD controller\n");
1311         }
1312 }
1313 #else
1314 #define lcd_enabled 0
1315 #endif /* CONFIG_LCD */
1316
1317 #ifndef CONFIG_ENV_IS_IN_MMC
1318 static void tx6ul_mmc_init(void)
1319 {
1320         puts("MMC:   ");
1321         if (board_mmc_init(gd->bd) < 0)
1322                 cpu_mmc_init(gd->bd);
1323         print_mmc_devices(',');
1324 }
1325 #else
1326 static inline void tx6ul_mmc_init(void)
1327 {
1328 }
1329 #endif
1330
1331 static void stk5_board_init(void)
1332 {
1333         int ret;
1334
1335         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1336         if (ret < 0) {
1337                 printf("Failed to request stk5_gpios: %d\n", ret);
1338                 return;
1339         }
1340
1341         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1342         if (getenv_yesno("jtag_enable") != 0) {
1343                 /* true if unset or set to one of: 'yYtT1' */
1344                 imx_iomux_v3_setup_multiple_pads(stk5_jtag_pads, ARRAY_SIZE(stk5_jtag_pads));
1345         }
1346
1347         debug("%s@%d: \n", __func__, __LINE__);
1348 }
1349
1350 static void stk5v3_board_init(void)
1351 {
1352         debug("%s@%d: \n", __func__, __LINE__);
1353         stk5_board_init();
1354         debug("%s@%d: \n", __func__, __LINE__);
1355         tx6ul_mmc_init();
1356 }
1357
1358 static void stk5v5_board_init(void)
1359 {
1360         int ret;
1361
1362         stk5_board_init();
1363         tx6ul_mmc_init();
1364
1365         ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
1366                                "Flexcan Transceiver");
1367         if (ret) {
1368                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1369                 return;
1370         }
1371
1372         imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 |
1373                                TX6UL_GPIO_OUT_PAD_CTRL);
1374 }
1375
1376 static void tx_tester_board_init(void)
1377 {
1378         int ret;
1379
1380         setenv("video_mode", NULL);
1381         setenv("touchpanel", NULL);
1382         if (getenv("eth1addr") && !getenv("ethprime"))
1383                 setenv("ethprime", "FEC1");
1384
1385         ret = gpio_request_array(tx_tester_gpios, ARRAY_SIZE(tx_tester_gpios));
1386         if (ret) {
1387                 printf("Failed to request TX-Tester GPIOs: %d\n", ret);
1388                 return;
1389         }
1390         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1391
1392         if (wrsr & WRSR_TOUT)
1393                 gpio_set_value(IMX_GPIO_NR(5, 4), 1);
1394
1395         if (getenv_yesno("jtag_enable") != 0) {
1396                 /* true if unset or set to one of: 'yYtT1' */
1397                 imx_iomux_v3_setup_multiple_pads(stk5_jtag_pads,
1398                                                  ARRAY_SIZE(stk5_jtag_pads));
1399         }
1400
1401         gpio_set_value(IMX_GPIO_NR(3, 8), 1);
1402 }
1403
1404 static void tx6ul_set_cpu_clock(void)
1405 {
1406         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1407
1408         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1409                 return;
1410
1411         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1412                 printf("%s detected; skipping cpu clock change\n",
1413                        (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1414                 return;
1415         }
1416         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1417                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1418                 printf("CPU clock set to %lu.%03lu MHz\n",
1419                        cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1420         } else {
1421                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1422         }
1423 }
1424
1425 int board_late_init(void)
1426 {
1427         const char *baseboard;
1428
1429         debug("%s@%d: \n", __func__, __LINE__);
1430
1431         env_cleanup();
1432
1433         if (tx6ul_temp_check_enabled)
1434                 check_cpu_temperature(1);
1435
1436         tx6ul_set_cpu_clock();
1437
1438         if (had_ctrlc())
1439                 setenv_ulong("safeboot", 1);
1440         else if (wrsr & WRSR_TOUT)
1441                 setenv_ulong("wdreset", 1);
1442         else
1443                 karo_fdt_move_fdt();
1444
1445         baseboard = getenv("baseboard");
1446         if (!baseboard)
1447                 goto exit;
1448
1449         printf("Baseboard: %s\n", baseboard);
1450
1451         if (strncmp(baseboard, "stk5", 4) == 0) {
1452                 if ((strlen(baseboard) == 4) ||
1453                         strcmp(baseboard, "stk5-v3") == 0) {
1454                         stk5v3_board_init();
1455                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1456                         const char *otg_mode = getenv("otg_mode");
1457
1458                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1459                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1460                                        otg_mode, baseboard);
1461                                 setenv("otg_mode", "none");
1462                         }
1463                         stk5v5_board_init();
1464                 } else {
1465                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1466                                 baseboard + 4);
1467                 }
1468         } else if (strncmp(baseboard, "ulmb-", 5) == 0) {
1469                         const char *otg_mode = getenv("otg_mode");
1470
1471                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1472                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1473                                        otg_mode, baseboard);
1474                                 setenv("otg_mode", "none");
1475                         }
1476                         stk5_board_init();
1477         } else if (strncmp(baseboard, "tx-tester-", 10) == 0) {
1478                         const char *otg_mode = getenv("otg_mode");
1479
1480                         if (!otg_mode || strcmp(otg_mode, "none") != 0)
1481                                 setenv("otg_mode", "device");
1482                         tx_tester_board_init();
1483         } else {
1484                 printf("WARNING: Unsupported baseboard: '%s'\n",
1485                         baseboard);
1486                 printf("Reboot with <CTRL-C> pressed to fix this\n");
1487                 if (!had_ctrlc())
1488                         return -EINVAL;
1489         }
1490
1491 exit:
1492         debug("%s@%d: \n", __func__, __LINE__);
1493
1494         clear_ctrlc();
1495         return 0;
1496 }
1497
1498 #ifdef CONFIG_FEC_MXC
1499
1500 #ifndef ETH_ALEN
1501 #define ETH_ALEN 6
1502 #endif
1503
1504 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
1505 {
1506         unsigned int mac0, mac1, mac2;
1507         unsigned int __maybe_unused fuse3_override, fuse4_override;
1508
1509         memset(mac, 0, 6);
1510
1511         switch (dev_id) {
1512         case 0:
1513                 if (fuse_read(4, 2, &mac0)) {
1514                         printf("Failed to read MAC0 fuse\n");
1515                         return;
1516                 }
1517                 if (fuse_read(4, 3, &mac1)) {
1518                         printf("Failed to read MAC1 fuse\n");
1519                         return;
1520                 }
1521                 mac[0] = mac1 >> 8;
1522                 mac[1] = mac1;
1523                 mac[2] = mac0 >> 24;
1524                 mac[3] = mac0 >> 16;
1525                 mac[4] = mac0 >> 8;
1526                 mac[5] = mac0;
1527                 break;
1528
1529         case 1:
1530                 if (fuse_read(4, 3, &mac1)) {
1531                         printf("Failed to read MAC1 fuse\n");
1532                         return;
1533                 }
1534                 debug("read %08x from fuse 3\n", mac1);
1535                 if (fuse_read(4, 4, &mac2)) {
1536                         printf("Failed to read MAC2 fuse\n");
1537                         return;
1538                 }
1539                 debug("read %08x from fuse 4\n", mac2);
1540                 mac[0] = mac2 >> 24;
1541                 mac[1] = mac2 >> 16;
1542                 mac[2] = mac2 >> 8;
1543                 mac[3] = mac2;
1544                 mac[4] = mac1 >> 24;
1545                 mac[5] = mac1 >> 16;
1546                 break;
1547
1548         default:
1549                 return;
1550         }
1551         debug("%s@%d: Done %d %pM\n", __func__, __LINE__, dev_id, mac);
1552 }
1553
1554 static void tx6ul_init_mac(void)
1555 {
1556         u8 mac[ETH_ALEN];
1557         const char *baseboard = getenv("baseboard");
1558
1559         imx_get_mac_from_fuse(0, mac);
1560         if (!is_valid_ethaddr(mac)) {
1561                 printf("No valid MAC address programmed\n");
1562                 return;
1563         }
1564         printf("MAC addr from fuse: %pM\n", mac);
1565         if (!getenv("ethaddr"))
1566                 eth_setenv_enetaddr("ethaddr", mac);
1567
1568         if (!baseboard || strncmp(baseboard, "stk5", 4) == 0) {
1569                 setenv("eth1addr", NULL);
1570                 return;
1571         }
1572         if (getenv("eth1addr"))
1573                 return;
1574         imx_get_mac_from_fuse(1, mac);
1575         if (is_valid_ethaddr(mac))
1576                 eth_setenv_enetaddr("eth1addr", mac);
1577 }
1578
1579 int board_eth_init(bd_t *bis)
1580 {
1581         int ret;
1582
1583         tx6ul_init_mac();
1584
1585         /* delay at least 21ms for the PHY internal POR signal to deassert */
1586         udelay(22000);
1587
1588         imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads,
1589                                          ARRAY_SIZE(tx6ul_enet1_pads));
1590
1591         /* Deassert RESET to the external phys */
1592         gpio_set_value(TX6UL_FEC_RST_GPIO, 1);
1593
1594         if (getenv("ethaddr")) {
1595                 ret = fecmxc_initialize_multi(bis, 0, 0, ENET_BASE_ADDR);
1596                 if (ret) {
1597                         printf("failed to initialize FEC0: %d\n", ret);
1598                         return ret;
1599                 }
1600         }
1601         if (getenv("eth1addr")) {
1602                 ret = gpio_request_array(tx6ul_fec2_gpios,
1603                                          ARRAY_SIZE(tx6ul_fec2_gpios));
1604                 if (ret < 0) {
1605                         printf("Failed to request tx6ul_fec2_gpios: %d\n", ret);
1606                 }
1607                 imx_iomux_v3_setup_multiple_pads(tx6ul_enet2_pads,
1608                                                  ARRAY_SIZE(tx6ul_enet2_pads));
1609
1610                 writel(0x00100000, 0x020c80e4); /* assert ENET2_125M_EN */
1611
1612                 /* Minimum PHY reset duration */
1613                 udelay(100);
1614                 gpio_set_value(TX6UL_FEC2_RST_GPIO, 1);
1615                 /* Wait for PHY internal POR to finish */
1616                 udelay(22000);
1617
1618                 ret = fecmxc_initialize_multi(bis, 1, 2, ENET2_BASE_ADDR);
1619                 if (ret) {
1620                         printf("failed to initialize FEC1: %d\n", ret);
1621                         return ret;
1622                 }
1623         }
1624         return 0;
1625 }
1626 #endif /* CONFIG_FEC_MXC */
1627
1628 #ifdef CONFIG_SERIAL_TAG
1629 void get_board_serial(struct tag_serialnr *serialnr)
1630 {
1631         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1632         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1633
1634         serialnr->low = readl(&fuse->cfg0);
1635         serialnr->high = readl(&fuse->cfg1);
1636 }
1637 #endif
1638
1639 #if defined(CONFIG_OF_BOARD_SETUP)
1640 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1641 #include <jffs2/jffs2.h>
1642 #include <mtd_node.h>
1643 static struct node_info nodes[] = {
1644         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1645 };
1646 #else
1647 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1648 #endif
1649
1650 static const char *tx6ul_touchpanels[] = {
1651         "ti,tsc2007",
1652         "edt,edt-ft5x06",
1653         "eeti,egalax_ts",
1654 };
1655
1656 int ft_board_setup(void *blob, bd_t *bd)
1657 {
1658         const char *baseboard = getenv("baseboard");
1659         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1660         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1661         int ret;
1662
1663         ret = fdt_increase_size(blob, 4096);
1664         if (ret) {
1665                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1666                 return ret;
1667         }
1668         if (stk5_v5)
1669                 karo_fdt_enable_node(blob, "stk5led", 0);
1670
1671         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1672
1673         karo_fdt_fixup_touchpanel(blob, tx6ul_touchpanels,
1674                                   ARRAY_SIZE(tx6ul_touchpanels));
1675         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1676         karo_fdt_fixup_flexcan(blob, stk5_v5);
1677
1678         karo_fdt_update_fb_mode(blob, video_mode, "/lcd-panel");
1679
1680         return 0;
1681 }
1682 #endif /* CONFIG_OF_BOARD_SETUP */