karo: tx6: rework PMIC code to allow for different configs for same chip
[karo-tx-uboot.git] / board / karo / tx6 / tx6ul.c
1 /*
2  * Copyright (C) 2015 Lothar WaƟmann <LW@KARO-electronics.de>
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  *
6  */
7 #include <common.h>
8 #include <errno.h>
9 #include <libfdt.h>
10 #include <fdt_support.h>
11 #include <lcd.h>
12 #include <netdev.h>
13 #include <mmc.h>
14 #include <fsl_esdhc.h>
15 #include <video_fb.h>
16 #include <ipu.h>
17 #include <mxcfb.h>
18 #include <i2c.h>
19 #include <linux/fb.h>
20 #include <asm/io.h>
21 #include <asm/gpio.h>
22 #include <asm/arch/mx6-pins.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/hab.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/crm_regs.h>
27 #include <asm/arch/sys_proto.h>
28
29 #include "../common/karo.h"
30 #include "pmic.h"
31
32 #define __data __attribute__((section(".data")))
33
34 #define TX6UL_FEC_RST_GPIO              IMX_GPIO_NR(5, 6)
35 #define TX6UL_FEC_PWR_GPIO              IMX_GPIO_NR(5, 7)
36 #define TX6UL_FEC_INT_GPIO              IMX_GPIO_NR(5, 5)
37 #define TX6UL_LED_GPIO                  IMX_GPIO_NR(5, 9)
38
39 #define TX6UL_LCD_PWR_GPIO              IMX_GPIO_NR(5, 4)
40 #define TX6UL_LCD_RST_GPIO              IMX_GPIO_NR(3, 4)
41 #define TX6UL_LCD_BACKLIGHT_GPIO        IMX_GPIO_NR(4, 16)
42
43 #define TX6UL_I2C1_SCL_GPIO             CONFIG_SOFT_I2C_GPIO_SCL
44 #define TX6UL_I2C1_SDA_GPIO             CONFIG_SOFT_I2C_GPIO_SDA
45
46 #define TX6UL_SD1_CD_GPIO               IMX_GPIO_NR(4, 14)
47
48 #ifdef CONFIG_MX6_TEMPERATURE_MIN
49 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
50 #else
51 #define TEMPERATURE_MIN                 (-40)
52 #endif
53 #ifdef CONFIG_MX6_TEMPERATURE_HOT
54 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
55 #else
56 #define TEMPERATURE_HOT                 80
57 #endif
58
59 DECLARE_GLOBAL_DATA_PTR;
60
61 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
62
63 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
64 #ifdef CONFIG_SECURE_BOOT
65 char __csf_data[0] __attribute__((section(".__csf_data")));
66 #endif
67
68 static const iomux_v3_cfg_t const tx6ul_pads[] = {
69         /* UART pads */
70 #if CONFIG_MXC_UART_BASE == UART1_BASE
71         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX,
72         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX,
73         MX6_PAD_UART1_RTS_B__UART1_DCE_RTS,
74         MX6_PAD_UART1_CTS_B__UART1_DCE_CTS,
75 #endif
76 #if CONFIG_MXC_UART_BASE == UART2_BASE
77         MX6_PAD_UART2_TX_DATA__UART2_DCE_TX,
78         MX6_PAD_UART2_RX_DATA__UART2_DCE_RX,
79         MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS,
80         MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS,
81 #endif
82 #if CONFIG_MXC_UART_BASE == UART5_BASE
83         MX6_PAD_GPIO1_IO04__UART5_DCE_TX,
84         MX6_PAD_GPIO1_IO05__UART5_DCE_RX,
85         MX6_PAD_GPIO1_IO08__UART5_DCE_RTS,
86         MX6_PAD_GPIO1_IO09__UART5_DCE_CTS,
87 #endif
88         /* internal I2C */
89         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
90                         MUX_PAD_CTRL(PAD_CTL_DSE_240ohm), /* I2C SCL */
91         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
92                         MUX_PAD_CTRL(PAD_CTL_DSE_240ohm | PAD_CTL_HYS |
93                         PAD_CTL_ODE), /* I2C SDA */
94
95         /* FEC PHY GPIO functions */
96         MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_CFG_SION, /* PHY POWER */
97         MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | MUX_CFG_SION, /* PHY RESET */
98         MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
99                                                         PAD_CTL_DSE_40ohm), /* PHY INT */
100 };
101
102 #define TX6_ENET_PAD_CTRL       (PAD_CTL_SPEED_HIGH |   \
103                                 PAD_CTL_DSE_48ohm |     \
104                                 PAD_CTL_PUS_100K_UP |   \
105                                 PAD_CTL_SRE_FAST)
106 #define TX6_GPIO_OUT_PAD_CTRL   (PAD_CTL_SPEED_LOW |    \
107                                 PAD_CTL_DSE_60ohm |     \
108                                 PAD_CTL_SRE_SLOW)
109 #define TX6_GPIO_IN_PAD_CTRL    (PAD_CTL_SPEED_LOW |    \
110                                 PAD_CTL_PUS_47K_UP)
111
112 static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = {
113         /* FEC functions */
114         MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_48ohm |
115                                 PAD_CTL_SPEED_MED),
116         MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
117                                 PAD_CTL_DSE_48ohm |
118                                 PAD_CTL_SPEED_MED),
119         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_CFG_SION |
120                                 MUX_PAD_CTRL(PAD_CTL_SPEED_MED |
121                                 PAD_CTL_DSE_40ohm |
122                                 PAD_CTL_SRE_FAST),
123         MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
124         MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
125         MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
126         MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
127         MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
128         MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
129         MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
130
131         MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_CFG_SION |
132                                 MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |
133                                 PAD_CTL_DSE_48ohm |
134                                 PAD_CTL_SRE_FAST),
135         MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
136         MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
137         MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
138         MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
139         MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
140         MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
141         MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
142 };
143
144 #define TX6_I2C_PAD_CTRL        (PAD_CTL_PUS_22K_UP |   \
145                                 PAD_CTL_SPEED_MED |     \
146                                 PAD_CTL_DSE_34ohm |     \
147                                 PAD_CTL_SRE_FAST)
148
149 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
150         /* internal I2C */
151         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
152         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
153 };
154
155 static const struct gpio const tx6ul_gpios[] = {
156         /* These two entries are used to forcefully reinitialize the I2C bus */
157         { TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
158         { TX6UL_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
159
160         { TX6UL_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
161         { TX6UL_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
162         { TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
163 };
164
165 #define GPIO_DR 0
166 #define GPIO_DIR 4
167 #define GPIO_PSR 8
168
169 static void tx6_i2c_recover(void)
170 {
171         int i;
172         int bad = 0;
173 #define SCL_BIT         (1 << (TX6UL_I2C1_SCL_GPIO % 32))
174 #define SDA_BIT         (1 << (TX6UL_I2C1_SDA_GPIO % 32))
175 #define I2C_GPIO_BASE   (GPIO1_BASE_ADDR + TX6UL_I2C1_SCL_GPIO / 32 * 0x4000)
176
177         if ((readl(I2C_GPIO_BASE + GPIO_PSR) &
178                         (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
179                 return;
180
181         debug("Clearing I2C bus\n");
182         if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SCL_BIT)) {
183                 printf("I2C SCL stuck LOW\n");
184                 bad++;
185
186                 writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
187                         I2C_GPIO_BASE + GPIO_DR);
188                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
189                         I2C_GPIO_BASE + GPIO_DIR);
190         }
191         if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)) {
192                 printf("I2C SDA stuck LOW\n");
193                 bad++;
194
195                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) & ~SDA_BIT,
196                         I2C_GPIO_BASE + GPIO_DIR);
197                 writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
198                         I2C_GPIO_BASE + GPIO_DR);
199                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
200                         I2C_GPIO_BASE + GPIO_DIR);
201
202                 imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
203                                                 ARRAY_SIZE(tx6_i2c_gpio_pads));
204                 udelay(10);
205
206                 for (i = 0; i < 18; i++) {
207                         u32 reg = readl(I2C_GPIO_BASE + GPIO_DR) ^ SCL_BIT;
208
209                         debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
210                         writel(reg, I2C_GPIO_BASE + GPIO_DR);
211                         udelay(10);
212                         if (reg & SCL_BIT &&
213                                 readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)
214                                 break;
215                 }
216         }
217         if (bad) {
218                 u32 reg = readl(I2C_GPIO_BASE + GPIO_PSR);
219
220                 if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
221                         printf("I2C bus recovery succeeded\n");
222                 } else {
223                         printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
224                                 SCL_BIT | SDA_BIT);
225                 }
226         }
227 }
228
229 /* placed in section '.data' to prevent overwriting relocation info
230  * overlayed with bss
231  */
232 static u32 wrsr __data;
233
234 #define WRSR_POR                        (1 << 4)
235 #define WRSR_TOUT                       (1 << 1)
236 #define WRSR_SFTW                       (1 << 0)
237
238 static void print_reset_cause(void)
239 {
240         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
241         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
242         u32 srsr;
243         char *dlm = "";
244
245         printf("Reset cause: ");
246
247         srsr = readl(&src_regs->srsr);
248         wrsr = readw(wdt_base + 4);
249
250         if (wrsr & WRSR_POR) {
251                 printf("%sPOR", dlm);
252                 dlm = " | ";
253         }
254         if (srsr & 0x00004) {
255                 printf("%sCSU", dlm);
256                 dlm = " | ";
257         }
258         if (srsr & 0x00008) {
259                 printf("%sIPP USER", dlm);
260                 dlm = " | ";
261         }
262         if (srsr & 0x00010) {
263                 if (wrsr & WRSR_SFTW) {
264                         printf("%sSOFT", dlm);
265                         dlm = " | ";
266                 }
267                 if (wrsr & WRSR_TOUT) {
268                         printf("%sWDOG", dlm);
269                         dlm = " | ";
270                 }
271         }
272         if (srsr & 0x00020) {
273                 printf("%sJTAG HIGH-Z", dlm);
274                 dlm = " | ";
275         }
276         if (srsr & 0x00040) {
277                 printf("%sJTAG SW", dlm);
278                 dlm = " | ";
279         }
280         if (srsr & 0x10000) {
281                 printf("%sWARM BOOT", dlm);
282                 dlm = " | ";
283         }
284         if (dlm[0] == '\0')
285                 printf("unknown");
286
287         printf("\n");
288 }
289
290 #ifdef CONFIG_IMX6_THERMAL
291 #include <thermal.h>
292 #include <imx_thermal.h>
293 #include <fuse.h>
294
295 static void print_temperature(void)
296 {
297         struct udevice *thermal_dev;
298         int cpu_tmp, minc, maxc, ret;
299         char const *grade_str;
300         static u32 __data thermal_calib;
301
302         puts("Temperature: ");
303         switch (get_cpu_temp_grade(&minc, &maxc)) {
304         case TEMP_AUTOMOTIVE:
305                 grade_str = "Automotive";
306                 break;
307         case TEMP_INDUSTRIAL:
308                 grade_str = "Industrial";
309                 break;
310         case TEMP_EXTCOMMERCIAL:
311                 grade_str = "Extended Commercial";
312                 break;
313         default:
314                 grade_str = "Commercial";
315         }
316         printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
317         ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
318         if (ret == 0) {
319                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
320
321                 if (ret == 0)
322                         printf(" at %dC", cpu_tmp);
323                 else
324                         puts(" - failed to read sensor data");
325         } else {
326                 puts(" - no sensor device found");
327         }
328
329         if (fuse_read(1, 6, &thermal_calib) == 0) {
330                 printf(" - calibration data 0x%08x\n", thermal_calib);
331         } else {
332                 puts(" - Failed to read thermal calib fuse\n");
333         }
334 }
335 #else
336 static inline void print_temperature(void)
337 {
338 }
339 #endif
340
341 int checkboard(void)
342 {
343         u32 cpurev = get_cpu_rev();
344         char *cpu_str = "?";
345
346         switch ((cpurev >> 12) & 0xff) {
347         case MXC_CPU_MX6SL:
348                 cpu_str = "SL";
349                 break;
350         case MXC_CPU_MX6DL:
351                 cpu_str = "DL";
352                 break;
353         case MXC_CPU_MX6SOLO:
354                 cpu_str = "SOLO";
355                 break;
356         case MXC_CPU_MX6Q:
357                 cpu_str = "Q";
358                 break;
359         case MXC_CPU_MX6UL:
360                 cpu_str = "UL";
361                 break;
362         }
363
364         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
365                 cpu_str,
366                 (cpurev & 0x000F0) >> 4,
367                 (cpurev & 0x0000F) >> 0,
368                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
369
370         print_temperature();
371         print_reset_cause();
372 #ifdef CONFIG_MX6_TEMPERATURE_HOT
373         check_cpu_temperature(1);
374 #endif
375         tx6_i2c_recover();
376         return 0;
377 }
378
379 /* serial port not initialized at this point */
380 int board_early_init_f(void)
381 {
382         return 0;
383 }
384
385 #ifndef CONFIG_MX6_TEMPERATURE_HOT
386 static bool tx6_temp_check_enabled = true;
387 #else
388 #define tx6_temp_check_enabled  0
389 #endif
390
391 static inline u8 tx6ul_mem_suffix(void)
392 {
393 #ifdef CONFIG_TX6_NAND
394         return '0';
395 #else
396         return '1';
397 #endif
398 }
399
400 /* PMIC settings */
401 #define VDD_RTC_VAL             rn5t_mV_to_regval_rtc(3000)
402 #define VDD_CORE_VAL            rn5t_mV_to_regval(1300)         /* DCDC1 */
403 #define VDD_CORE_VAL_LP         rn5t_mV_to_regval(900)
404 #define VDD_DDR_VAL             rn5t_mV_to_regval(1350)         /* DCDC3 */
405 #define VDD_DDR_VAL_LP          rn5t_mV_to_regval(1350)
406 #define VDD_HIGH_VAL            rn5t_mV_to_regval(3300)         /* DCDC4 */
407 #define VDD_HIGH_VAL_LP         rn5t_mV_to_regval(3300)
408 #define VDD_CSI_VAL             rn5t_mV_to_regval2(3300)        /* LDO4 */
409 #define VDD_CSI_VAL_LP          rn5t_mV_to_regval2(3300)
410
411 static struct pmic_regs rn5t567_regs[] = {
412         { RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, },
413         { RN5T567_DC2CTL, DC2_DC2DIS, },
414         { RN5T567_DC1DAC, VDD_CORE_VAL, },
415         { RN5T567_DC3DAC, VDD_DDR_VAL, },
416         { RN5T567_DC4DAC, VDD_HIGH_VAL, },
417         { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
418         { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
419         { RN5T567_DC4DAC_SLP, VDD_HIGH_VAL_LP, },
420         { RN5T567_LDOEN1, 0x01f, ~0x1f, },
421         { RN5T567_LDOEN2, 0x10, ~0x30, },
422         { RN5T567_LDODIS, 0x00, },
423         { RN5T567_LDO4DAC, VDD_CSI_VAL, },
424         { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
425         { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
426 };
427
428 static int pmic_addr __maybe_unused = 0x33;
429
430 int board_init(void)
431 {
432         int ret;
433
434         debug("%s@%d: \n", __func__, __LINE__);
435
436         printf("Board: Ka-Ro TXUL-001%c\n",
437                 tx6ul_mem_suffix());
438
439         get_hab_status();
440
441         ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios));
442         if (ret < 0) {
443                 printf("Failed to request tx6ul_gpios: %d\n", ret);
444         }
445         imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads));
446
447         /* Address of boot parameters */
448         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
449         gd->bd->bi_arch_number = -1;
450
451         if (ctrlc() || (wrsr & WRSR_TOUT)) {
452                 if (wrsr & WRSR_TOUT)
453                         printf("WDOG RESET detected; Skipping PMIC setup\n");
454                 else
455                         printf("<CTRL-C> detected; safeboot enabled\n");
456 #ifndef CONFIG_MX6_TEMPERATURE_HOT
457                 tx6_temp_check_enabled = false;
458 #endif
459                 return 0;
460         }
461
462         ret = tx6_pmic_init(pmic_addr, rn5t567_regs, ARRAY_SIZE(rn5t567_regs));
463         if (ret) {
464                 printf("Failed to setup PMIC voltages: %d\n", ret);
465                 hang();
466         }
467         return 0;
468 }
469
470 int dram_init(void)
471 {
472         debug("%s@%d: \n", __func__, __LINE__);
473
474         /* dram_init must store complete ramsize in gd->ram_size */
475         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
476                                 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
477         return 0;
478 }
479
480 void dram_init_banksize(void)
481 {
482         debug("%s@%d: \n", __func__, __LINE__);
483
484         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
485         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
486                         PHYS_SDRAM_1_SIZE);
487 #if CONFIG_NR_DRAM_BANKS > 1
488         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
489         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
490                         PHYS_SDRAM_2_SIZE);
491 #endif
492 }
493
494 #ifdef  CONFIG_FSL_ESDHC
495 #define TX6_SD_PAD_CTRL         (PAD_CTL_PUS_47K_UP |   \
496                                 PAD_CTL_SPEED_MED |     \
497                                 PAD_CTL_DSE_40ohm |     \
498                                 PAD_CTL_SRE_FAST)
499
500 static const iomux_v3_cfg_t mmc0_pads[] = {
501         MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
502         MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
503         MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
504         MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
505         MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
506         MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
507         /* SD1 CD */
508         MX6_PAD_NAND_CE1_B__GPIO4_IO14 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
509 };
510
511 #ifdef CONFIG_TX6_EMMC
512 static const iomux_v3_cfg_t mmc1_pads[] = {
513         MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
514         MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
515         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
516         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
517         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
518         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
519         /* eMMC RESET */
520         MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
521                                                 PAD_CTL_DSE_40ohm),
522 };
523 #endif
524
525 static struct tx6_esdhc_cfg {
526         const iomux_v3_cfg_t *pads;
527         int num_pads;
528         enum mxc_clock clkid;
529         struct fsl_esdhc_cfg cfg;
530         int cd_gpio;
531 } tx6ul_esdhc_cfg[] = {
532 #ifdef CONFIG_TX6_EMMC
533         {
534                 .pads = mmc1_pads,
535                 .num_pads = ARRAY_SIZE(mmc1_pads),
536                 .clkid = MXC_ESDHC2_CLK,
537                 .cfg = {
538                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
539                         .max_bus_width = 4,
540                 },
541                 .cd_gpio = -EINVAL,
542         },
543 #endif
544         {
545                 .pads = mmc0_pads,
546                 .num_pads = ARRAY_SIZE(mmc0_pads),
547                 .clkid = MXC_ESDHC_CLK,
548                 .cfg = {
549                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
550                         .max_bus_width = 4,
551                 },
552                 .cd_gpio = TX6UL_SD1_CD_GPIO,
553         },
554 };
555
556 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
557 {
558         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
559 }
560
561 int board_mmc_getcd(struct mmc *mmc)
562 {
563         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
564
565         if (cfg->cd_gpio < 0)
566                 return 1;
567
568         debug("SD card %d is %spresent (GPIO %d)\n",
569                 cfg - tx6ul_esdhc_cfg,
570                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
571                 cfg->cd_gpio);
572         return !gpio_get_value(cfg->cd_gpio);
573 }
574
575 int board_mmc_init(bd_t *bis)
576 {
577         int i;
578
579         debug("%s@%d: \n", __func__, __LINE__);
580
581         for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) {
582                 struct mmc *mmc;
583                 struct tx6_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
584                 int ret;
585
586                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
587                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
588
589                 if (cfg->cd_gpio >= 0) {
590                         ret = gpio_request_one(cfg->cd_gpio,
591                                         GPIOFLAG_INPUT, "MMC CD");
592                         if (ret) {
593                                 printf("Error %d requesting GPIO%d_%d\n",
594                                         ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
595                                 continue;
596                         }
597                 }
598
599                 debug("%s: Initializing MMC slot %d\n", __func__, i);
600                 fsl_esdhc_initialize(bis, &cfg->cfg);
601
602                 mmc = find_mmc_device(i);
603                 if (mmc == NULL)
604                         continue;
605                 if (board_mmc_getcd(mmc))
606                         mmc_init(mmc);
607         }
608         return 0;
609 }
610 #endif /* CONFIG_CMD_MMC */
611
612 #ifdef CONFIG_FEC_MXC
613
614 #ifndef ETH_ALEN
615 #define ETH_ALEN 6
616 #endif
617
618 int board_eth_init(bd_t *bis)
619 {
620         int ret;
621
622         debug("%s@%d: \n", __func__, __LINE__);
623
624         /* delay at least 21ms for the PHY internal POR signal to deassert */
625         udelay(22000);
626
627         imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads,
628                                         ARRAY_SIZE(tx6ul_enet1_pads));
629
630         /* Deassert RESET to the external phy */
631         gpio_set_value(TX6UL_FEC_RST_GPIO, 1);
632
633         if (getenv("ethaddr")) {
634                 ret = fecmxc_initialize_multi(bis, 0, -1, ENET_BASE_ADDR);
635                 if (ret) {
636                         printf("failed to initialize FEC0: %d\n", ret);
637                         return ret;
638                 }
639         }
640         if (getenv("eth1addr")) {
641                 ret = fecmxc_initialize_multi(bis, 1, -1, ENET2_BASE_ADDR);
642                 if (ret) {
643                         printf("failed to initialize FEC1: %d\n", ret);
644                         return ret;
645                 }
646         }
647         return 0;
648 }
649
650 static void tx6_init_mac(void)
651 {
652         u8 mac[ETH_ALEN];
653
654         imx_get_mac_from_fuse(0, mac);
655         if (!is_valid_ethaddr(mac)) {
656                 printf("No valid MAC address programmed\n");
657                 return;
658         }
659
660         printf("MAC addr from fuse: %pM\n", mac);
661         eth_setenv_enetaddr("ethaddr", mac);
662
663         imx_get_mac_from_fuse(1, mac);
664         eth_setenv_enetaddr("eth1addr", mac);
665 }
666 #else
667 static inline void tx6_init_mac(void)
668 {
669 }
670 #endif /* CONFIG_FEC_MXC */
671
672 enum {
673         LED_STATE_INIT = -1,
674         LED_STATE_OFF,
675         LED_STATE_ON,
676 };
677
678 static inline int calc_blink_rate(void)
679 {
680         if (!tx6_temp_check_enabled)
681                 return CONFIG_SYS_HZ;
682
683         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
684                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
685                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
686 }
687
688 void show_activity(int arg)
689 {
690         static int led_state = LED_STATE_INIT;
691         static int blink_rate;
692         static ulong last;
693
694         if (led_state == LED_STATE_INIT) {
695                 last = get_timer(0);
696                 gpio_set_value(TX6UL_LED_GPIO, 1);
697                 led_state = LED_STATE_ON;
698                 blink_rate = calc_blink_rate();
699         } else {
700                 if (get_timer(last) > blink_rate) {
701                         blink_rate = calc_blink_rate();
702                         last = get_timer_masked();
703                         if (led_state == LED_STATE_ON) {
704                                 gpio_set_value(TX6UL_LED_GPIO, 0);
705                         } else {
706                                 gpio_set_value(TX6UL_LED_GPIO, 1);
707                         }
708                         led_state = 1 - led_state;
709                 }
710         }
711 }
712
713 static const iomux_v3_cfg_t stk5_pads[] = {
714         /* SW controlled LED on STK5 baseboard */
715         MX6_PAD_SNVS_TAMPER9__GPIO5_IO09,
716
717         /* I2C bus on DIMM pins 40/41 */
718         MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
719         MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
720
721         /* TSC200x PEN IRQ */
722         MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL),
723 #if 0
724         /* EDT-FT5x06 Polytouch panel */
725         MX6_PAD_NAND_CS2__GPIO6_IO15 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* IRQ */
726         MX6_PAD_EIM_A16__GPIO2_IO22 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* RESET */
727         MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* WAKE */
728
729         /* USBH1 */
730         MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
731         MX6_PAD_EIM_D30__GPIO3_IO30 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
732         /* USBOTG */
733         MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* USBOTG ID */
734         MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
735         MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
736 #endif
737 };
738
739 static const struct gpio stk5_gpios[] = {
740         { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
741
742         { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
743         { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
744         { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
745         { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
746         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
747 };
748
749 #ifdef CONFIG_LCD
750 static u16 tx6_cmap[256];
751 vidinfo_t panel_info = {
752         /* set to max. size supported by SoC */
753         .vl_col = 4096,
754         .vl_row = 1024,
755
756         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
757         .cmap = tx6_cmap,
758 };
759
760 static struct fb_videomode tx6_fb_modes[] = {
761 #ifndef CONFIG_SYS_LVDS_IF
762         {
763                 /* Standard VGA timing */
764                 .name           = "VGA",
765                 .refresh        = 60,
766                 .xres           = 640,
767                 .yres           = 480,
768                 .pixclock       = KHZ2PICOS(25175),
769                 .left_margin    = 48,
770                 .hsync_len      = 96,
771                 .right_margin   = 16,
772                 .upper_margin   = 31,
773                 .vsync_len      = 2,
774                 .lower_margin   = 12,
775                 .sync           = FB_SYNC_CLK_LAT_FALL,
776         },
777         {
778                 /* Emerging ETV570 640 x 480 display. Syncs low active,
779                  * DE high active, 115.2 mm x 86.4 mm display area
780                  * VGA compatible timing
781                  */
782                 .name           = "ETV570",
783                 .refresh        = 60,
784                 .xres           = 640,
785                 .yres           = 480,
786                 .pixclock       = KHZ2PICOS(25175),
787                 .left_margin    = 114,
788                 .hsync_len      = 30,
789                 .right_margin   = 16,
790                 .upper_margin   = 32,
791                 .vsync_len      = 3,
792                 .lower_margin   = 10,
793                 .sync           = FB_SYNC_CLK_LAT_FALL,
794         },
795         {
796                 /* Emerging ET0350G0DH6 320 x 240 display.
797                  * 70.08 mm x 52.56 mm display area.
798                  */
799                 .name           = "ET0350",
800                 .refresh        = 60,
801                 .xres           = 320,
802                 .yres           = 240,
803                 .pixclock       = KHZ2PICOS(6500),
804                 .left_margin    = 68 - 34,
805                 .hsync_len      = 34,
806                 .right_margin   = 20,
807                 .upper_margin   = 18 - 3,
808                 .vsync_len      = 3,
809                 .lower_margin   = 4,
810                 .sync           = FB_SYNC_CLK_LAT_FALL,
811         },
812         {
813                 /* Emerging ET0430G0DH6 480 x 272 display.
814                  * 95.04 mm x 53.856 mm display area.
815                  */
816                 .name           = "ET0430",
817                 .refresh        = 60,
818                 .xres           = 480,
819                 .yres           = 272,
820                 .pixclock       = KHZ2PICOS(9000),
821                 .left_margin    = 2,
822                 .hsync_len      = 41,
823                 .right_margin   = 2,
824                 .upper_margin   = 2,
825                 .vsync_len      = 10,
826                 .lower_margin   = 2,
827         },
828         {
829                 /* Emerging ET0500G0DH6 800 x 480 display.
830                  * 109.6 mm x 66.4 mm display area.
831                  */
832                 .name           = "ET0500",
833                 .refresh        = 60,
834                 .xres           = 800,
835                 .yres           = 480,
836                 .pixclock       = KHZ2PICOS(33260),
837                 .left_margin    = 216 - 128,
838                 .hsync_len      = 128,
839                 .right_margin   = 1056 - 800 - 216,
840                 .upper_margin   = 35 - 2,
841                 .vsync_len      = 2,
842                 .lower_margin   = 525 - 480 - 35,
843                 .sync           = FB_SYNC_CLK_LAT_FALL,
844         },
845         {
846                 /* Emerging ETQ570G0DH6 320 x 240 display.
847                  * 115.2 mm x 86.4 mm display area.
848                  */
849                 .name           = "ETQ570",
850                 .refresh        = 60,
851                 .xres           = 320,
852                 .yres           = 240,
853                 .pixclock       = KHZ2PICOS(6400),
854                 .left_margin    = 38,
855                 .hsync_len      = 30,
856                 .right_margin   = 30,
857                 .upper_margin   = 16, /* 15 according to datasheet */
858                 .vsync_len      = 3, /* TVP -> 1>x>5 */
859                 .lower_margin   = 4, /* 4.5 according to datasheet */
860                 .sync           = FB_SYNC_CLK_LAT_FALL,
861         },
862         {
863                 /* Emerging ET0700G0DH6 800 x 480 display.
864                  * 152.4 mm x 91.44 mm display area.
865                  */
866                 .name           = "ET0700",
867                 .refresh        = 60,
868                 .xres           = 800,
869                 .yres           = 480,
870                 .pixclock       = KHZ2PICOS(33260),
871                 .left_margin    = 216 - 128,
872                 .hsync_len      = 128,
873                 .right_margin   = 1056 - 800 - 216,
874                 .upper_margin   = 35 - 2,
875                 .vsync_len      = 2,
876                 .lower_margin   = 525 - 480 - 35,
877                 .sync           = FB_SYNC_CLK_LAT_FALL,
878         },
879         {
880                 /* Emerging ET070001DM6 800 x 480 display.
881                  * 152.4 mm x 91.44 mm display area.
882                  */
883                 .name           = "ET070001DM6",
884                 .refresh        = 60,
885                 .xres           = 800,
886                 .yres           = 480,
887                 .pixclock       = KHZ2PICOS(33260),
888                 .left_margin    = 216 - 128,
889                 .hsync_len      = 128,
890                 .right_margin   = 1056 - 800 - 216,
891                 .upper_margin   = 35 - 2,
892                 .vsync_len      = 2,
893                 .lower_margin   = 525 - 480 - 35,
894                 .sync           = 0,
895         },
896 #else
897         {
898                 /* HannStar HSD100PXN1
899                  * 202.7m mm x 152.06 mm display area.
900                  */
901                 .name           = "HSD100PXN1",
902                 .refresh        = 60,
903                 .xres           = 1024,
904                 .yres           = 768,
905                 .pixclock       = KHZ2PICOS(65000),
906                 .left_margin    = 0,
907                 .hsync_len      = 0,
908                 .right_margin   = 320,
909                 .upper_margin   = 0,
910                 .vsync_len      = 0,
911                 .lower_margin   = 38,
912                 .sync           = FB_SYNC_CLK_LAT_FALL,
913         },
914 #endif
915         {
916                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
917                 .refresh        = 60,
918                 .left_margin    = 48,
919                 .hsync_len      = 96,
920                 .right_margin   = 16,
921                 .upper_margin   = 31,
922                 .vsync_len      = 2,
923                 .lower_margin   = 12,
924                 .sync           = FB_SYNC_CLK_LAT_FALL,
925         },
926 };
927
928 static int lcd_enabled = 1;
929 static int lcd_bl_polarity;
930
931 static int lcd_backlight_polarity(void)
932 {
933         return lcd_bl_polarity;
934 }
935
936 void lcd_enable(void)
937 {
938         /* HACK ALERT:
939          * global variable from common/lcd.c
940          * Set to 0 here to prevent messages from going to LCD
941          * rather than serial console
942          */
943         lcd_is_enabled = 0;
944
945         if (lcd_enabled) {
946                 karo_load_splashimage(1);
947
948                 debug("Switching LCD on\n");
949                 gpio_set_value(TX6UL_LCD_PWR_GPIO, 1);
950                 udelay(100);
951                 gpio_set_value(TX6UL_LCD_RST_GPIO, 1);
952                 udelay(300000);
953                 gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
954                         lcd_backlight_polarity());
955         }
956 }
957
958 void lcd_disable(void)
959 {
960         if (lcd_enabled) {
961                 printf("Disabling LCD\n");
962 //              ipuv3_fb_shutdown();
963         }
964 }
965
966 void lcd_panel_disable(void)
967 {
968         if (lcd_enabled) {
969                 debug("Switching LCD off\n");
970                 gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
971                         !lcd_backlight_polarity());
972                 gpio_set_value(TX6UL_LCD_RST_GPIO, 0);
973                 gpio_set_value(TX6UL_LCD_PWR_GPIO, 0);
974         }
975 }
976
977 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
978 #if 1
979         /* LCD RESET */
980         MX6_PAD_LCD_RESET__LCDIF_RESET,
981         /* LCD POWER_ENABLE */
982         MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
983         /* LCD Backlight (PWM) */
984         MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
985 #endif
986 #ifdef CONFIG_LCD
987         /* Display */
988         MX6_PAD_LCD_DATA00__LCDIF_DATA00,
989         MX6_PAD_LCD_DATA01__LCDIF_DATA01,
990         MX6_PAD_LCD_DATA02__LCDIF_DATA02,
991         MX6_PAD_LCD_DATA03__LCDIF_DATA03,
992         MX6_PAD_LCD_DATA04__LCDIF_DATA04,
993         MX6_PAD_LCD_DATA05__LCDIF_DATA05,
994         MX6_PAD_LCD_DATA06__LCDIF_DATA06,
995         MX6_PAD_LCD_DATA07__LCDIF_DATA07,
996         MX6_PAD_LCD_DATA08__LCDIF_DATA08,
997         MX6_PAD_LCD_DATA09__LCDIF_DATA09,
998         MX6_PAD_LCD_DATA10__LCDIF_DATA10,
999         MX6_PAD_LCD_DATA11__LCDIF_DATA11,
1000         MX6_PAD_LCD_DATA12__LCDIF_DATA12,
1001         MX6_PAD_LCD_DATA13__LCDIF_DATA13,
1002         MX6_PAD_LCD_DATA14__LCDIF_DATA14,
1003         MX6_PAD_LCD_DATA15__LCDIF_DATA15,
1004         MX6_PAD_LCD_DATA16__LCDIF_DATA16,
1005         MX6_PAD_LCD_DATA17__LCDIF_DATA17,
1006         MX6_PAD_LCD_DATA18__LCDIF_DATA18,
1007         MX6_PAD_LCD_DATA19__LCDIF_DATA19,
1008         MX6_PAD_LCD_DATA20__LCDIF_DATA20,
1009         MX6_PAD_LCD_DATA21__LCDIF_DATA21,
1010         MX6_PAD_LCD_DATA22__LCDIF_DATA22,
1011         MX6_PAD_LCD_DATA23__LCDIF_DATA23,
1012         MX6_PAD_LCD_HSYNC__LCDIF_HSYNC, /* HSYNC */
1013         MX6_PAD_LCD_VSYNC__LCDIF_VSYNC, /* VSYNC */
1014         MX6_PAD_LCD_ENABLE__LCDIF_ENABLE, /* OE_ACD */
1015         MX6_PAD_LCD_CLK__LCDIF_CLK, /* LSCLK */
1016 #endif
1017 };
1018
1019 static const struct gpio stk5_lcd_gpios[] = {
1020 //      { TX6UL_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1021         { TX6UL_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1022         { TX6UL_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1023 };
1024
1025 void lcd_ctrl_init(void *lcdbase)
1026 {
1027         int color_depth = 24;
1028         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1029         const char *vm;
1030         unsigned long val;
1031         int refresh = 60;
1032         struct fb_videomode *p = &tx6_fb_modes[0];
1033         struct fb_videomode fb_mode;
1034         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1035         int pix_fmt;
1036         int lcd_bus_width;
1037
1038         if (!lcd_enabled) {
1039                 debug("LCD disabled\n");
1040                 return;
1041         }
1042
1043         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1044                 debug("Disabling LCD\n");
1045                 lcd_enabled = 0;
1046                 setenv("splashimage", NULL);
1047                 return;
1048         }
1049
1050         karo_fdt_move_fdt();
1051         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1052
1053         if (video_mode == NULL) {
1054                 debug("Disabling LCD\n");
1055                 lcd_enabled = 0;
1056                 return;
1057         }
1058         vm = video_mode;
1059         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1060                 p = &fb_mode;
1061                 debug("Using video mode from FDT\n");
1062                 vm += strlen(vm);
1063                 if (fb_mode.xres > panel_info.vl_col ||
1064                         fb_mode.yres > panel_info.vl_row) {
1065                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1066                                 fb_mode.xres, fb_mode.yres,
1067                                 panel_info.vl_col, panel_info.vl_row);
1068                         lcd_enabled = 0;
1069                         return;
1070                 }
1071         }
1072         if (p->name != NULL)
1073                 debug("Trying compiled-in video modes\n");
1074         while (p->name != NULL) {
1075                 if (strcmp(p->name, vm) == 0) {
1076                         debug("Using video mode: '%s'\n", p->name);
1077                         vm += strlen(vm);
1078                         break;
1079                 }
1080                 p++;
1081         }
1082         if (*vm != '\0')
1083                 debug("Trying to decode video_mode: '%s'\n", vm);
1084         while (*vm != '\0') {
1085                 if (*vm >= '0' && *vm <= '9') {
1086                         char *end;
1087
1088                         val = simple_strtoul(vm, &end, 0);
1089                         if (end > vm) {
1090                                 if (!xres_set) {
1091                                         if (val > panel_info.vl_col)
1092                                                 val = panel_info.vl_col;
1093                                         p->xres = val;
1094                                         panel_info.vl_col = val;
1095                                         xres_set = 1;
1096                                 } else if (!yres_set) {
1097                                         if (val > panel_info.vl_row)
1098                                                 val = panel_info.vl_row;
1099                                         p->yres = val;
1100                                         panel_info.vl_row = val;
1101                                         yres_set = 1;
1102                                 } else if (!bpp_set) {
1103                                         switch (val) {
1104                                         case 32:
1105                                         case 24:
1106                                                 if (is_lvds())
1107                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
1108                                                 /* fallthru */
1109                                         case 16:
1110                                         case 8:
1111                                                 color_depth = val;
1112                                                 break;
1113
1114                                         case 18:
1115                                                 if (is_lvds()) {
1116                                                         color_depth = val;
1117                                                         break;
1118                                                 }
1119                                                 /* fallthru */
1120                                         default:
1121                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1122                                                         end - vm, vm, color_depth);
1123                                         }
1124                                         bpp_set = 1;
1125                                 } else if (!refresh_set) {
1126                                         refresh = val;
1127                                         refresh_set = 1;
1128                                 }
1129                         }
1130                         vm = end;
1131                 }
1132                 switch (*vm) {
1133                 case '@':
1134                         bpp_set = 1;
1135                         /* fallthru */
1136                 case '-':
1137                         yres_set = 1;
1138                         /* fallthru */
1139                 case 'x':
1140                         xres_set = 1;
1141                         /* fallthru */
1142                 case 'M':
1143                 case 'R':
1144                         vm++;
1145                         break;
1146
1147                 default:
1148                         if (*vm != '\0')
1149                                 vm++;
1150                 }
1151         }
1152         if (p->xres == 0 || p->yres == 0) {
1153                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1154                 lcd_enabled = 0;
1155                 printf("Supported video modes are:");
1156                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1157                         printf(" %s", p->name);
1158                 }
1159                 printf("\n");
1160                 return;
1161         }
1162         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1163                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1164                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1165                 lcd_enabled = 0;
1166                 return;
1167         }
1168         panel_info.vl_col = p->xres;
1169         panel_info.vl_row = p->yres;
1170
1171         switch (color_depth) {
1172         case 8:
1173                 panel_info.vl_bpix = LCD_COLOR8;
1174                 break;
1175         case 16:
1176                 panel_info.vl_bpix = LCD_COLOR16;
1177                 break;
1178         default:
1179                 panel_info.vl_bpix = LCD_COLOR32;
1180         }
1181
1182         p->pixclock = KHZ2PICOS(refresh *
1183                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1184                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1185                                 1000);
1186         debug("Pixel clock set to %lu.%03lu MHz\n",
1187                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1188
1189         if (p != &fb_mode) {
1190                 int ret;
1191
1192                 debug("Creating new display-timing node from '%s'\n",
1193                         video_mode);
1194                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1195                 if (ret)
1196                         printf("Failed to create new display-timing node from '%s': %d\n",
1197                                 video_mode, ret);
1198         }
1199
1200         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1201         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1202                                         ARRAY_SIZE(stk5_lcd_pads));
1203
1204         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1205         switch (lcd_bus_width) {
1206         case 24:
1207                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1208                 break;
1209
1210         case 18:
1211                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1212                 break;
1213
1214         case 16:
1215                 if (!is_lvds()) {
1216                         pix_fmt = IPU_PIX_FMT_RGB565;
1217                         break;
1218                 }
1219                 /* fallthru */
1220         default:
1221                 lcd_enabled = 0;
1222                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1223                         lcd_bus_width);
1224                 return;
1225         }
1226         if (is_lvds()) {
1227                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1228                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1229                 uint32_t gpr2;
1230                 uint32_t gpr3;
1231
1232                 if (lvds_chan_mask == 0) {
1233                         printf("No LVDS channel active\n");
1234                         lcd_enabled = 0;
1235                         return;
1236                 }
1237
1238                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1239                 if (lcd_bus_width == 24)
1240                         gpr2 |= (1 << 5) | (1 << 7);
1241                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1242                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1243                 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1244                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1245
1246                 gpr3 = readl(IOMUXC_BASE_ADDR + 0xc);
1247                 gpr3 &= ~((3 << 8) | (3 << 6));
1248                 writel(gpr3, IOMUXC_BASE_ADDR + 0xc);
1249         }
1250         if (karo_load_splashimage(0) == 0) {
1251 #if 0
1252                 int ret;
1253
1254                 debug("Initializing LCD controller\n");
1255                 ret = ipuv3_fb_init(p, 0, pix_fmt,
1256                                 is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
1257                                 di_clk_rate, -1);
1258                 if (ret) {
1259                         printf("Failed to initialize FB driver: %d\n", ret);
1260                         lcd_enabled = 0;
1261                 }
1262 #else
1263                 lcd_enabled = pix_fmt * 0;
1264 #endif
1265         } else {
1266                 debug("Skipping initialization of LCD controller\n");
1267         }
1268 }
1269 #else
1270 #define lcd_enabled 0
1271 #endif /* CONFIG_LCD */
1272
1273 static void stk5_board_init(void)
1274 {
1275         int ret;
1276
1277         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1278         if (ret < 0) {
1279                 printf("Failed to request stk5_gpios: %d\n", ret);
1280                 return;
1281         }
1282         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1283 debug("%s@%d: \n", __func__, __LINE__);
1284 }
1285
1286 static void stk5v3_board_init(void)
1287 {
1288 debug("%s@%d: \n", __func__, __LINE__);
1289         stk5_board_init();
1290 debug("%s@%d: \n", __func__, __LINE__);
1291 }
1292
1293 static void stk5v5_board_init(void)
1294 {
1295         int ret;
1296
1297         stk5_board_init();
1298
1299         ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
1300                         "Flexcan Transceiver");
1301         if (ret) {
1302                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1303                 return;
1304         }
1305
1306         imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 |
1307                         MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL));
1308 }
1309
1310 static void tx6ul_set_cpu_clock(void)
1311 {
1312         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1313
1314         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1315                 return;
1316
1317         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1318                 printf("%s detected; skipping cpu clock change\n",
1319                         (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1320                 return;
1321         }
1322         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1323                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1324                 printf("CPU clock set to %lu.%03lu MHz\n",
1325                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1326         } else {
1327                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1328         }
1329 }
1330
1331 int board_late_init(void)
1332 {
1333         int ret = 0;
1334         const char *baseboard;
1335
1336         debug("%s@%d: \n", __func__, __LINE__);
1337
1338         env_cleanup();
1339
1340         if (tx6_temp_check_enabled)
1341                 check_cpu_temperature(1);
1342
1343         tx6ul_set_cpu_clock();
1344
1345         if (had_ctrlc())
1346                 setenv_ulong("safeboot", 1);
1347         else if (wrsr & WRSR_TOUT)
1348                 setenv_ulong("wdreset", 1);
1349         else
1350                 karo_fdt_move_fdt();
1351
1352         baseboard = getenv("baseboard");
1353         if (!baseboard)
1354                 goto exit;
1355
1356         printf("Baseboard: %s\n", baseboard);
1357
1358         if (strncmp(baseboard, "stk5", 4) == 0) {
1359                 if ((strlen(baseboard) == 4) ||
1360                         strcmp(baseboard, "stk5-v3") == 0) {
1361                         stk5v3_board_init();
1362                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1363                         const char *otg_mode = getenv("otg_mode");
1364
1365                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1366                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1367                                         otg_mode, baseboard);
1368                                 setenv("otg_mode", "none");
1369                         }
1370                         stk5v5_board_init();
1371                 } else {
1372                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1373                                 baseboard + 4);
1374                 }
1375         } else {
1376                 printf("WARNING: Unsupported baseboard: '%s'\n",
1377                         baseboard);
1378                 ret = -EINVAL;
1379         }
1380
1381 exit:
1382 debug("%s@%d: \n", __func__, __LINE__);
1383         tx6_init_mac();
1384 debug("%s@%d: \n", __func__, __LINE__);
1385
1386         clear_ctrlc();
1387         return ret;
1388 }
1389
1390 #ifdef CONFIG_SERIAL_TAG
1391 void get_board_serial(struct tag_serialnr *serialnr)
1392 {
1393         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1394         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1395
1396         serialnr->low = readl(&fuse->cfg0);
1397         serialnr->high = readl(&fuse->cfg1);
1398 }
1399 #endif
1400
1401 #if defined(CONFIG_OF_BOARD_SETUP)
1402 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1403 #include <jffs2/jffs2.h>
1404 #include <mtd_node.h>
1405 static struct node_info nodes[] = {
1406         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1407 };
1408 #else
1409 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1410 #endif
1411
1412 static const char *tx6_touchpanels[] = {
1413         "ti,tsc2007",
1414         "edt,edt-ft5x06",
1415         "eeti,egalax_ts",
1416 };
1417
1418 int ft_board_setup(void *blob, bd_t *bd)
1419 {
1420         const char *baseboard = getenv("baseboard");
1421         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1422         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1423         int ret;
1424
1425         ret = fdt_increase_size(blob, 4096);
1426         if (ret) {
1427                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1428                 return ret;
1429         }
1430         if (stk5_v5)
1431                 karo_fdt_enable_node(blob, "stk5led", 0);
1432
1433         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1434
1435         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1436                                 ARRAY_SIZE(tx6_touchpanels));
1437         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1438         karo_fdt_fixup_flexcan(blob, stk5_v5);
1439
1440         karo_fdt_update_fb_mode(blob, video_mode);
1441
1442         return 0;
1443 }
1444 #endif /* CONFIG_OF_BOARD_SETUP */