board/karo/tx6/tx6ul.c

   1 /*
   2  * Copyright (C) 2015 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  *
   6  */
   7 #include <common.h>
   8 #include <errno.h>
   9 #include <libfdt.h>
  10 #include <fdt_support.h>
  11 #include <lcd.h>
  12 #include <netdev.h>
  13 #include <mmc.h>
  14 #include <fsl_esdhc.h>
  15 #include <video_fb.h>
  16 #include <ipu.h>
  17 #include <mxcfb.h>
  18 #include <i2c.h>
  19 #include <linux/fb.h>
  20 #include <asm/io.h>
  21 #include <asm/gpio.h>
  22 #include <asm/arch/mx6-pins.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/hab.h>
  25 #include <asm/arch/imx-regs.h>
  26 #include <asm/arch/crm_regs.h>
  27 #include <asm/arch/sys_proto.h>
  28
  29 #include "../common/karo.h"
  30 #include "pmic.h"
  31
  32 #define __data __attribute__((section(".data")))
  33
  34 #define TX6UL_FEC_RST_GPIO              IMX_GPIO_NR(5, 6)
  35 #define TX6UL_FEC_PWR_GPIO              IMX_GPIO_NR(5, 7)
  36 #define TX6UL_FEC_INT_GPIO              IMX_GPIO_NR(5, 5)
  37 #define TX6UL_LED_GPIO                  IMX_GPIO_NR(5, 9)
  38
  39 #define TX6UL_LCD_PWR_GPIO              IMX_GPIO_NR(5, 4)
  40 #define TX6UL_LCD_RST_GPIO              IMX_GPIO_NR(3, 4)
  41 #define TX6UL_LCD_BACKLIGHT_GPIO        IMX_GPIO_NR(4, 16)
  42
  43 #define TX6UL_I2C1_SCL_GPIO             CONFIG_SOFT_I2C_GPIO_SCL
  44 #define TX6UL_I2C1_SDA_GPIO             CONFIG_SOFT_I2C_GPIO_SDA
  45
  46 #define TX6UL_SD1_CD_GPIO               IMX_GPIO_NR(4, 14)
  47
  48 #ifdef CONFIG_MX6_TEMPERATURE_MIN
  49 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
  50 #else
  51 #define TEMPERATURE_MIN                 (-40)
  52 #endif
  53 #ifdef CONFIG_MX6_TEMPERATURE_HOT
  54 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
  55 #else
  56 #define TEMPERATURE_HOT                 80
  57 #endif
  58
  59 DECLARE_GLOBAL_DATA_PTR;
  60
  61 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  62
  63 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
  64 #ifdef CONFIG_SECURE_BOOT
  65 char __csf_data[0] __attribute__((section(".__csf_data")));
  66 #endif
  67
  68 static const iomux_v3_cfg_t const tx6ul_pads[] = {
  69         /* UART pads */
  70 #if CONFIG_MXC_UART_BASE == UART1_BASE
  71         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX,
  72         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX,
  73         MX6_PAD_UART1_RTS_B__UART1_DCE_RTS,
  74         MX6_PAD_UART1_CTS_B__UART1_DCE_CTS,
  75 #endif
  76 #if CONFIG_MXC_UART_BASE == UART2_BASE
  77         MX6_PAD_UART2_TX_DATA__UART2_DCE_TX,
  78         MX6_PAD_UART2_RX_DATA__UART2_DCE_RX,
  79         MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS,
  80         MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS,
  81 #endif
  82 #if CONFIG_MXC_UART_BASE == UART5_BASE
  83         MX6_PAD_GPIO1_IO04__UART5_DCE_TX,
  84         MX6_PAD_GPIO1_IO05__UART5_DCE_RX,
  85         MX6_PAD_GPIO1_IO08__UART5_DCE_RTS,
  86         MX6_PAD_GPIO1_IO09__UART5_DCE_CTS,
  87 #endif
  88         /* internal I2C */
  89         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
  90                         MUX_PAD_CTRL(PAD_CTL_DSE_240ohm), /* I2C SCL */
  91         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
  92                         MUX_PAD_CTRL(PAD_CTL_DSE_240ohm | PAD_CTL_HYS |
  93                         PAD_CTL_ODE), /* I2C SDA */
  94
  95         /* FEC PHY GPIO functions */
  96         MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_CFG_SION, /* PHY POWER */
  97         MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | MUX_CFG_SION, /* PHY RESET */
  98         MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
  99                                                         PAD_CTL_DSE_40ohm), /* PHY INT */
 100 };
 101
 102 #define TX6_ENET_PAD_CTRL       (PAD_CTL_SPEED_HIGH |   \
 103                                 PAD_CTL_DSE_48ohm |     \
 104                                 PAD_CTL_PUS_100K_UP |   \
 105                                 PAD_CTL_SRE_FAST)
 106 #define TX6_GPIO_OUT_PAD_CTRL   (PAD_CTL_SPEED_LOW |    \
 107                                 PAD_CTL_DSE_60ohm |     \
 108                                 PAD_CTL_SRE_SLOW)
 109 #define TX6_GPIO_IN_PAD_CTRL    (PAD_CTL_SPEED_LOW |    \
 110                                 PAD_CTL_PUS_47K_UP)
 111
 112 static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = {
 113         /* FEC functions */
 114         MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_48ohm |
 115                                 PAD_CTL_SPEED_MED),
 116         MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
 117                                 PAD_CTL_DSE_48ohm |
 118                                 PAD_CTL_SPEED_MED),
 119         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_CFG_SION |
 120                                 MUX_PAD_CTRL(PAD_CTL_SPEED_MED |
 121                                 PAD_CTL_DSE_40ohm |
 122                                 PAD_CTL_SRE_FAST),
 123         MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 124         MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 125         MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 126         MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 127         MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 128         MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 129         MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 130
 131         MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_CFG_SION |
 132                                 MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |
 133                                 PAD_CTL_DSE_48ohm |
 134                                 PAD_CTL_SRE_FAST),
 135         MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 136         MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 137         MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 138         MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 139         MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 140         MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 141         MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 142 };
 143
 144 #define TX6_I2C_PAD_CTRL        (PAD_CTL_PUS_22K_UP |   \
 145                                 PAD_CTL_SPEED_MED |     \
 146                                 PAD_CTL_DSE_34ohm |     \
 147                                 PAD_CTL_SRE_FAST)
 148
 149 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
 150         /* internal I2C */
 151         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
 152                         MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
 153         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
 154                         MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
 155 };
 156
 157 static const struct gpio const tx6ul_gpios[] = {
 158         /* These two entries are used to forcefully reinitialize the I2C bus */
 159         { TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
 160         { TX6UL_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
 161
 162         { TX6UL_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 163         { TX6UL_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 164         { TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
 165 };
 166
 167 #define GPIO_DR 0
 168 #define GPIO_DIR 4
 169 #define GPIO_PSR 8
 170
 171 static void tx6_i2c_recover(void)
 172 {
 173         int i;
 174         int bad = 0;
 175 #define SCL_BIT         (1 << (TX6UL_I2C1_SCL_GPIO % 32))
 176 #define SDA_BIT         (1 << (TX6UL_I2C1_SDA_GPIO % 32))
 177 #define I2C_GPIO_BASE   (GPIO1_BASE_ADDR + TX6UL_I2C1_SCL_GPIO / 32 * 0x4000)
 178
 179         if ((readl(I2C_GPIO_BASE + GPIO_PSR) &
 180                         (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
 181                 return;
 182
 183         debug("Clearing I2C bus\n");
 184         if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SCL_BIT)) {
 185                 printf("I2C SCL stuck LOW\n");
 186                 bad++;
 187
 188                 writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
 189                         I2C_GPIO_BASE + GPIO_DR);
 190                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
 191                         I2C_GPIO_BASE + GPIO_DIR);
 192         }
 193         if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)) {
 194                 printf("I2C SDA stuck LOW\n");
 195                 bad++;
 196
 197                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) & ~SDA_BIT,
 198                         I2C_GPIO_BASE + GPIO_DIR);
 199                 writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
 200                         I2C_GPIO_BASE + GPIO_DR);
 201                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
 202                         I2C_GPIO_BASE + GPIO_DIR);
 203
 204                 imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
 205                                                 ARRAY_SIZE(tx6_i2c_gpio_pads));
 206                 udelay(10);
 207
 208                 for (i = 0; i < 18; i++) {
 209                         u32 reg = readl(I2C_GPIO_BASE + GPIO_DR) ^ SCL_BIT;
 210
 211                         debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
 212                         writel(reg, I2C_GPIO_BASE + GPIO_DR);
 213                         udelay(10);
 214                         if (reg & SCL_BIT &&
 215                                 readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)
 216                                 break;
 217                 }
 218         }
 219         if (bad) {
 220                 u32 reg = readl(I2C_GPIO_BASE + GPIO_PSR);
 221
 222                 if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
 223                         printf("I2C bus recovery succeeded\n");
 224                 } else {
 225                         printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
 226                                 SCL_BIT | SDA_BIT);
 227                 }
 228         }
 229 }
 230
 231 /* placed in section '.data' to prevent overwriting relocation info
 232  * overlayed with bss
 233  */
 234 static u32 wrsr __data;
 235
 236 #define WRSR_POR                        (1 << 4)
 237 #define WRSR_TOUT                       (1 << 1)
 238 #define WRSR_SFTW                       (1 << 0)
 239
 240 static void print_reset_cause(void)
 241 {
 242         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 243         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 244         u32 srsr;
 245         char *dlm = "";
 246
 247         printf("Reset cause: ");
 248
 249         srsr = readl(&src_regs->srsr);
 250         wrsr = readw(wdt_base + 4);
 251
 252         if (wrsr & WRSR_POR) {
 253                 printf("%sPOR", dlm);
 254                 dlm = " | ";
 255         }
 256         if (srsr & 0x00004) {
 257                 printf("%sCSU", dlm);
 258                 dlm = " | ";
 259         }
 260         if (srsr & 0x00008) {
 261                 printf("%sIPP USER", dlm);
 262                 dlm = " | ";
 263         }
 264         if (srsr & 0x00010) {
 265                 if (wrsr & WRSR_SFTW) {
 266                         printf("%sSOFT", dlm);
 267                         dlm = " | ";
 268                 }
 269                 if (wrsr & WRSR_TOUT) {
 270                         printf("%sWDOG", dlm);
 271                         dlm = " | ";
 272                 }
 273         }
 274         if (srsr & 0x00020) {
 275                 printf("%sJTAG HIGH-Z", dlm);
 276                 dlm = " | ";
 277         }
 278         if (srsr & 0x00040) {
 279                 printf("%sJTAG SW", dlm);
 280                 dlm = " | ";
 281         }
 282         if (srsr & 0x10000) {
 283                 printf("%sWARM BOOT", dlm);
 284                 dlm = " | ";
 285         }
 286         if (dlm[0] == '\0')
 287                 printf("unknown");
 288
 289         printf("\n");
 290 }
 291
 292 #ifdef CONFIG_IMX6_THERMAL
 293 #include <thermal.h>
 294 #include <imx_thermal.h>
 295 #include <fuse.h>
 296
 297 static void print_temperature(void)
 298 {
 299         struct udevice *thermal_dev;
 300         int cpu_tmp, minc, maxc, ret;
 301         char const *grade_str;
 302         static u32 __data thermal_calib;
 303
 304         puts("Temperature: ");
 305         switch (get_cpu_temp_grade(&minc, &maxc)) {
 306         case TEMP_AUTOMOTIVE:
 307                 grade_str = "Automotive";
 308                 break;
 309         case TEMP_INDUSTRIAL:
 310                 grade_str = "Industrial";
 311                 break;
 312         case TEMP_EXTCOMMERCIAL:
 313                 grade_str = "Extended Commercial";
 314                 break;
 315         default:
 316                 grade_str = "Commercial";
 317         }
 318         printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
 319         ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
 320         if (ret == 0) {
 321                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
 322
 323                 if (ret == 0)
 324                         printf(" at %dC", cpu_tmp);
 325                 else
 326                         puts(" - failed to read sensor data");
 327         } else {
 328                 puts(" - no sensor device found");
 329         }
 330
 331         if (fuse_read(1, 6, &thermal_calib) == 0) {
 332                 printf(" - calibration data 0x%08x\n", thermal_calib);
 333         } else {
 334                 puts(" - Failed to read thermal calib fuse\n");
 335         }
 336 }
 337 #else
 338 static inline void print_temperature(void)
 339 {
 340 }
 341 #endif
 342
 343 int checkboard(void)
 344 {
 345         u32 cpurev = get_cpu_rev();
 346         char *cpu_str = "?";
 347
 348         switch ((cpurev >> 12) & 0xff) {
 349         case MXC_CPU_MX6SL:
 350                 cpu_str = "SL";
 351                 break;
 352         case MXC_CPU_MX6DL:
 353                 cpu_str = "DL";
 354                 break;
 355         case MXC_CPU_MX6SOLO:
 356                 cpu_str = "SOLO";
 357                 break;
 358         case MXC_CPU_MX6Q:
 359                 cpu_str = "Q";
 360                 break;
 361         case MXC_CPU_MX6UL:
 362                 cpu_str = "UL";
 363                 break;
 364         }
 365
 366         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
 367                 cpu_str,
 368                 (cpurev & 0x000F0) >> 4,
 369                 (cpurev & 0x0000F) >> 0,
 370                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 371
 372         print_temperature();
 373         print_reset_cause();
 374 #ifdef CONFIG_MX6_TEMPERATURE_HOT
 375         check_cpu_temperature(1);
 376 #endif
 377         tx6_i2c_recover();
 378         return 0;
 379 }
 380
 381 /* serial port not initialized at this point */
 382 int board_early_init_f(void)
 383 {
 384         return 0;
 385 }
 386
 387 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 388 static bool tx6_temp_check_enabled = true;
 389 #else
 390 #define tx6_temp_check_enabled  0
 391 #endif
 392
 393 static inline u8 tx6ul_mem_suffix(void)
 394 {
 395 #ifdef CONFIG_TX6_NAND
 396         return '0';
 397 #else
 398         return '1';
 399 #endif
 400 }
 401
 402 /* PMIC settings */
 403 #define VDD_RTC_VAL             rn5t_mV_to_regval_rtc(3000)
 404 #define VDD_CORE_VAL            rn5t_mV_to_regval(1300)         /* DCDC1 */
 405 #define VDD_CORE_VAL_LP         rn5t_mV_to_regval(900)
 406 #define VDD_DDR_VAL             rn5t_mV_to_regval(1350)         /* DCDC3 */
 407 #define VDD_DDR_VAL_LP          rn5t_mV_to_regval(1350)
 408 #define VDD_HIGH_VAL            rn5t_mV_to_regval(3300)         /* DCDC4 */
 409 #define VDD_HIGH_VAL_LP         rn5t_mV_to_regval(3300)
 410 #define VDD_CSI_VAL             rn5t_mV_to_regval2(3300)        /* LDO4 */
 411 #define VDD_CSI_VAL_LP          rn5t_mV_to_regval2(3300)
 412
 413 static struct pmic_regs rn5t567_regs[] = {
 414         { RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, },
 415         { RN5T567_DC2CTL, DC2_DC2DIS, },
 416         { RN5T567_DC1DAC, VDD_CORE_VAL, },
 417         { RN5T567_DC3DAC, VDD_DDR_VAL, },
 418         { RN5T567_DC4DAC, VDD_HIGH_VAL, },
 419         { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
 420         { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
 421         { RN5T567_DC4DAC_SLP, VDD_HIGH_VAL_LP, },
 422         { RN5T567_LDOEN1, 0x01f, ~0x1f, },
 423         { RN5T567_LDOEN2, 0x10, ~0x30, },
 424         { RN5T567_LDODIS, 0x00, },
 425         { RN5T567_LDO4DAC, VDD_CSI_VAL, },
 426         { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
 427         { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
 428 };
 429
 430 static int pmic_addr __maybe_unused = 0x33;
 431
 432 int board_init(void)
 433 {
 434         int ret;
 435
 436         debug("%s@%d: \n", __func__, __LINE__);
 437
 438         printf("Board: Ka-Ro TXUL-001%c\n",
 439                 tx6ul_mem_suffix());
 440
 441         get_hab_status();
 442
 443         ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios));
 444         if (ret < 0) {
 445                 printf("Failed to request tx6ul_gpios: %d\n", ret);
 446         }
 447         imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads));
 448
 449         /* Address of boot parameters */
 450         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 451         gd->bd->bi_arch_number = -1;
 452
 453         if (ctrlc() || (wrsr & WRSR_TOUT)) {
 454                 if (wrsr & WRSR_TOUT)
 455                         printf("WDOG RESET detected; Skipping PMIC setup\n");
 456                 else
 457                         printf("<CTRL-C> detected; safeboot enabled\n");
 458 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 459                 tx6_temp_check_enabled = false;
 460 #endif
 461                 return 0;
 462         }
 463
 464         ret = tx6_pmic_init(pmic_addr, rn5t567_regs, ARRAY_SIZE(rn5t567_regs));
 465         if (ret) {
 466                 printf("Failed to setup PMIC voltages: %d\n", ret);
 467                 hang();
 468         }
 469         return 0;
 470 }
 471
 472 int dram_init(void)
 473 {
 474         debug("%s@%d: \n", __func__, __LINE__);
 475
 476         /* dram_init must store complete ramsize in gd->ram_size */
 477         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 478                                 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
 479         return 0;
 480 }
 481
 482 void dram_init_banksize(void)
 483 {
 484         debug("%s@%d: \n", __func__, __LINE__);
 485
 486         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 487         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 488                         PHYS_SDRAM_1_SIZE);
 489 #if CONFIG_NR_DRAM_BANKS > 1
 490         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 491         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 492                         PHYS_SDRAM_2_SIZE);
 493 #endif
 494 }
 495
 496 #ifdef  CONFIG_FSL_ESDHC
 497 #define TX6_SD_PAD_CTRL         (PAD_CTL_PUS_47K_UP |   \
 498                                 PAD_CTL_SPEED_MED |     \
 499                                 PAD_CTL_DSE_40ohm |     \
 500                                 PAD_CTL_SRE_FAST)
 501
 502 static const iomux_v3_cfg_t mmc0_pads[] = {
 503         MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 504         MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 505         MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 506         MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 507         MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 508         MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 509         /* SD1 CD */
 510         MX6_PAD_NAND_CE1_B__GPIO4_IO14 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 511 };
 512
 513 #ifdef CONFIG_TX6_EMMC
 514 static const iomux_v3_cfg_t mmc1_pads[] = {
 515         MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 516         MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 517         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 518         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 519         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 520         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 521         /* eMMC RESET */
 522         MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
 523                                                 PAD_CTL_DSE_40ohm),
 524 };
 525 #endif
 526
 527 static struct tx6_esdhc_cfg {
 528         const iomux_v3_cfg_t *pads;
 529         int num_pads;
 530         enum mxc_clock clkid;
 531         struct fsl_esdhc_cfg cfg;
 532         int cd_gpio;
 533 } tx6ul_esdhc_cfg[] = {
 534 #ifdef CONFIG_TX6_EMMC
 535         {
 536                 .pads = mmc1_pads,
 537                 .num_pads = ARRAY_SIZE(mmc1_pads),
 538                 .clkid = MXC_ESDHC2_CLK,
 539                 .cfg = {
 540                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
 541                         .max_bus_width = 4,
 542                 },
 543                 .cd_gpio = -EINVAL,
 544         },
 545 #endif
 546         {
 547                 .pads = mmc0_pads,
 548                 .num_pads = ARRAY_SIZE(mmc0_pads),
 549                 .clkid = MXC_ESDHC_CLK,
 550                 .cfg = {
 551                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
 552                         .max_bus_width = 4,
 553                 },
 554                 .cd_gpio = TX6UL_SD1_CD_GPIO,
 555         },
 556 };
 557
 558 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 559 {
 560         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
 561 }
 562
 563 int board_mmc_getcd(struct mmc *mmc)
 564 {
 565         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
 566
 567         if (cfg->cd_gpio < 0)
 568                 return 1;
 569
 570         debug("SD card %d is %spresent (GPIO %d)\n",
 571                 cfg - tx6ul_esdhc_cfg,
 572                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
 573                 cfg->cd_gpio);
 574         return !gpio_get_value(cfg->cd_gpio);
 575 }
 576
 577 int board_mmc_init(bd_t *bis)
 578 {
 579         int i;
 580
 581         debug("%s@%d: \n", __func__, __LINE__);
 582
 583         for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) {
 584                 struct mmc *mmc;
 585                 struct tx6_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
 586                 int ret;
 587
 588                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
 589                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
 590
 591                 if (cfg->cd_gpio >= 0) {
 592                         ret = gpio_request_one(cfg->cd_gpio,
 593                                         GPIOFLAG_INPUT, "MMC CD");
 594                         if (ret) {
 595                                 printf("Error %d requesting GPIO%d_%d\n",
 596                                         ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 597                                 continue;
 598                         }
 599                 }
 600
 601                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 602                 fsl_esdhc_initialize(bis, &cfg->cfg);
 603
 604                 mmc = find_mmc_device(i);
 605                 if (mmc == NULL)
 606                         continue;
 607                 if (board_mmc_getcd(mmc))
 608                         mmc_init(mmc);
 609         }
 610         return 0;
 611 }
 612 #endif /* CONFIG_CMD_MMC */
 613
 614 #ifdef CONFIG_FEC_MXC
 615
 616 #ifndef ETH_ALEN
 617 #define ETH_ALEN 6
 618 #endif
 619
 620 int board_eth_init(bd_t *bis)
 621 {
 622         int ret;
 623
 624         debug("%s@%d: \n", __func__, __LINE__);
 625
 626         /* delay at least 21ms for the PHY internal POR signal to deassert */
 627         udelay(22000);
 628
 629         imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads,
 630                                         ARRAY_SIZE(tx6ul_enet1_pads));
 631
 632         /* Deassert RESET to the external phy */
 633         gpio_set_value(TX6UL_FEC_RST_GPIO, 1);
 634
 635         if (getenv("ethaddr")) {
 636                 ret = fecmxc_initialize_multi(bis, 0, -1, ENET_BASE_ADDR);
 637                 if (ret) {
 638                         printf("failed to initialize FEC0: %d\n", ret);
 639                         return ret;
 640                 }
 641         }
 642         if (getenv("eth1addr")) {
 643                 ret = fecmxc_initialize_multi(bis, 1, -1, ENET2_BASE_ADDR);
 644                 if (ret) {
 645                         printf("failed to initialize FEC1: %d\n", ret);
 646                         return ret;
 647                 }
 648         }
 649         return 0;
 650 }
 651
 652 static void tx6_init_mac(void)
 653 {
 654         u8 mac[ETH_ALEN];
 655
 656         imx_get_mac_from_fuse(0, mac);
 657         if (!is_valid_ethaddr(mac)) {
 658                 printf("No valid MAC address programmed\n");
 659                 return;
 660         }
 661
 662         printf("MAC addr from fuse: %pM\n", mac);
 663         eth_setenv_enetaddr("ethaddr", mac);
 664
 665         imx_get_mac_from_fuse(1, mac);
 666         eth_setenv_enetaddr("eth1addr", mac);
 667 }
 668 #else
 669 static inline void tx6_init_mac(void)
 670 {
 671 }
 672 #endif /* CONFIG_FEC_MXC */
 673
 674 enum {
 675         LED_STATE_INIT = -1,
 676         LED_STATE_OFF,
 677         LED_STATE_ON,
 678         LED_STATE_ERR,
 679 };
 680
 681 static inline int calc_blink_rate(void)
 682 {
 683         if (!tx6_temp_check_enabled)
 684                 return CONFIG_SYS_HZ;
 685
 686         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
 687                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
 688                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
 689 }
 690
 691 void show_activity(int arg)
 692 {
 693         static int led_state = LED_STATE_INIT;
 694         static int blink_rate;
 695         static ulong last;
 696         int ret;
 697
 698         switch (led_state) {
 699         case LED_STATE_ERR:
 700                 return;
 701
 702         case LED_STATE_INIT:
 703                 last = get_timer(0);
 704                 ret = gpio_set_value(TX6UL_LED_GPIO, 1);
 705                 if (ret)
 706                         led_state = LED_STATE_ERR;
 707                 else
 708                         led_state = LED_STATE_ON;
 709                 blink_rate = calc_blink_rate();
 710                 break;
 711
 712         case LED_STATE_ON:
 713         case LED_STATE_OFF:
 714                 if (get_timer(last) > blink_rate) {
 715                         blink_rate = calc_blink_rate();
 716                         last = get_timer_masked();
 717                         if (led_state == LED_STATE_ON) {
 718                                 gpio_set_value(TX6UL_LED_GPIO, 0);
 719                         } else {
 720                                 gpio_set_value(TX6UL_LED_GPIO, 1);
 721                         }
 722                         led_state = 1 - led_state;
 723                 }
 724                 break;
 725         }
 726 }
 727
 728 static const iomux_v3_cfg_t stk5_pads[] = {
 729         /* SW controlled LED on STK5 baseboard */
 730         MX6_PAD_SNVS_TAMPER9__GPIO5_IO09,
 731
 732         /* I2C bus on DIMM pins 40/41 */
 733         MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
 734         MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
 735
 736         /* TSC200x PEN IRQ */
 737         MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL),
 738 #if 0
 739         /* EDT-FT5x06 Polytouch panel */
 740         MX6_PAD_NAND_CS2__GPIO6_IO15 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* IRQ */
 741         MX6_PAD_EIM_A16__GPIO2_IO22 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* RESET */
 742         MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* WAKE */
 743
 744         /* USBH1 */
 745         MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
 746         MX6_PAD_EIM_D30__GPIO3_IO30 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
 747         /* USBOTG */
 748         MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* USBOTG ID */
 749         MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
 750         MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
 751 #endif
 752 };
 753
 754 static const struct gpio stk5_gpios[] = {
 755         { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 756
 757         { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
 758         { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
 759         { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 760         { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
 761         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 762 };
 763
 764 #ifdef CONFIG_LCD
 765 static u16 tx6_cmap[256];
 766 vidinfo_t panel_info = {
 767         /* set to max. size supported by SoC */
 768         .vl_col = 4096,
 769         .vl_row = 1024,
 770
 771         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 772         .cmap = tx6_cmap,
 773 };
 774
 775 static struct fb_videomode tx6_fb_modes[] = {
 776 #ifndef CONFIG_SYS_LVDS_IF
 777         {
 778                 /* Standard VGA timing */
 779                 .name           = "VGA",
 780                 .refresh        = 60,
 781                 .xres           = 640,
 782                 .yres           = 480,
 783                 .pixclock       = KHZ2PICOS(25175),
 784                 .left_margin    = 48,
 785                 .hsync_len      = 96,
 786                 .right_margin   = 16,
 787                 .upper_margin   = 31,
 788                 .vsync_len      = 2,
 789                 .lower_margin   = 12,
 790                 .sync           = FB_SYNC_CLK_LAT_FALL,
 791         },
 792         {
 793                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 794                  * DE high active, 115.2 mm x 86.4 mm display area
 795                  * VGA compatible timing
 796                  */
 797                 .name           = "ETV570",
 798                 .refresh        = 60,
 799                 .xres           = 640,
 800                 .yres           = 480,
 801                 .pixclock       = KHZ2PICOS(25175),
 802                 .left_margin    = 114,
 803                 .hsync_len      = 30,
 804                 .right_margin   = 16,
 805                 .upper_margin   = 32,
 806                 .vsync_len      = 3,
 807                 .lower_margin   = 10,
 808                 .sync           = FB_SYNC_CLK_LAT_FALL,
 809         },
 810         {
 811                 /* Emerging ET0350G0DH6 320 x 240 display.
 812                  * 70.08 mm x 52.56 mm display area.
 813                  */
 814                 .name           = "ET0350",
 815                 .refresh        = 60,
 816                 .xres           = 320,
 817                 .yres           = 240,
 818                 .pixclock       = KHZ2PICOS(6500),
 819                 .left_margin    = 68 - 34,
 820                 .hsync_len      = 34,
 821                 .right_margin   = 20,
 822                 .upper_margin   = 18 - 3,
 823                 .vsync_len      = 3,
 824                 .lower_margin   = 4,
 825                 .sync           = FB_SYNC_CLK_LAT_FALL,
 826         },
 827         {
 828                 /* Emerging ET0430G0DH6 480 x 272 display.
 829                  * 95.04 mm x 53.856 mm display area.
 830                  */
 831                 .name           = "ET0430",
 832                 .refresh        = 60,
 833                 .xres           = 480,
 834                 .yres           = 272,
 835                 .pixclock       = KHZ2PICOS(9000),
 836                 .left_margin    = 2,
 837                 .hsync_len      = 41,
 838                 .right_margin   = 2,
 839                 .upper_margin   = 2,
 840                 .vsync_len      = 10,
 841                 .lower_margin   = 2,
 842         },
 843         {
 844                 /* Emerging ET0500G0DH6 800 x 480 display.
 845                  * 109.6 mm x 66.4 mm display area.
 846                  */
 847                 .name           = "ET0500",
 848                 .refresh        = 60,
 849                 .xres           = 800,
 850                 .yres           = 480,
 851                 .pixclock       = KHZ2PICOS(33260),
 852                 .left_margin    = 216 - 128,
 853                 .hsync_len      = 128,
 854                 .right_margin   = 1056 - 800 - 216,
 855                 .upper_margin   = 35 - 2,
 856                 .vsync_len      = 2,
 857                 .lower_margin   = 525 - 480 - 35,
 858                 .sync           = FB_SYNC_CLK_LAT_FALL,
 859         },
 860         {
 861                 /* Emerging ETQ570G0DH6 320 x 240 display.
 862                  * 115.2 mm x 86.4 mm display area.
 863                  */
 864                 .name           = "ETQ570",
 865                 .refresh        = 60,
 866                 .xres           = 320,
 867                 .yres           = 240,
 868                 .pixclock       = KHZ2PICOS(6400),
 869                 .left_margin    = 38,
 870                 .hsync_len      = 30,
 871                 .right_margin   = 30,
 872                 .upper_margin   = 16, /* 15 according to datasheet */
 873                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 874                 .lower_margin   = 4, /* 4.5 according to datasheet */
 875                 .sync           = FB_SYNC_CLK_LAT_FALL,
 876         },
 877         {
 878                 /* Emerging ET0700G0DH6 800 x 480 display.
 879                  * 152.4 mm x 91.44 mm display area.
 880                  */
 881                 .name           = "ET0700",
 882                 .refresh        = 60,
 883                 .xres           = 800,
 884                 .yres           = 480,
 885                 .pixclock       = KHZ2PICOS(33260),
 886                 .left_margin    = 216 - 128,
 887                 .hsync_len      = 128,
 888                 .right_margin   = 1056 - 800 - 216,
 889                 .upper_margin   = 35 - 2,
 890                 .vsync_len      = 2,
 891                 .lower_margin   = 525 - 480 - 35,
 892                 .sync           = FB_SYNC_CLK_LAT_FALL,
 893         },
 894         {
 895                 /* Emerging ET070001DM6 800 x 480 display.
 896                  * 152.4 mm x 91.44 mm display area.
 897                  */
 898                 .name           = "ET070001DM6",
 899                 .refresh        = 60,
 900                 .xres           = 800,
 901                 .yres           = 480,
 902                 .pixclock       = KHZ2PICOS(33260),
 903                 .left_margin    = 216 - 128,
 904                 .hsync_len      = 128,
 905                 .right_margin   = 1056 - 800 - 216,
 906                 .upper_margin   = 35 - 2,
 907                 .vsync_len      = 2,
 908                 .lower_margin   = 525 - 480 - 35,
 909                 .sync           = 0,
 910         },
 911 #else
 912         {
 913                 /* HannStar HSD100PXN1
 914                  * 202.7m mm x 152.06 mm display area.
 915                  */
 916                 .name           = "HSD100PXN1",
 917                 .refresh        = 60,
 918                 .xres           = 1024,
 919                 .yres           = 768,
 920                 .pixclock       = KHZ2PICOS(65000),
 921                 .left_margin    = 0,
 922                 .hsync_len      = 0,
 923                 .right_margin   = 320,
 924                 .upper_margin   = 0,
 925                 .vsync_len      = 0,
 926                 .lower_margin   = 38,
 927                 .sync           = FB_SYNC_CLK_LAT_FALL,
 928         },
 929 #endif
 930         {
 931                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 932                 .refresh        = 60,
 933                 .left_margin    = 48,
 934                 .hsync_len      = 96,
 935                 .right_margin   = 16,
 936                 .upper_margin   = 31,
 937                 .vsync_len      = 2,
 938                 .lower_margin   = 12,
 939                 .sync           = FB_SYNC_CLK_LAT_FALL,
 940         },
 941 };
 942
 943 static int lcd_enabled = 1;
 944 static int lcd_bl_polarity;
 945
 946 static int lcd_backlight_polarity(void)
 947 {
 948         return lcd_bl_polarity;
 949 }
 950
 951 void lcd_enable(void)
 952 {
 953         /* HACK ALERT:
 954          * global variable from common/lcd.c
 955          * Set to 0 here to prevent messages from going to LCD
 956          * rather than serial console
 957          */
 958         lcd_is_enabled = 0;
 959
 960         if (lcd_enabled) {
 961                 karo_load_splashimage(1);
 962
 963                 debug("Switching LCD on\n");
 964                 gpio_set_value(TX6UL_LCD_PWR_GPIO, 1);
 965                 udelay(100);
 966                 gpio_set_value(TX6UL_LCD_RST_GPIO, 1);
 967                 udelay(300000);
 968                 gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
 969                         lcd_backlight_polarity());
 970         }
 971 }
 972
 973 void lcd_disable(void)
 974 {
 975         if (lcd_enabled) {
 976                 printf("Disabling LCD\n");
 977                 panel_info.vl_row = 0;
 978                 lcd_enabled = 0;
 979         }
 980 }
 981
 982 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 983 #if 1
 984         /* LCD RESET */
 985         MX6_PAD_LCD_RESET__LCDIF_RESET,
 986         /* LCD POWER_ENABLE */
 987         MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
 988         /* LCD Backlight (PWM) */
 989         MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
 990 #endif
 991 #ifdef CONFIG_LCD
 992         /* Display */
 993         MX6_PAD_LCD_DATA00__LCDIF_DATA00,
 994         MX6_PAD_LCD_DATA01__LCDIF_DATA01,
 995         MX6_PAD_LCD_DATA02__LCDIF_DATA02,
 996         MX6_PAD_LCD_DATA03__LCDIF_DATA03,
 997         MX6_PAD_LCD_DATA04__LCDIF_DATA04,
 998         MX6_PAD_LCD_DATA05__LCDIF_DATA05,
 999         MX6_PAD_LCD_DATA06__LCDIF_DATA06,
1000         MX6_PAD_LCD_DATA07__LCDIF_DATA07,
1001         MX6_PAD_LCD_DATA08__LCDIF_DATA08,
1002         MX6_PAD_LCD_DATA09__LCDIF_DATA09,
1003         MX6_PAD_LCD_DATA10__LCDIF_DATA10,
1004         MX6_PAD_LCD_DATA11__LCDIF_DATA11,
1005         MX6_PAD_LCD_DATA12__LCDIF_DATA12,
1006         MX6_PAD_LCD_DATA13__LCDIF_DATA13,
1007         MX6_PAD_LCD_DATA14__LCDIF_DATA14,
1008         MX6_PAD_LCD_DATA15__LCDIF_DATA15,
1009         MX6_PAD_LCD_DATA16__LCDIF_DATA16,
1010         MX6_PAD_LCD_DATA17__LCDIF_DATA17,
1011         MX6_PAD_LCD_DATA18__LCDIF_DATA18,
1012         MX6_PAD_LCD_DATA19__LCDIF_DATA19,
1013         MX6_PAD_LCD_DATA20__LCDIF_DATA20,
1014         MX6_PAD_LCD_DATA21__LCDIF_DATA21,
1015         MX6_PAD_LCD_DATA22__LCDIF_DATA22,
1016         MX6_PAD_LCD_DATA23__LCDIF_DATA23,
1017         MX6_PAD_LCD_HSYNC__LCDIF_HSYNC, /* HSYNC */
1018         MX6_PAD_LCD_VSYNC__LCDIF_VSYNC, /* VSYNC */
1019         MX6_PAD_LCD_ENABLE__LCDIF_ENABLE, /* OE_ACD */
1020         MX6_PAD_LCD_CLK__LCDIF_CLK, /* LSCLK */
1021 #endif
1022 };
1023
1024 static const struct gpio stk5_lcd_gpios[] = {
1025         { TX6UL_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1026         { TX6UL_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1027         { TX6UL_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1028 };
1029
1030 void lcd_ctrl_init(void *lcdbase)
1031 {
1032         int color_depth = 24;
1033         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1034         const char *vm;
1035         unsigned long val;
1036         int refresh = 60;
1037         struct fb_videomode *p = &tx6_fb_modes[0];
1038         struct fb_videomode fb_mode;
1039         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1040
1041         if (!lcd_enabled) {
1042                 debug("LCD disabled\n");
1043                 return;
1044         }
1045
1046         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1047                 lcd_disable();
1048                 setenv("splashimage", NULL);
1049                 return;
1050         }
1051
1052         karo_fdt_move_fdt();
1053         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1054
1055         if (video_mode == NULL) {
1056                 lcd_disable();
1057                 return;
1058         }
1059         vm = video_mode;
1060         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1061                 p = &fb_mode;
1062                 debug("Using video mode from FDT\n");
1063                 vm += strlen(vm);
1064                 if (fb_mode.xres > panel_info.vl_col ||
1065                         fb_mode.yres > panel_info.vl_row) {
1066                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1067                                 fb_mode.xres, fb_mode.yres,
1068                                 panel_info.vl_col, panel_info.vl_row);
1069                         lcd_enabled = 0;
1070                         return;
1071                 }
1072         }
1073         if (p->name != NULL)
1074                 debug("Trying compiled-in video modes\n");
1075         while (p->name != NULL) {
1076                 if (strcmp(p->name, vm) == 0) {
1077                         debug("Using video mode: '%s'\n", p->name);
1078                         vm += strlen(vm);
1079                         break;
1080                 }
1081                 p++;
1082         }
1083         if (*vm != '\0')
1084                 debug("Trying to decode video_mode: '%s'\n", vm);
1085         while (*vm != '\0') {
1086                 if (*vm >= '0' && *vm <= '9') {
1087                         char *end;
1088
1089                         val = simple_strtoul(vm, &end, 0);
1090                         if (end > vm) {
1091                                 if (!xres_set) {
1092                                         if (val > panel_info.vl_col)
1093                                                 val = panel_info.vl_col;
1094                                         p->xres = val;
1095                                         panel_info.vl_col = val;
1096                                         xres_set = 1;
1097                                 } else if (!yres_set) {
1098                                         if (val > panel_info.vl_row)
1099                                                 val = panel_info.vl_row;
1100                                         p->yres = val;
1101                                         panel_info.vl_row = val;
1102                                         yres_set = 1;
1103                                 } else if (!bpp_set) {
1104                                         switch (val) {
1105                                         case 8:
1106                                         case 16:
1107                                         case 18:
1108                                         case 24:
1109                                         case 32:
1110                                                 color_depth = val;
1111                                                 break;
1112
1113                                         default:
1114                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1115                                                         end - vm, vm, color_depth);
1116                                         }
1117                                         bpp_set = 1;
1118                                 } else if (!refresh_set) {
1119                                         refresh = val;
1120                                         refresh_set = 1;
1121                                 }
1122                         }
1123                         vm = end;
1124                 }
1125                 switch (*vm) {
1126                 case '@':
1127                         bpp_set = 1;
1128                         /* fallthru */
1129                 case '-':
1130                         yres_set = 1;
1131                         /* fallthru */
1132                 case 'x':
1133                         xres_set = 1;
1134                         /* fallthru */
1135                 case 'M':
1136                 case 'R':
1137                         vm++;
1138                         break;
1139
1140                 default:
1141                         if (*vm != '\0')
1142                                 vm++;
1143                 }
1144         }
1145         if (p->xres == 0 || p->yres == 0) {
1146                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1147                 lcd_enabled = 0;
1148                 printf("Supported video modes are:");
1149                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1150                         printf(" %s", p->name);
1151                 }
1152                 printf("\n");
1153                 return;
1154         }
1155         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1156                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1157                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1158                 lcd_enabled = 0;
1159                 return;
1160         }
1161         panel_info.vl_col = p->xres;
1162         panel_info.vl_row = p->yres;
1163
1164         switch (color_depth) {
1165         case 8:
1166                 panel_info.vl_bpix = LCD_COLOR8;
1167                 break;
1168         case 16:
1169                 panel_info.vl_bpix = LCD_COLOR16;
1170                 break;
1171         default:
1172                 panel_info.vl_bpix = LCD_COLOR32;
1173         }
1174
1175         p->pixclock = KHZ2PICOS(refresh *
1176                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1177                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1178                                 1000);
1179         debug("Pixel clock set to %lu.%03lu MHz\n",
1180                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1181
1182         if (p != &fb_mode) {
1183                 int ret;
1184
1185                 debug("Creating new display-timing node from '%s'\n",
1186                         video_mode);
1187                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1188                 if (ret)
1189                         printf("Failed to create new display-timing node from '%s': %d\n",
1190                                 video_mode, ret);
1191         }
1192
1193         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1194         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1195                                         ARRAY_SIZE(stk5_lcd_pads));
1196
1197         debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
1198                 color_depth, refresh);
1199
1200         if (karo_load_splashimage(0) == 0) {
1201                 char vmode[128];
1202
1203                 /* setup env variable for mxsfb display driver */
1204                 snprintf(vmode, sizeof(vmode),
1205                         "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
1206                         p->xres, p->yres, p->left_margin, p->right_margin,
1207                         p->upper_margin, p->lower_margin, p->hsync_len,
1208                         p->vsync_len, p->sync, p->pixclock, color_depth);
1209                 setenv("videomode", vmode);
1210
1211                 debug("Initializing LCD controller\n");
1212                 lcdif_clk_enable();
1213                 video_hw_init();
1214                 setenv("videomode", NULL);
1215         } else {
1216                 debug("Skipping initialization of LCD controller\n");
1217         }
1218 }
1219 #else
1220 #define lcd_enabled 0
1221 #endif /* CONFIG_LCD */
1222
1223 static void stk5_board_init(void)
1224 {
1225         int ret;
1226
1227         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1228         if (ret < 0) {
1229                 printf("Failed to request stk5_gpios: %d\n", ret);
1230                 return;
1231         }
1232         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1233         debug("%s@%d: \n", __func__, __LINE__);
1234 }
1235
1236 static void stk5v3_board_init(void)
1237 {
1238         debug("%s@%d: \n", __func__, __LINE__);
1239         stk5_board_init();
1240         debug("%s@%d: \n", __func__, __LINE__);
1241 }
1242
1243 static void stk5v5_board_init(void)
1244 {
1245         int ret;
1246
1247         stk5_board_init();
1248
1249         ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
1250                         "Flexcan Transceiver");
1251         if (ret) {
1252                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1253                 return;
1254         }
1255
1256         imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 |
1257                         MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL));
1258 }
1259
1260 static void tx6ul_set_cpu_clock(void)
1261 {
1262         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1263
1264         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1265                 return;
1266
1267         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1268                 printf("%s detected; skipping cpu clock change\n",
1269                         (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1270                 return;
1271         }
1272         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1273                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1274                 printf("CPU clock set to %lu.%03lu MHz\n",
1275                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1276         } else {
1277                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1278         }
1279 }
1280
1281 int board_late_init(void)
1282 {
1283         int ret = 0;
1284         const char *baseboard;
1285
1286         debug("%s@%d: \n", __func__, __LINE__);
1287
1288         env_cleanup();
1289
1290         if (tx6_temp_check_enabled)
1291                 check_cpu_temperature(1);
1292
1293         tx6ul_set_cpu_clock();
1294
1295         if (had_ctrlc())
1296                 setenv_ulong("safeboot", 1);
1297         else if (wrsr & WRSR_TOUT)
1298                 setenv_ulong("wdreset", 1);
1299         else
1300                 karo_fdt_move_fdt();
1301
1302         baseboard = getenv("baseboard");
1303         if (!baseboard)
1304                 goto exit;
1305
1306         printf("Baseboard: %s\n", baseboard);
1307
1308         if (strncmp(baseboard, "stk5", 4) == 0) {
1309                 if ((strlen(baseboard) == 4) ||
1310                         strcmp(baseboard, "stk5-v3") == 0) {
1311                         stk5v3_board_init();
1312                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1313                         const char *otg_mode = getenv("otg_mode");
1314
1315                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1316                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1317                                         otg_mode, baseboard);
1318                                 setenv("otg_mode", "none");
1319                         }
1320                         stk5v5_board_init();
1321                 } else {
1322                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1323                                 baseboard + 4);
1324                 }
1325         } else {
1326                 printf("WARNING: Unsupported baseboard: '%s'\n",
1327                         baseboard);
1328                 ret = -EINVAL;
1329         }
1330
1331 exit:
1332         debug("%s@%d: \n", __func__, __LINE__);
1333         tx6_init_mac();
1334         debug("%s@%d: \n", __func__, __LINE__);
1335
1336         clear_ctrlc();
1337         return ret;
1338 }
1339
1340 #ifdef CONFIG_SERIAL_TAG
1341 void get_board_serial(struct tag_serialnr *serialnr)
1342 {
1343         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1344         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1345
1346         serialnr->low = readl(&fuse->cfg0);
1347         serialnr->high = readl(&fuse->cfg1);
1348 }
1349 #endif
1350
1351 #if defined(CONFIG_OF_BOARD_SETUP)
1352 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1353 #include <jffs2/jffs2.h>
1354 #include <mtd_node.h>
1355 static struct node_info nodes[] = {
1356         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1357 };
1358 #else
1359 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1360 #endif
1361
1362 static const char *tx6_touchpanels[] = {
1363         "ti,tsc2007",
1364         "edt,edt-ft5x06",
1365         "eeti,egalax_ts",
1366 };
1367
1368 int ft_board_setup(void *blob, bd_t *bd)
1369 {
1370         const char *baseboard = getenv("baseboard");
1371         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1372         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1373         int ret;
1374
1375         ret = fdt_increase_size(blob, 4096);
1376         if (ret) {
1377                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1378                 return ret;
1379         }
1380         if (stk5_v5)
1381                 karo_fdt_enable_node(blob, "stk5led", 0);
1382
1383         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1384
1385         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1386                                 ARRAY_SIZE(tx6_touchpanels));
1387         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1388         karo_fdt_fixup_flexcan(blob, stk5_v5);
1389
1390         karo_fdt_update_fb_mode(blob, video_mode);
1391
1392         return 0;
1393 }
1394 #endif /* CONFIG_OF_BOARD_SETUP */