board/karo/tx6/tx6ul.c

   1 /*
   2  * Copyright (C) 2015 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  *
   6  */
   7 #include <common.h>
   8 #include <errno.h>
   9 #include <libfdt.h>
  10 #include <fdt_support.h>
  11 #include <lcd.h>
  12 #include <netdev.h>
  13 #include <mmc.h>
  14 #include <fsl_esdhc.h>
  15 #include <video_fb.h>
  16 #include <ipu.h>
  17 #include <mxcfb.h>
  18 #include <i2c.h>
  19 #include <linux/fb.h>
  20 #include <asm/io.h>
  21 #include <asm/gpio.h>
  22 #include <asm/arch/mx6-pins.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/hab.h>
  25 #include <asm/arch/imx-regs.h>
  26 #include <asm/arch/crm_regs.h>
  27 #include <asm/arch/sys_proto.h>
  28
  29 #include "../common/karo.h"
  30 #include "pmic.h"
  31
  32 #define __data __attribute__((section(".data")))
  33
  34 #define TX6UL_FEC_RST_GPIO              IMX_GPIO_NR(5, 6)
  35 #define TX6UL_FEC_PWR_GPIO              IMX_GPIO_NR(5, 7)
  36 #define TX6UL_FEC_INT_GPIO              IMX_GPIO_NR(5, 5)
  37
  38 #define TX6UL_FEC2_RST_GPIO             IMX_GPIO_NR(4, 28)
  39 #define TX6UL_FEC2_INT_GPIO             IMX_GPIO_NR(4, 27)
  40
  41 #define TX6UL_LED_GPIO                  IMX_GPIO_NR(5, 9)
  42
  43 #define TX6UL_LCD_PWR_GPIO              IMX_GPIO_NR(5, 4)
  44 #define TX6UL_LCD_RST_GPIO              IMX_GPIO_NR(3, 4)
  45 #define TX6UL_LCD_BACKLIGHT_GPIO        IMX_GPIO_NR(4, 16)
  46
  47 #ifdef CONFIG_SYS_I2C_SOFT
  48 #define TX6UL_I2C1_SCL_GPIO             CONFIG_SOFT_I2C_GPIO_SCL
  49 #define TX6UL_I2C1_SDA_GPIO             CONFIG_SOFT_I2C_GPIO_SDA
  50 #endif
  51
  52 #define TX6UL_SD1_CD_GPIO               IMX_GPIO_NR(4, 14)
  53
  54 #ifdef CONFIG_MX6_TEMPERATURE_MIN
  55 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
  56 #else
  57 #define TEMPERATURE_MIN                 (-40)
  58 #endif
  59 #ifdef CONFIG_MX6_TEMPERATURE_HOT
  60 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
  61 #else
  62 #define TEMPERATURE_HOT                 80
  63 #endif
  64
  65 DECLARE_GLOBAL_DATA_PTR;
  66
  67 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  68
  69 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
  70 #ifdef CONFIG_SECURE_BOOT
  71 char __csf_data[0] __attribute__((section(".__csf_data")));
  72 #endif
  73
  74 #define TX6UL_DEFAULT_PAD_CTRL  MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |      \
  75                                         PAD_CTL_SPEED_MED |             \
  76                                         PAD_CTL_DSE_40ohm |             \
  77                                         PAD_CTL_SRE_FAST)
  78 #define TX6UL_I2C_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |       \
  79                                         PAD_CTL_ODE |                   \
  80                                         PAD_CTL_HYS |                   \
  81                                         PAD_CTL_SPEED_LOW |             \
  82                                         PAD_CTL_DSE_34ohm |             \
  83                                         PAD_CTL_SRE_FAST)
  84 #define TX6UL_I2C_GPIO_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |       \
  85                                         PAD_CTL_HYS |                   \
  86                                         PAD_CTL_DSE_34ohm |             \
  87                                         PAD_CTL_SPEED_MED)
  88 #define TX6UL_ENET_PAD_CTRL     MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |       \
  89                                         PAD_CTL_DSE_48ohm |             \
  90                                         PAD_CTL_PUS_100K_UP |           \
  91                                         PAD_CTL_SRE_FAST)
  92 #define TX6UL_GPIO_OUT_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |        \
  93                                         PAD_CTL_DSE_60ohm |             \
  94                                         PAD_CTL_SRE_SLOW)
  95 #define TX6UL_GPIO_IN_PAD_CTRL  MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |        \
  96                                         PAD_CTL_PUS_47K_UP)
  97
  98
  99 static const iomux_v3_cfg_t const tx6ul_pads[] = {
 100         /* UART pads */
 101 #if CONFIG_MXC_UART_BASE == UART1_BASE
 102         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
 103         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
 104         MX6_PAD_UART1_RTS_B__UART1_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
 105         MX6_PAD_UART1_CTS_B__UART1_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
 106 #endif
 107 #if CONFIG_MXC_UART_BASE == UART2_BASE
 108         MX6_PAD_UART2_TX_DATA__UART2_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
 109         MX6_PAD_UART2_RX_DATA__UART2_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
 110         MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
 111         MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
 112 #endif
 113 #if CONFIG_MXC_UART_BASE == UART5_BASE
 114         MX6_PAD_GPIO1_IO04__UART5_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
 115         MX6_PAD_GPIO1_IO05__UART5_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
 116         MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
 117         MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
 118 #endif
 119         /* FEC PHY GPIO functions */
 120         MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY POWER */
 121         MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY RESET */
 122         MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | TX6UL_GPIO_IN_PAD_CTRL, /* PHY INT */
 123 };
 124
 125 static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = {
 126         /* FEC functions */
 127         MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_48ohm |
 128                                                      PAD_CTL_SPEED_MED),
 129         MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
 130                                                       PAD_CTL_DSE_48ohm |
 131                                                       PAD_CTL_SPEED_MED),
 132         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_CFG_SION |
 133                                         MUX_PAD_CTRL(PAD_CTL_SPEED_MED |
 134                                                      PAD_CTL_DSE_40ohm |
 135                                                      PAD_CTL_SRE_FAST),
 136         MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | TX6UL_ENET_PAD_CTRL,
 137         MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | TX6UL_ENET_PAD_CTRL,
 138         MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | TX6UL_ENET_PAD_CTRL,
 139         MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | TX6UL_ENET_PAD_CTRL,
 140         MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | TX6UL_ENET_PAD_CTRL,
 141         MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | TX6UL_ENET_PAD_CTRL,
 142         MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | TX6UL_ENET_PAD_CTRL,
 143 };
 144
 145 static const iomux_v3_cfg_t const tx6ul_enet2_pads[] = {
 146         MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_CFG_SION |
 147                                         MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |
 148                                                      PAD_CTL_DSE_48ohm |
 149                                                      PAD_CTL_SRE_FAST),
 150         MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | TX6UL_ENET_PAD_CTRL,
 151         MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | TX6UL_ENET_PAD_CTRL,
 152         MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | TX6UL_ENET_PAD_CTRL,
 153         MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | TX6UL_ENET_PAD_CTRL,
 154         MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | TX6UL_ENET_PAD_CTRL,
 155         MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | TX6UL_ENET_PAD_CTRL,
 156         MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | TX6UL_ENET_PAD_CTRL,
 157 };
 158
 159 static const iomux_v3_cfg_t const tx6ul_i2c_pads[] = {
 160         /* internal I2C */
 161         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
 162                         TX6UL_I2C_PAD_CTRL, /* I2C SCL */
 163         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
 164                         TX6UL_I2C_PAD_CTRL, /* I2C SDA */
 165 };
 166
 167 static const iomux_v3_cfg_t const tx6ul_i2c_gpio_pads[] = {
 168         /* internal I2C set up for I2C bus recovery */
 169         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
 170                         TX6UL_I2C_PAD_CTRL, /* I2C SCL */
 171         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
 172                         TX6UL_I2C_PAD_CTRL, /* I2C SDA */
 173 };
 174
 175 static const struct gpio const tx6ul_gpios[] = {
 176 #ifdef CONFIG_SYS_I2C_SOFT
 177         /* These two entries are used to forcefully reinitialize the I2C bus */
 178         { TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
 179         { TX6UL_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
 180 #endif
 181         { TX6UL_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 182         { TX6UL_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 183         { TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
 184 };
 185
 186 static const struct gpio const tx6ul_fec2_gpios[] = {
 187         { TX6UL_FEC2_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC2 PHY RESET", },
 188         { TX6UL_FEC2_INT_GPIO, GPIOFLAG_INPUT, "FEC2 PHY INT", },
 189 };
 190
 191 #define GPIO_DR 0
 192 #define GPIO_DIR 4
 193 #define GPIO_PSR 8
 194
 195 /* run with default environment */
 196 #if defined(TX6UL_I2C1_SCL_GPIO) && defined(TX6UL_I2C1_SDA_GPIO)
 197 #define SCL_BANK        (TX6UL_I2C1_SCL_GPIO / 32)
 198 #define SDA_BANK        (TX6UL_I2C1_SDA_GPIO / 32)
 199 #define SCL_BIT         (1 << (TX6UL_I2C1_SCL_GPIO % 32))
 200 #define SDA_BIT         (1 << (TX6UL_I2C1_SDA_GPIO % 32))
 201
 202 static void * const gpio_ports[] = {
 203         (void *)GPIO1_BASE_ADDR,
 204         (void *)GPIO2_BASE_ADDR,
 205         (void *)GPIO3_BASE_ADDR,
 206         (void *)GPIO4_BASE_ADDR,
 207         (void *)GPIO5_BASE_ADDR,
 208 };
 209
 210 static void tx6ul_i2c_recover(void)
 211 {
 212         int i;
 213         int bad = 0;
 214         struct gpio_regs *scl_regs = gpio_ports[SCL_BANK];
 215         struct gpio_regs *sda_regs = gpio_ports[SDA_BANK];
 216
 217         if ((readl(&scl_regs->gpio_psr) & SCL_BIT) &&
 218             (readl(&sda_regs->gpio_psr) & SDA_BIT))
 219                 return;
 220
 221         debug("Clearing I2C bus\n");
 222         if (!(readl(&scl_regs->gpio_psr) & SCL_BIT)) {
 223                 printf("I2C SCL stuck LOW\n");
 224                 bad++;
 225
 226                 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
 227                 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
 228
 229                 imx_iomux_v3_setup_pad(MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 |
 230                                        MUX_CFG_SION | TX6UL_GPIO_OUT_PAD_CTRL);
 231         }
 232         if (!(readl(&sda_regs->gpio_psr) & SDA_BIT)) {
 233                 printf("I2C SDA stuck LOW\n");
 234                 bad++;
 235
 236                 clrbits_le32(&sda_regs->gpio_dir, SDA_BIT);
 237                 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
 238                 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
 239
 240                 imx_iomux_v3_setup_multiple_pads(tx6ul_i2c_gpio_pads,
 241                                                  ARRAY_SIZE(tx6ul_i2c_gpio_pads));
 242
 243                 udelay(5);
 244
 245                 for (i = 0; i < 18; i++) {
 246                         u32 reg = readl(&scl_regs->gpio_dr) ^ SCL_BIT;
 247
 248                         debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
 249                         writel(reg, &scl_regs->gpio_dr);
 250                         udelay(5);
 251                         if (reg & SCL_BIT) {
 252                                 if (readl(&sda_regs->gpio_psr) & SDA_BIT)
 253                                         break;
 254                                 if (!(readl(&scl_regs->gpio_psr) & SCL_BIT))
 255                                         break;
 256                                 break;
 257                         }
 258                 }
 259         }
 260         if (bad) {
 261                 bool scl = !!(readl(&scl_regs->gpio_psr) & SCL_BIT);
 262                 bool sda = !!(readl(&sda_regs->gpio_psr) & SDA_BIT);
 263
 264                 if (scl && sda) {
 265                         printf("I2C bus recovery succeeded\n");
 266                 } else {
 267                         printf("I2C bus recovery FAILED: SCL: %d SDA: %d\n",
 268                                scl, sda);
 269                 }
 270                 imx_iomux_v3_setup_multiple_pads(tx6ul_i2c_pads,
 271                                                  ARRAY_SIZE(tx6ul_i2c_pads));
 272         }
 273 }
 274 #else
 275 static inline void tx6ul_i2c_recover(void)
 276 {
 277 }
 278 #endif
 279
 280 /* placed in section '.data' to prevent overwriting relocation info
 281  * overlayed with bss
 282  */
 283 static u32 wrsr __data;
 284
 285 #define WRSR_POR                        (1 << 4)
 286 #define WRSR_TOUT                       (1 << 1)
 287 #define WRSR_SFTW                       (1 << 0)
 288
 289 static void print_reset_cause(void)
 290 {
 291         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 292         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 293         u32 srsr;
 294         char *dlm = "";
 295
 296         printf("Reset cause: ");
 297
 298         srsr = readl(&src_regs->srsr);
 299         wrsr = readw(wdt_base + 4);
 300
 301         if (wrsr & WRSR_POR) {
 302                 printf("%sPOR", dlm);
 303                 dlm = " | ";
 304         }
 305         if (srsr & 0x00004) {
 306                 printf("%sCSU", dlm);
 307                 dlm = " | ";
 308         }
 309         if (srsr & 0x00008) {
 310                 printf("%sIPP USER", dlm);
 311                 dlm = " | ";
 312         }
 313         if (srsr & 0x00010) {
 314                 if (wrsr & WRSR_SFTW) {
 315                         printf("%sSOFT", dlm);
 316                         dlm = " | ";
 317                 }
 318                 if (wrsr & WRSR_TOUT) {
 319                         printf("%sWDOG", dlm);
 320                         dlm = " | ";
 321                 }
 322         }
 323         if (srsr & 0x00020) {
 324                 printf("%sJTAG HIGH-Z", dlm);
 325                 dlm = " | ";
 326         }
 327         if (srsr & 0x00040) {
 328                 printf("%sJTAG SW", dlm);
 329                 dlm = " | ";
 330         }
 331         if (srsr & 0x10000) {
 332                 printf("%sWARM BOOT", dlm);
 333                 dlm = " | ";
 334         }
 335         if (dlm[0] == '\0')
 336                 printf("unknown");
 337
 338         printf("\n");
 339 }
 340
 341 #ifdef CONFIG_IMX6_THERMAL
 342 #include <thermal.h>
 343 #include <imx_thermal.h>
 344 #include <fuse.h>
 345
 346 static void print_temperature(void)
 347 {
 348         struct udevice *thermal_dev;
 349         int cpu_tmp, minc, maxc, ret;
 350         char const *grade_str;
 351         static u32 __data thermal_calib;
 352
 353         puts("Temperature: ");
 354         switch (get_cpu_temp_grade(&minc, &maxc)) {
 355         case TEMP_AUTOMOTIVE:
 356                 grade_str = "Automotive";
 357                 break;
 358         case TEMP_INDUSTRIAL:
 359                 grade_str = "Industrial";
 360                 break;
 361         case TEMP_EXTCOMMERCIAL:
 362                 grade_str = "Extended Commercial";
 363                 break;
 364         default:
 365                 grade_str = "Commercial";
 366         }
 367         printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
 368         ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
 369         if (ret == 0) {
 370                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
 371
 372                 if (ret == 0)
 373                         printf(" at %dC", cpu_tmp);
 374                 else
 375                         puts(" - failed to read sensor data");
 376         } else {
 377                 puts(" - no sensor device found");
 378         }
 379
 380         if (fuse_read(1, 6, &thermal_calib) == 0) {
 381                 printf(" - calibration data 0x%08x\n", thermal_calib);
 382         } else {
 383                 puts(" - Failed to read thermal calib fuse\n");
 384         }
 385 }
 386 #else
 387 static inline void print_temperature(void)
 388 {
 389 }
 390 #endif
 391
 392 int checkboard(void)
 393 {
 394         u32 cpurev = get_cpu_rev();
 395         char *cpu_str = "?";
 396
 397         if (is_cpu_type(MXC_CPU_MX6SL))
 398                 cpu_str = "SL";
 399         else if (is_cpu_type(MXC_CPU_MX6DL))
 400                 cpu_str = "DL";
 401         else if (is_cpu_type(MXC_CPU_MX6SOLO))
 402                 cpu_str = "SOLO";
 403         else if (is_cpu_type(MXC_CPU_MX6Q))
 404                 cpu_str = "Q";
 405         else if (is_cpu_type(MXC_CPU_MX6UL))
 406                 cpu_str = "UL";
 407         else if (is_cpu_type(MXC_CPU_MX6ULL))
 408                 cpu_str = "ULL";
 409
 410         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
 411                 cpu_str,
 412                 (cpurev & 0x000F0) >> 4,
 413                 (cpurev & 0x0000F) >> 0,
 414                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 415
 416         print_temperature();
 417         print_reset_cause();
 418 #ifdef CONFIG_MX6_TEMPERATURE_HOT
 419         check_cpu_temperature(1);
 420 #endif
 421         tx6ul_i2c_recover();
 422         return 0;
 423 }
 424
 425 /* serial port not initialized at this point */
 426 int board_early_init_f(void)
 427 {
 428         return 0;
 429 }
 430
 431 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 432 static bool tx6ul_temp_check_enabled = true;
 433 #else
 434 #define tx6ul_temp_check_enabled        0
 435 #endif
 436
 437 static inline u8 tx6ul_mem_suffix(void)
 438 {
 439         return '0' + CONFIG_SYS_SDRAM_CHIP_SIZE / 1024 * 2 +
 440                 IS_ENABLED(CONFIG_TX6_EMMC);
 441 }
 442
 443 #ifdef CONFIG_RN5T567
 444 /* PMIC settings */
 445 #define VDD_RTC_VAL             rn5t_mV_to_regval_rtc(3000)
 446 #define VDD_CORE_VAL            rn5t_mV_to_regval(1300)         /* DCDC1 */
 447 #define VDD_CORE_VAL_LP         rn5t_mV_to_regval(900)
 448 #define VDD_DDR_VAL             rn5t_mV_to_regval(1350)         /* DCDC3 */
 449 #define VDD_DDR_VAL_LP          rn5t_mV_to_regval(1350)
 450 #define VDD_IO_EXT_VAL          rn5t_mV_to_regval(3300)         /* DCDC4 */
 451 #define VDD_IO_EXT_VAL_LP       rn5t_mV_to_regval(3300)
 452 #define VDD_IO_INT_VAL          rn5t_mV_to_regval2(3300)        /* LDO1 */
 453 #define VDD_IO_INT_VAL_LP       rn5t_mV_to_regval2(3300)
 454 #define VDD_ADC_VAL             rn5t_mV_to_regval2(3300)        /* LDO2 */
 455 #define VDD_ADC_VAL_LP          rn5t_mV_to_regval2(3300)
 456 #define VDD_PMIC_VAL            rn5t_mV_to_regval2(2500)        /* LDO3 */
 457 #define VDD_PMIC_VAL_LP         rn5t_mV_to_regval2(2500)
 458 #define VDD_CSI_VAL             rn5t_mV_to_regval2(1800)        /* LDO4 */
 459 #define VDD_CSI_VAL_LP          rn5t_mV_to_regval2(1800)
 460
 461 static struct pmic_regs rn5t567_regs[] = {
 462         { RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, },
 463         { RN5T567_DC1DAC, VDD_CORE_VAL, },
 464         { RN5T567_DC3DAC, VDD_DDR_VAL, },
 465         { RN5T567_DC4DAC, VDD_IO_EXT_VAL, },
 466         { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
 467         { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
 468         { RN5T567_DC4DAC_SLP, VDD_IO_EXT_VAL_LP, },
 469         { RN5T567_DC1CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
 470         { RN5T567_DC2CTL, DCnCTL_DCnDIS, },
 471         { RN5T567_DC3CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
 472         { RN5T567_DC4CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
 473         { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
 474         { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
 475         { RN5T567_LDO1DAC, VDD_IO_INT_VAL, },
 476         { RN5T567_LDO2DAC, VDD_ADC_VAL, },
 477         { RN5T567_LDO3DAC, VDD_PMIC_VAL, },
 478         { RN5T567_LDO4DAC, VDD_CSI_VAL, },
 479         { RN5T567_LDOEN1, 0x0f, ~0x1f, },
 480         { RN5T567_LDOEN2, 0x10, ~0x30, },
 481         { RN5T567_LDODIS, 0x10, ~0x1f, },
 482         { RN5T567_INTPOL, 0, },
 483         { RN5T567_INTEN, 0x3, },
 484         { RN5T567_IREN, 0xf, },
 485         { RN5T567_EN_GPIR, 0, },
 486 };
 487
 488 static int pmic_addr = 0x33;
 489 #endif
 490
 491 int board_init(void)
 492 {
 493         int ret;
 494         u32 cpurev = get_cpu_rev();
 495         char f = '?';
 496
 497         if (is_cpu_type(MXC_CPU_MX6UL))
 498                 f = ((cpurev & 0xf0) > 0x10) ? '5' : '0';
 499         else if (is_cpu_type(MXC_CPU_MX6ULL))
 500                 f = '8';
 501
 502         debug("%s@%d: cpurev=%08x\n", __func__, __LINE__, cpurev);
 503
 504         printf("Board: Ka-Ro TXUL-%c01%c\n", f, tx6ul_mem_suffix());
 505
 506         get_hab_status();
 507
 508         ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios));
 509         if (ret < 0)
 510                 printf("Failed to request tx6ul_gpios: %d\n", ret);
 511
 512         imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads));
 513
 514         /* Address of boot parameters */
 515         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 516         gd->bd->bi_arch_number = -1;
 517
 518         if (ctrlc() || (wrsr & WRSR_TOUT)) {
 519                 if (wrsr & WRSR_TOUT)
 520                         printf("WDOG RESET detected; Skipping PMIC setup\n");
 521                 else
 522                         printf("<CTRL-C> detected; safeboot enabled\n");
 523 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 524                 tx6ul_temp_check_enabled = false;
 525 #endif
 526                 return 0;
 527         }
 528
 529         ret = tx6_pmic_init(pmic_addr, rn5t567_regs, ARRAY_SIZE(rn5t567_regs));
 530         if (ret) {
 531                 printf("Failed to setup PMIC voltages: %d\n", ret);
 532                 hang();
 533         }
 534         return 0;
 535 }
 536
 537 int dram_init(void)
 538 {
 539         debug("%s@%d: \n", __func__, __LINE__);
 540
 541         /* dram_init must store complete ramsize in gd->ram_size */
 542         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 543                                     PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
 544         return 0;
 545 }
 546
 547 void dram_init_banksize(void)
 548 {
 549         debug("%s@%d: \n", __func__, __LINE__);
 550
 551         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 552         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 553                                                PHYS_SDRAM_1_SIZE);
 554 #if CONFIG_NR_DRAM_BANKS > 1
 555         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 556         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 557                                                PHYS_SDRAM_2_SIZE);
 558 #endif
 559 }
 560
 561 #ifdef  CONFIG_FSL_ESDHC
 562 #define TX6UL_SD_PAD_CTRL       MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |       \
 563                                         PAD_CTL_SPEED_MED |             \
 564                                         PAD_CTL_DSE_40ohm |             \
 565                                         PAD_CTL_SRE_FAST)
 566
 567 static const iomux_v3_cfg_t mmc0_pads[] = {
 568         MX6_PAD_SD1_CMD__USDHC1_CMD | TX6UL_SD_PAD_CTRL,
 569         MX6_PAD_SD1_CLK__USDHC1_CLK | TX6UL_SD_PAD_CTRL,
 570         MX6_PAD_SD1_DATA0__USDHC1_DATA0 | TX6UL_SD_PAD_CTRL,
 571         MX6_PAD_SD1_DATA1__USDHC1_DATA1 | TX6UL_SD_PAD_CTRL,
 572         MX6_PAD_SD1_DATA2__USDHC1_DATA2 | TX6UL_SD_PAD_CTRL,
 573         MX6_PAD_SD1_DATA3__USDHC1_DATA3 | TX6UL_SD_PAD_CTRL,
 574         /* SD1 CD */
 575         MX6_PAD_NAND_CE1_B__GPIO4_IO14 | TX6UL_SD_PAD_CTRL,
 576 };
 577
 578 #ifdef CONFIG_TX6_EMMC
 579 static const iomux_v3_cfg_t mmc1_pads[] = {
 580         MX6_PAD_NAND_WE_B__USDHC2_CMD | TX6UL_SD_PAD_CTRL,
 581         MX6_PAD_NAND_RE_B__USDHC2_CLK | TX6UL_SD_PAD_CTRL,
 582         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | TX6UL_SD_PAD_CTRL,
 583         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | TX6UL_SD_PAD_CTRL,
 584         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | TX6UL_SD_PAD_CTRL,
 585         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | TX6UL_SD_PAD_CTRL,
 586         /* eMMC RESET */
 587         MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
 588                                                         PAD_CTL_DSE_40ohm),
 589 };
 590 #endif
 591
 592 static struct tx6ul_esdhc_cfg {
 593         const iomux_v3_cfg_t *pads;
 594         int num_pads;
 595         enum mxc_clock clkid;
 596         struct fsl_esdhc_cfg cfg;
 597         int cd_gpio;
 598 } tx6ul_esdhc_cfg[] = {
 599 #ifdef CONFIG_TX6_EMMC
 600         {
 601                 .pads = mmc1_pads,
 602                 .num_pads = ARRAY_SIZE(mmc1_pads),
 603                 .clkid = MXC_ESDHC2_CLK,
 604                 .cfg = {
 605                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
 606                         .max_bus_width = 4,
 607                 },
 608                 .cd_gpio = -EINVAL,
 609         },
 610 #endif
 611         {
 612                 .pads = mmc0_pads,
 613                 .num_pads = ARRAY_SIZE(mmc0_pads),
 614                 .clkid = MXC_ESDHC_CLK,
 615                 .cfg = {
 616                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
 617                         .max_bus_width = 4,
 618                 },
 619                 .cd_gpio = TX6UL_SD1_CD_GPIO,
 620         },
 621 };
 622
 623 static inline struct tx6ul_esdhc_cfg *to_tx6ul_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 624 {
 625         return container_of(cfg, struct tx6ul_esdhc_cfg, cfg);
 626 }
 627
 628 int board_mmc_getcd(struct mmc *mmc)
 629 {
 630         struct tx6ul_esdhc_cfg *cfg = to_tx6ul_esdhc_cfg(mmc->priv);
 631
 632         if (cfg->cd_gpio < 0)
 633                 return 1;
 634
 635         debug("SD card %d is %spresent (GPIO %d)\n",
 636               cfg - tx6ul_esdhc_cfg,
 637               gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
 638               cfg->cd_gpio);
 639         return !gpio_get_value(cfg->cd_gpio);
 640 }
 641
 642 int board_mmc_init(bd_t *bis)
 643 {
 644         int i;
 645
 646         debug("%s@%d: \n", __func__, __LINE__);
 647
 648 #ifndef CONFIG_ENV_IS_IN_MMC
 649         if (!(gd->flags & GD_FLG_ENV_READY)) {
 650                 printf("deferred ...");
 651                 return 0;
 652         }
 653 #endif
 654         for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) {
 655                 struct mmc *mmc;
 656                 struct tx6ul_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
 657                 int ret;
 658
 659                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
 660                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
 661
 662                 if (cfg->cd_gpio >= 0) {
 663                         ret = gpio_request_one(cfg->cd_gpio,
 664                                                GPIOFLAG_INPUT, "MMC CD");
 665                         if (ret) {
 666                                 printf("Error %d requesting GPIO%d_%d\n",
 667                                        ret, cfg->cd_gpio / 32,
 668                                        cfg->cd_gpio % 32);
 669                                 continue;
 670                         }
 671                 }
 672
 673                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 674                 fsl_esdhc_initialize(bis, &cfg->cfg);
 675
 676                 mmc = find_mmc_device(i);
 677                 if (mmc == NULL)
 678                         continue;
 679                 if (board_mmc_getcd(mmc))
 680                         mmc_init(mmc);
 681         }
 682         return 0;
 683 }
 684 #endif /* CONFIG_FSL_ESDHC */
 685
 686 enum {
 687         LED_STATE_INIT = -1,
 688         LED_STATE_OFF,
 689         LED_STATE_ON,
 690         LED_STATE_ERR,
 691 };
 692
 693 static inline int calc_blink_rate(void)
 694 {
 695         if (!tx6ul_temp_check_enabled)
 696                 return CONFIG_SYS_HZ;
 697
 698         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
 699                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
 700                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
 701 }
 702
 703 void show_activity(int arg)
 704 {
 705         static int led_state = LED_STATE_INIT;
 706         static int blink_rate;
 707         static ulong last;
 708         int ret;
 709
 710         switch (led_state) {
 711         case LED_STATE_ERR:
 712                 return;
 713
 714         case LED_STATE_INIT:
 715                 last = get_timer(0);
 716                 ret = gpio_set_value(TX6UL_LED_GPIO, 1);
 717                 if (ret)
 718                         led_state = LED_STATE_ERR;
 719                 else
 720                         led_state = LED_STATE_ON;
 721                 blink_rate = calc_blink_rate();
 722                 break;
 723
 724         case LED_STATE_ON:
 725         case LED_STATE_OFF:
 726                 if (get_timer(last) > blink_rate) {
 727                         blink_rate = calc_blink_rate();
 728                         last = get_timer_masked();
 729                         if (led_state == LED_STATE_ON) {
 730                                 gpio_set_value(TX6UL_LED_GPIO, 0);
 731                         } else {
 732                                 gpio_set_value(TX6UL_LED_GPIO, 1);
 733                         }
 734                         led_state = 1 - led_state;
 735                 }
 736                 break;
 737         }
 738 }
 739
 740 static const iomux_v3_cfg_t stk5_jtag_pads[] = {
 741         MX6_PAD_JTAG_MOD__SJC_MOD | TX6UL_GPIO_IN_PAD_CTRL,
 742         MX6_PAD_JTAG_TCK__SJC_TCK | TX6UL_GPIO_IN_PAD_CTRL,
 743         MX6_PAD_JTAG_TRST_B__SJC_TRSTB | TX6UL_GPIO_IN_PAD_CTRL,
 744         MX6_PAD_JTAG_TDI__SJC_TDI | TX6UL_GPIO_IN_PAD_CTRL,
 745         MX6_PAD_JTAG_TDO__SJC_TDO | TX6UL_GPIO_OUT_PAD_CTRL,
 746         MX6_PAD_JTAG_TMS__SJC_TMS | TX6UL_GPIO_IN_PAD_CTRL,
 747 };
 748
 749 static const iomux_v3_cfg_t stk5_pads[] = {
 750         /* SW controlled LED on STK5 baseboard */
 751         MX6_PAD_SNVS_TAMPER9__GPIO5_IO09,
 752
 753         /* I2C bus on DIMM pins 40/41 */
 754         MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
 755         MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
 756
 757         /* TSC200x PEN IRQ */
 758         MX6_PAD_JTAG_TMS__GPIO1_IO11 | TX6UL_GPIO_IN_PAD_CTRL,
 759
 760         /* EDT-FT5x06 Polytouch panel */
 761         MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | TX6UL_GPIO_IN_PAD_CTRL, /* IRQ */
 762         MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 | TX6UL_GPIO_OUT_PAD_CTRL, /* RESET */
 763         MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | TX6UL_GPIO_OUT_PAD_CTRL, /* WAKE */
 764
 765         /* USBH1 */
 766         MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
 767         MX6_PAD_GPIO1_IO03__USB_OTG2_OC | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
 768
 769         /* USBOTG */
 770         MX6_PAD_UART3_CTS_B__GPIO1_IO26 | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
 771         MX6_PAD_UART3_RTS_B__GPIO1_IO27 | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
 772 };
 773
 774 static const struct gpio stk5_gpios[] = {
 775         { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 776
 777         { IMX_GPIO_NR(1, 27), GPIOFLAG_INPUT, "USBOTG OC", },
 778         { IMX_GPIO_NR(1, 26), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 779 };
 780
 781 #ifdef CONFIG_LCD
 782 vidinfo_t panel_info = {
 783         /* set to max. size supported by SoC */
 784         .vl_col = 4096,
 785         .vl_row = 1024,
 786
 787         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 788 };
 789
 790 static struct fb_videomode tx6ul_fb_modes[] = {
 791 #ifndef CONFIG_SYS_LVDS_IF
 792         {
 793                 /* Standard VGA timing */
 794                 .name           = "VGA",
 795                 .refresh        = 60,
 796                 .xres           = 640,
 797                 .yres           = 480,
 798                 .pixclock       = KHZ2PICOS(25175),
 799                 .left_margin    = 48,
 800                 .hsync_len      = 96,
 801                 .right_margin   = 16,
 802                 .upper_margin   = 31,
 803                 .vsync_len      = 2,
 804                 .lower_margin   = 12,
 805                 .sync           = FB_SYNC_CLK_LAT_FALL,
 806         },
 807         {
 808                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 809                  * DE high active, 115.2 mm x 86.4 mm display area
 810                  * VGA compatible timing
 811                  */
 812                 .name           = "ETV570",
 813                 .refresh        = 60,
 814                 .xres           = 640,
 815                 .yres           = 480,
 816                 .pixclock       = KHZ2PICOS(25175),
 817                 .left_margin    = 114,
 818                 .hsync_len      = 30,
 819                 .right_margin   = 16,
 820                 .upper_margin   = 32,
 821                 .vsync_len      = 3,
 822                 .lower_margin   = 10,
 823                 .sync           = FB_SYNC_CLK_LAT_FALL,
 824         },
 825         {
 826                 /* Emerging ET0350G0DH6 320 x 240 display.
 827                  * 70.08 mm x 52.56 mm display area.
 828                  */
 829                 .name           = "ET0350",
 830                 .refresh        = 60,
 831                 .xres           = 320,
 832                 .yres           = 240,
 833                 .pixclock       = KHZ2PICOS(6500),
 834                 .left_margin    = 68 - 34,
 835                 .hsync_len      = 34,
 836                 .right_margin   = 20,
 837                 .upper_margin   = 18 - 3,
 838                 .vsync_len      = 3,
 839                 .lower_margin   = 4,
 840                 .sync           = FB_SYNC_CLK_LAT_FALL,
 841         },
 842         {
 843                 /* Emerging ET0430G0DH6 480 x 272 display.
 844                  * 95.04 mm x 53.856 mm display area.
 845                  */
 846                 .name           = "ET0430",
 847                 .refresh        = 60,
 848                 .xres           = 480,
 849                 .yres           = 272,
 850                 .pixclock       = KHZ2PICOS(9000),
 851                 .left_margin    = 2,
 852                 .hsync_len      = 41,
 853                 .right_margin   = 2,
 854                 .upper_margin   = 2,
 855                 .vsync_len      = 10,
 856                 .lower_margin   = 2,
 857         },
 858         {
 859                 /* Emerging ET0500G0DH6 800 x 480 display.
 860                  * 109.6 mm x 66.4 mm display area.
 861                  */
 862                 .name           = "ET0500",
 863                 .refresh        = 60,
 864                 .xres           = 800,
 865                 .yres           = 480,
 866                 .pixclock       = KHZ2PICOS(33260),
 867                 .left_margin    = 216 - 128,
 868                 .hsync_len      = 128,
 869                 .right_margin   = 1056 - 800 - 216,
 870                 .upper_margin   = 35 - 2,
 871                 .vsync_len      = 2,
 872                 .lower_margin   = 525 - 480 - 35,
 873                 .sync           = FB_SYNC_CLK_LAT_FALL,
 874         },
 875         {
 876                 /* Emerging ETQ570G0DH6 320 x 240 display.
 877                  * 115.2 mm x 86.4 mm display area.
 878                  */
 879                 .name           = "ETQ570",
 880                 .refresh        = 60,
 881                 .xres           = 320,
 882                 .yres           = 240,
 883                 .pixclock       = KHZ2PICOS(6400),
 884                 .left_margin    = 38,
 885                 .hsync_len      = 30,
 886                 .right_margin   = 30,
 887                 .upper_margin   = 16, /* 15 according to datasheet */
 888                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 889                 .lower_margin   = 4, /* 4.5 according to datasheet */
 890                 .sync           = FB_SYNC_CLK_LAT_FALL,
 891         },
 892         {
 893                 /* Emerging ET0700G0DH6 800 x 480 display.
 894                  * 152.4 mm x 91.44 mm display area.
 895                  */
 896                 .name           = "ET0700",
 897                 .refresh        = 60,
 898                 .xres           = 800,
 899                 .yres           = 480,
 900                 .pixclock       = KHZ2PICOS(33260),
 901                 .left_margin    = 216 - 128,
 902                 .hsync_len      = 128,
 903                 .right_margin   = 1056 - 800 - 216,
 904                 .upper_margin   = 35 - 2,
 905                 .vsync_len      = 2,
 906                 .lower_margin   = 525 - 480 - 35,
 907                 .sync           = FB_SYNC_CLK_LAT_FALL,
 908         },
 909         {
 910                 /* Emerging ET070001DM6 800 x 480 display.
 911                  * 152.4 mm x 91.44 mm display area.
 912                  */
 913                 .name           = "ET070001DM6",
 914                 .refresh        = 60,
 915                 .xres           = 800,
 916                 .yres           = 480,
 917                 .pixclock       = KHZ2PICOS(33260),
 918                 .left_margin    = 216 - 128,
 919                 .hsync_len      = 128,
 920                 .right_margin   = 1056 - 800 - 216,
 921                 .upper_margin   = 35 - 2,
 922                 .vsync_len      = 2,
 923                 .lower_margin   = 525 - 480 - 35,
 924                 .sync           = 0,
 925         },
 926 #else
 927         {
 928                 /* HannStar HSD100PXN1
 929                  * 202.7m mm x 152.06 mm display area.
 930                  */
 931                 .name           = "HSD100PXN1",
 932                 .refresh        = 60,
 933                 .xres           = 1024,
 934                 .yres           = 768,
 935                 .pixclock       = KHZ2PICOS(65000),
 936                 .left_margin    = 0,
 937                 .hsync_len      = 0,
 938                 .right_margin   = 320,
 939                 .upper_margin   = 0,
 940                 .vsync_len      = 0,
 941                 .lower_margin   = 38,
 942                 .sync           = FB_SYNC_CLK_LAT_FALL,
 943         },
 944 #endif
 945         {
 946                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 947                 .refresh        = 60,
 948                 .left_margin    = 48,
 949                 .hsync_len      = 96,
 950                 .right_margin   = 16,
 951                 .upper_margin   = 31,
 952                 .vsync_len      = 2,
 953                 .lower_margin   = 12,
 954                 .sync           = FB_SYNC_CLK_LAT_FALL,
 955         },
 956 };
 957
 958 static int lcd_enabled = 1;
 959 static int lcd_bl_polarity;
 960
 961 static int lcd_backlight_polarity(void)
 962 {
 963         return lcd_bl_polarity;
 964 }
 965
 966 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 967 #ifdef CONFIG_LCD
 968         /* LCD RESET */
 969         MX6_PAD_LCD_RESET__GPIO3_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
 970         /* LCD POWER_ENABLE */
 971         MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
 972         /* LCD Backlight (PWM) */
 973         MX6_PAD_NAND_DQS__GPIO4_IO16 | TX6UL_GPIO_OUT_PAD_CTRL,
 974         /* Display */
 975         MX6_PAD_LCD_DATA00__LCDIF_DATA00,
 976         MX6_PAD_LCD_DATA01__LCDIF_DATA01,
 977         MX6_PAD_LCD_DATA02__LCDIF_DATA02,
 978         MX6_PAD_LCD_DATA03__LCDIF_DATA03,
 979         MX6_PAD_LCD_DATA04__LCDIF_DATA04,
 980         MX6_PAD_LCD_DATA05__LCDIF_DATA05,
 981         MX6_PAD_LCD_DATA06__LCDIF_DATA06,
 982         MX6_PAD_LCD_DATA07__LCDIF_DATA07,
 983         MX6_PAD_LCD_DATA08__LCDIF_DATA08,
 984         MX6_PAD_LCD_DATA09__LCDIF_DATA09,
 985         MX6_PAD_LCD_DATA10__LCDIF_DATA10,
 986         MX6_PAD_LCD_DATA11__LCDIF_DATA11,
 987         MX6_PAD_LCD_DATA12__LCDIF_DATA12,
 988         MX6_PAD_LCD_DATA13__LCDIF_DATA13,
 989         MX6_PAD_LCD_DATA14__LCDIF_DATA14,
 990         MX6_PAD_LCD_DATA15__LCDIF_DATA15,
 991         MX6_PAD_LCD_DATA16__LCDIF_DATA16,
 992         MX6_PAD_LCD_DATA17__LCDIF_DATA17,
 993         MX6_PAD_LCD_DATA18__LCDIF_DATA18,
 994         MX6_PAD_LCD_DATA19__LCDIF_DATA19,
 995         MX6_PAD_LCD_DATA20__LCDIF_DATA20,
 996         MX6_PAD_LCD_DATA21__LCDIF_DATA21,
 997         MX6_PAD_LCD_DATA22__LCDIF_DATA22,
 998         MX6_PAD_LCD_DATA23__LCDIF_DATA23,
 999         MX6_PAD_LCD_HSYNC__LCDIF_HSYNC, /* HSYNC */
1000         MX6_PAD_LCD_VSYNC__LCDIF_VSYNC, /* VSYNC */
1001         MX6_PAD_LCD_ENABLE__LCDIF_ENABLE, /* OE_ACD */
1002         MX6_PAD_LCD_CLK__LCDIF_CLK, /* LSCLK */
1003 #endif
1004 };
1005
1006 static const struct gpio stk5_lcd_gpios[] = {
1007         { TX6UL_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1008         { TX6UL_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1009         { TX6UL_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1010 };
1011
1012 /* run with valid env from NAND/eMMC */
1013 void lcd_enable(void)
1014 {
1015         /* HACK ALERT:
1016          * global variable from common/lcd.c
1017          * Set to 0 here to prevent messages from going to LCD
1018          * rather than serial console
1019          */
1020         lcd_is_enabled = 0;
1021
1022         if (lcd_enabled) {
1023                 karo_load_splashimage(1);
1024
1025                 debug("Switching LCD on\n");
1026                 gpio_set_value(TX6UL_LCD_PWR_GPIO, 1);
1027                 udelay(100);
1028                 gpio_set_value(TX6UL_LCD_RST_GPIO, 1);
1029                 udelay(300000);
1030                 gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
1031                                lcd_backlight_polarity());
1032         }
1033 }
1034
1035 static void lcd_disable(void)
1036 {
1037         if (lcd_enabled) {
1038                 printf("Disabling LCD\n");
1039                 panel_info.vl_row = 0;
1040                 lcd_enabled = 0;
1041         }
1042 }
1043
1044 void lcd_ctrl_init(void *lcdbase)
1045 {
1046         int color_depth = 24;
1047         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1048         const char *vm;
1049         unsigned long val;
1050         int refresh = 60;
1051         struct fb_videomode *p = &tx6ul_fb_modes[0];
1052         struct fb_videomode fb_mode;
1053         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1054
1055         if (!lcd_enabled) {
1056                 debug("LCD disabled\n");
1057                 return;
1058         }
1059
1060         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1061                 lcd_disable();
1062                 setenv("splashimage", NULL);
1063                 return;
1064         }
1065
1066         karo_fdt_move_fdt();
1067         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1068
1069         if (video_mode == NULL) {
1070                 lcd_disable();
1071                 return;
1072         }
1073         vm = video_mode;
1074         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1075                 p = &fb_mode;
1076                 debug("Using video mode from FDT\n");
1077                 vm += strlen(vm);
1078                 if (fb_mode.xres > panel_info.vl_col ||
1079                         fb_mode.yres > panel_info.vl_row) {
1080                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1081                                fb_mode.xres, fb_mode.yres,
1082                                panel_info.vl_col, panel_info.vl_row);
1083                         lcd_enabled = 0;
1084                         return;
1085                 }
1086         }
1087         if (p->name != NULL)
1088                 debug("Trying compiled-in video modes\n");
1089         while (p->name != NULL) {
1090                 if (strcmp(p->name, vm) == 0) {
1091                         debug("Using video mode: '%s'\n", p->name);
1092                         vm += strlen(vm);
1093                         break;
1094                 }
1095                 p++;
1096         }
1097         if (*vm != '\0')
1098                 debug("Trying to decode video_mode: '%s'\n", vm);
1099         while (*vm != '\0') {
1100                 if (*vm >= '0' && *vm <= '9') {
1101                         char *end;
1102
1103                         val = simple_strtoul(vm, &end, 0);
1104                         if (end > vm) {
1105                                 if (!xres_set) {
1106                                         if (val > panel_info.vl_col)
1107                                                 val = panel_info.vl_col;
1108                                         p->xres = val;
1109                                         panel_info.vl_col = val;
1110                                         xres_set = 1;
1111                                 } else if (!yres_set) {
1112                                         if (val > panel_info.vl_row)
1113                                                 val = panel_info.vl_row;
1114                                         p->yres = val;
1115                                         panel_info.vl_row = val;
1116                                         yres_set = 1;
1117                                 } else if (!bpp_set) {
1118                                         switch (val) {
1119                                         case 8:
1120                                         case 16:
1121                                         case 18:
1122                                         case 24:
1123                                         case 32:
1124                                                 color_depth = val;
1125                                                 break;
1126
1127                                         default:
1128                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1129                                                        end - vm, vm,
1130                                                        color_depth);
1131                                         }
1132                                         bpp_set = 1;
1133                                 } else if (!refresh_set) {
1134                                         refresh = val;
1135                                         refresh_set = 1;
1136                                 }
1137                         }
1138                         vm = end;
1139                 }
1140                 switch (*vm) {
1141                 case '@':
1142                         bpp_set = 1;
1143                         /* fallthru */
1144                 case '-':
1145                         yres_set = 1;
1146                         /* fallthru */
1147                 case 'x':
1148                         xres_set = 1;
1149                         /* fallthru */
1150                 case 'M':
1151                 case 'R':
1152                         vm++;
1153                         break;
1154
1155                 default:
1156                         if (*vm != '\0')
1157                                 vm++;
1158                 }
1159         }
1160         if (p->xres == 0 || p->yres == 0) {
1161                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1162                 lcd_enabled = 0;
1163                 printf("Supported video modes are:");
1164                 for (p = &tx6ul_fb_modes[0]; p->name != NULL; p++) {
1165                         printf(" %s", p->name);
1166                 }
1167                 printf("\n");
1168                 return;
1169         }
1170         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1171                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1172                        p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1173                 lcd_enabled = 0;
1174                 return;
1175         }
1176         panel_info.vl_col = p->xres;
1177         panel_info.vl_row = p->yres;
1178
1179         switch (color_depth) {
1180         case 8:
1181                 panel_info.vl_bpix = LCD_COLOR8;
1182                 break;
1183         case 16:
1184                 panel_info.vl_bpix = LCD_COLOR16;
1185                 break;
1186         default:
1187                 panel_info.vl_bpix = LCD_COLOR32;
1188         }
1189
1190         p->pixclock = KHZ2PICOS(refresh *
1191                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1192                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1193                                 1000);
1194         debug("Pixel clock set to %lu.%03lu MHz\n",
1195               PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1196
1197         if (p != &fb_mode) {
1198                 int ret;
1199
1200                 debug("Creating new display-timing node from '%s'\n",
1201                       video_mode);
1202                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1203                 if (ret)
1204                         printf("Failed to create new display-timing node from '%s': %d\n",
1205                                video_mode, ret);
1206         }
1207
1208         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1209         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1210                                          ARRAY_SIZE(stk5_lcd_pads));
1211
1212         debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
1213               color_depth, refresh);
1214
1215         if (karo_load_splashimage(0) == 0) {
1216                 char vmode[128];
1217
1218                 /* setup env variable for mxsfb display driver */
1219                 snprintf(vmode, sizeof(vmode),
1220                          "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
1221                          p->xres, p->yres, p->left_margin, p->right_margin,
1222                          p->upper_margin, p->lower_margin, p->hsync_len,
1223                          p->vsync_len, p->sync, p->pixclock, color_depth);
1224                 setenv("videomode", vmode);
1225
1226                 debug("Initializing LCD controller\n");
1227                 lcdif_clk_enable();
1228                 video_hw_init();
1229                 setenv("videomode", NULL);
1230         } else {
1231                 debug("Skipping initialization of LCD controller\n");
1232         }
1233 }
1234 #else
1235 #define lcd_enabled 0
1236 #endif /* CONFIG_LCD */
1237
1238 #ifndef CONFIG_ENV_IS_IN_MMC
1239 static void tx6ul_mmc_init(void)
1240 {
1241         puts("MMC:   ");
1242         if (board_mmc_init(gd->bd) < 0)
1243                 cpu_mmc_init(gd->bd);
1244         print_mmc_devices(',');
1245 }
1246 #else
1247 static inline void tx6ul_mmc_init(void)
1248 {
1249 }
1250 #endif
1251
1252 static void stk5_board_init(void)
1253 {
1254         int ret;
1255
1256         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1257         if (ret < 0) {
1258                 printf("Failed to request stk5_gpios: %d\n", ret);
1259                 return;
1260         }
1261
1262         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1263         if (getenv_yesno("jtag_enable") != 0) {
1264                 /* true if unset or set to one of: 'yYtT1' */
1265                 imx_iomux_v3_setup_multiple_pads(stk5_jtag_pads, ARRAY_SIZE(stk5_jtag_pads));
1266         }
1267
1268         debug("%s@%d: \n", __func__, __LINE__);
1269 }
1270
1271 static void stk5v3_board_init(void)
1272 {
1273         debug("%s@%d: \n", __func__, __LINE__);
1274         stk5_board_init();
1275         debug("%s@%d: \n", __func__, __LINE__);
1276         tx6ul_mmc_init();
1277 }
1278
1279 static void stk5v5_board_init(void)
1280 {
1281         int ret;
1282
1283         stk5_board_init();
1284         tx6ul_mmc_init();
1285
1286         ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
1287                                "Flexcan Transceiver");
1288         if (ret) {
1289                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1290                 return;
1291         }
1292
1293         imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 |
1294                                TX6UL_GPIO_OUT_PAD_CTRL);
1295 }
1296
1297 static void tx6ul_set_cpu_clock(void)
1298 {
1299         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1300
1301         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1302                 return;
1303
1304         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1305                 printf("%s detected; skipping cpu clock change\n",
1306                        (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1307                 return;
1308         }
1309         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1310                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1311                 printf("CPU clock set to %lu.%03lu MHz\n",
1312                        cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1313         } else {
1314                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1315         }
1316 }
1317
1318 int board_late_init(void)
1319 {
1320         const char *baseboard;
1321
1322         debug("%s@%d: \n", __func__, __LINE__);
1323
1324         env_cleanup();
1325
1326         if (tx6ul_temp_check_enabled)
1327                 check_cpu_temperature(1);
1328
1329         tx6ul_set_cpu_clock();
1330
1331         if (had_ctrlc())
1332                 setenv_ulong("safeboot", 1);
1333         else if (wrsr & WRSR_TOUT)
1334                 setenv_ulong("wdreset", 1);
1335         else
1336                 karo_fdt_move_fdt();
1337
1338         baseboard = getenv("baseboard");
1339         if (!baseboard)
1340                 goto exit;
1341
1342         printf("Baseboard: %s\n", baseboard);
1343
1344         if (strncmp(baseboard, "stk5", 4) == 0) {
1345                 if ((strlen(baseboard) == 4) ||
1346                         strcmp(baseboard, "stk5-v3") == 0) {
1347                         stk5v3_board_init();
1348                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1349                         const char *otg_mode = getenv("otg_mode");
1350
1351                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1352                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1353                                        otg_mode, baseboard);
1354                                 setenv("otg_mode", "none");
1355                         }
1356                         stk5v5_board_init();
1357                 } else {
1358                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1359                                 baseboard + 4);
1360                 }
1361         } else if (strncmp(baseboard, "ulmb-", 5) == 0) {
1362                         const char *otg_mode = getenv("otg_mode");
1363
1364                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1365                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1366                                        otg_mode, baseboard);
1367                                 setenv("otg_mode", "none");
1368                         }
1369                         stk5_board_init();
1370         } else {
1371                 printf("WARNING: Unsupported baseboard: '%s'\n",
1372                         baseboard);
1373                 if (!had_ctrlc())
1374                         return -EINVAL;
1375         }
1376
1377 exit:
1378         debug("%s@%d: \n", __func__, __LINE__);
1379
1380         clear_ctrlc();
1381         return 0;
1382 }
1383
1384 #ifdef CONFIG_FEC_MXC
1385
1386 #ifndef ETH_ALEN
1387 #define ETH_ALEN 6
1388 #endif
1389
1390 static void tx6ul_init_mac(void)
1391 {
1392         u8 mac[ETH_ALEN];
1393         const char *baseboard = getenv("baseboard");
1394
1395         imx_get_mac_from_fuse(0, mac);
1396         if (!is_valid_ethaddr(mac)) {
1397                 printf("No valid MAC address programmed\n");
1398                 return;
1399         }
1400         printf("MAC addr from fuse: %pM\n", mac);
1401         if (!getenv("ethaddr"))
1402                 eth_setenv_enetaddr("ethaddr", mac);
1403
1404         if (!baseboard || strncmp(baseboard, "stk5", 4) == 0) {
1405                 setenv("eth1addr", NULL);
1406                 return;
1407         }
1408         if (getenv("eth1addr"))
1409                 return;
1410         imx_get_mac_from_fuse(1, mac);
1411         eth_setenv_enetaddr("eth1addr", mac);
1412 }
1413
1414 int board_eth_init(bd_t *bis)
1415 {
1416         int ret;
1417
1418         tx6ul_init_mac();
1419
1420         /* delay at least 21ms for the PHY internal POR signal to deassert */
1421         udelay(22000);
1422
1423         imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads,
1424                                          ARRAY_SIZE(tx6ul_enet1_pads));
1425
1426         /* Deassert RESET to the external phys */
1427         gpio_set_value(TX6UL_FEC_RST_GPIO, 1);
1428
1429         if (getenv("ethaddr")) {
1430                 ret = fecmxc_initialize_multi(bis, 0, 0, ENET_BASE_ADDR);
1431                 if (ret) {
1432                         printf("failed to initialize FEC0: %d\n", ret);
1433                         return ret;
1434                 }
1435         }
1436         if (getenv("eth1addr")) {
1437                 ret = gpio_request_array(tx6ul_fec2_gpios,
1438                                          ARRAY_SIZE(tx6ul_fec2_gpios));
1439                 if (ret < 0) {
1440                         printf("Failed to request tx6ul_fec2_gpios: %d\n", ret);
1441                 }
1442                 imx_iomux_v3_setup_multiple_pads(tx6ul_enet2_pads,
1443                                                  ARRAY_SIZE(tx6ul_enet2_pads));
1444
1445                 writel(0x00100000, 0x020c80e4); /* assert ENET2_125M_EN */
1446
1447                 /* Minimum PHY reset duration */
1448                 udelay(100);
1449                 gpio_set_value(TX6UL_FEC2_RST_GPIO, 1);
1450                 /* Wait for PHY internal POR to finish */
1451                 udelay(22000);
1452
1453                 ret = fecmxc_initialize_multi(bis, 1, 2, ENET2_BASE_ADDR);
1454                 if (ret) {
1455                         printf("failed to initialize FEC1: %d\n", ret);
1456                         return ret;
1457                 }
1458         }
1459         return 0;
1460 }
1461 #endif /* CONFIG_FEC_MXC */
1462
1463 #ifdef CONFIG_SERIAL_TAG
1464 void get_board_serial(struct tag_serialnr *serialnr)
1465 {
1466         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1467         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1468
1469         serialnr->low = readl(&fuse->cfg0);
1470         serialnr->high = readl(&fuse->cfg1);
1471 }
1472 #endif
1473
1474 #if defined(CONFIG_OF_BOARD_SETUP)
1475 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1476 #include <jffs2/jffs2.h>
1477 #include <mtd_node.h>
1478 static struct node_info nodes[] = {
1479         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1480 };
1481 #else
1482 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1483 #endif
1484
1485 static const char *tx6ul_touchpanels[] = {
1486         "ti,tsc2007",
1487         "edt,edt-ft5x06",
1488         "eeti,egalax_ts",
1489 };
1490
1491 int ft_board_setup(void *blob, bd_t *bd)
1492 {
1493         const char *baseboard = getenv("baseboard");
1494         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1495         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1496         int ret;
1497
1498         ret = fdt_increase_size(blob, 4096);
1499         if (ret) {
1500                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1501                 return ret;
1502         }
1503         if (stk5_v5)
1504                 karo_fdt_enable_node(blob, "stk5led", 0);
1505
1506         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1507
1508         karo_fdt_fixup_touchpanel(blob, tx6ul_touchpanels,
1509                                   ARRAY_SIZE(tx6ul_touchpanels));
1510         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1511         karo_fdt_fixup_flexcan(blob, stk5_v5);
1512
1513         karo_fdt_update_fb_mode(blob, video_mode, "/lcd-panel");
1514
1515         return 0;
1516 }
1517 #endif /* CONFIG_OF_BOARD_SETUP */