da40e530b8ff88db7e470ce7966f50bd966c61c6
[karo-tx-uboot.git] / board / karo / tx6 / tx6ul.c
1 /*
2  * Copyright (C) 2015 Lothar WaƟmann <LW@KARO-electronics.de>
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  *
6  */
7 #include <common.h>
8 #include <errno.h>
9 #include <libfdt.h>
10 #include <fdt_support.h>
11 #include <lcd.h>
12 #include <netdev.h>
13 #include <mmc.h>
14 #include <fsl_esdhc.h>
15 #include <video_fb.h>
16 #include <ipu.h>
17 #include <mxcfb.h>
18 #include <i2c.h>
19 #include <linux/fb.h>
20 #include <asm/io.h>
21 #include <asm/gpio.h>
22 #include <asm/arch/mx6-pins.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/hab.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/crm_regs.h>
27 #include <asm/arch/sys_proto.h>
28
29 #include "../common/karo.h"
30 #include "pmic.h"
31
32 #define __data __attribute__((section(".data")))
33
34 #define TX6UL_FEC_RST_GPIO              IMX_GPIO_NR(5, 6)
35 #define TX6UL_FEC_PWR_GPIO              IMX_GPIO_NR(5, 7)
36 #define TX6UL_FEC_INT_GPIO              IMX_GPIO_NR(5, 5)
37 #define TX6UL_LED_GPIO                  IMX_GPIO_NR(5, 9)
38
39 #define TX6UL_LCD_PWR_GPIO              IMX_GPIO_NR(5, 4)
40 #define TX6UL_LCD_RST_GPIO              IMX_GPIO_NR(3, 4)
41 #define TX6UL_LCD_BACKLIGHT_GPIO        IMX_GPIO_NR(4, 16)
42
43 #define TX6UL_I2C1_SCL_GPIO             CONFIG_SOFT_I2C_GPIO_SCL
44 #define TX6UL_I2C1_SDA_GPIO             CONFIG_SOFT_I2C_GPIO_SDA
45
46 #define TX6UL_SD1_CD_GPIO               IMX_GPIO_NR(4, 14)
47
48 #ifdef CONFIG_MX6_TEMPERATURE_MIN
49 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
50 #else
51 #define TEMPERATURE_MIN                 (-40)
52 #endif
53 #ifdef CONFIG_MX6_TEMPERATURE_HOT
54 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
55 #else
56 #define TEMPERATURE_HOT                 80
57 #endif
58
59 DECLARE_GLOBAL_DATA_PTR;
60
61 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
62
63 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
64 #ifdef CONFIG_SECURE_BOOT
65 char __csf_data[0] __attribute__((section(".__csf_data")));
66 #endif
67
68 static const iomux_v3_cfg_t const tx6ul_pads[] = {
69         /* UART pads */
70 #if CONFIG_MXC_UART_BASE == UART1_BASE
71         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX,
72         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX,
73         MX6_PAD_UART1_RTS_B__UART1_DCE_RTS,
74         MX6_PAD_UART1_CTS_B__UART1_DCE_CTS,
75 #endif
76 #if CONFIG_MXC_UART_BASE == UART2_BASE
77         MX6_PAD_UART2_TX_DATA__UART2_DCE_TX,
78         MX6_PAD_UART2_RX_DATA__UART2_DCE_RX,
79         MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS,
80         MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS,
81 #endif
82 #if CONFIG_MXC_UART_BASE == UART5_BASE
83         MX6_PAD_GPIO1_IO04__UART5_DCE_TX,
84         MX6_PAD_GPIO1_IO05__UART5_DCE_RX,
85         MX6_PAD_GPIO1_IO08__UART5_DCE_RTS,
86         MX6_PAD_GPIO1_IO09__UART5_DCE_CTS,
87 #endif
88         /* internal I2C */
89         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
90                         MUX_PAD_CTRL(PAD_CTL_DSE_240ohm), /* I2C SCL */
91         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
92                         MUX_PAD_CTRL(PAD_CTL_DSE_240ohm | PAD_CTL_HYS |
93                         PAD_CTL_ODE), /* I2C SDA */
94
95         /* FEC PHY GPIO functions */
96         MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_CFG_SION, /* PHY POWER */
97         MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | MUX_CFG_SION, /* PHY RESET */
98         MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
99                                                         PAD_CTL_DSE_40ohm), /* PHY INT */
100 };
101
102 #define TX6_ENET_PAD_CTRL       (PAD_CTL_SPEED_HIGH |   \
103                                 PAD_CTL_DSE_48ohm |     \
104                                 PAD_CTL_PUS_100K_UP |   \
105                                 PAD_CTL_SRE_FAST)
106 #define TX6_GPIO_OUT_PAD_CTRL   (PAD_CTL_SPEED_LOW |    \
107                                 PAD_CTL_DSE_60ohm |     \
108                                 PAD_CTL_SRE_SLOW)
109 #define TX6_GPIO_IN_PAD_CTRL    (PAD_CTL_SPEED_LOW |    \
110                                 PAD_CTL_PUS_47K_UP)
111
112 static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = {
113         /* FEC functions */
114         MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_48ohm |
115                                 PAD_CTL_SPEED_MED),
116         MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
117                                 PAD_CTL_DSE_48ohm |
118                                 PAD_CTL_SPEED_MED),
119         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_CFG_SION |
120                                 MUX_PAD_CTRL(PAD_CTL_SPEED_MED |
121                                 PAD_CTL_DSE_40ohm |
122                                 PAD_CTL_SRE_FAST),
123         MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
124         MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
125         MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
126         MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
127         MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
128         MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
129         MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
130
131         MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_CFG_SION |
132                                 MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |
133                                 PAD_CTL_DSE_48ohm |
134                                 PAD_CTL_SRE_FAST),
135         MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
136         MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
137         MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
138         MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
139         MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
140         MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
141         MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
142 };
143
144 #define TX6_I2C_PAD_CTRL        (PAD_CTL_PUS_22K_UP |   \
145                                 PAD_CTL_SPEED_MED |     \
146                                 PAD_CTL_DSE_34ohm |     \
147                                 PAD_CTL_SRE_FAST)
148
149 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
150         /* internal I2C */
151         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
152                         MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
153         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
154                         MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
155 };
156
157 static const struct gpio const tx6ul_gpios[] = {
158         /* These two entries are used to forcefully reinitialize the I2C bus */
159         { TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
160         { TX6UL_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
161
162         { TX6UL_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
163         { TX6UL_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
164         { TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
165 };
166
167 #define GPIO_DR 0
168 #define GPIO_DIR 4
169 #define GPIO_PSR 8
170
171 static void tx6_i2c_recover(void)
172 {
173         int i;
174         int bad = 0;
175 #define SCL_BIT         (1 << (TX6UL_I2C1_SCL_GPIO % 32))
176 #define SDA_BIT         (1 << (TX6UL_I2C1_SDA_GPIO % 32))
177 #define I2C_GPIO_BASE   (GPIO1_BASE_ADDR + TX6UL_I2C1_SCL_GPIO / 32 * 0x4000)
178
179         if ((readl(I2C_GPIO_BASE + GPIO_PSR) &
180                         (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
181                 return;
182
183         debug("Clearing I2C bus\n");
184         if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SCL_BIT)) {
185                 printf("I2C SCL stuck LOW\n");
186                 bad++;
187
188                 writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
189                         I2C_GPIO_BASE + GPIO_DR);
190                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
191                         I2C_GPIO_BASE + GPIO_DIR);
192         }
193         if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)) {
194                 printf("I2C SDA stuck LOW\n");
195                 bad++;
196
197                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) & ~SDA_BIT,
198                         I2C_GPIO_BASE + GPIO_DIR);
199                 writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
200                         I2C_GPIO_BASE + GPIO_DR);
201                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
202                         I2C_GPIO_BASE + GPIO_DIR);
203
204                 imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
205                                                 ARRAY_SIZE(tx6_i2c_gpio_pads));
206                 udelay(10);
207
208                 for (i = 0; i < 18; i++) {
209                         u32 reg = readl(I2C_GPIO_BASE + GPIO_DR) ^ SCL_BIT;
210
211                         debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
212                         writel(reg, I2C_GPIO_BASE + GPIO_DR);
213                         udelay(10);
214                         if (reg & SCL_BIT &&
215                                 readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)
216                                 break;
217                 }
218         }
219         if (bad) {
220                 u32 reg = readl(I2C_GPIO_BASE + GPIO_PSR);
221
222                 if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
223                         printf("I2C bus recovery succeeded\n");
224                 } else {
225                         printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
226                                 SCL_BIT | SDA_BIT);
227                 }
228         }
229 }
230
231 /* placed in section '.data' to prevent overwriting relocation info
232  * overlayed with bss
233  */
234 static u32 wrsr __data;
235
236 #define WRSR_POR                        (1 << 4)
237 #define WRSR_TOUT                       (1 << 1)
238 #define WRSR_SFTW                       (1 << 0)
239
240 static void print_reset_cause(void)
241 {
242         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
243         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
244         u32 srsr;
245         char *dlm = "";
246
247         printf("Reset cause: ");
248
249         srsr = readl(&src_regs->srsr);
250         wrsr = readw(wdt_base + 4);
251
252         if (wrsr & WRSR_POR) {
253                 printf("%sPOR", dlm);
254                 dlm = " | ";
255         }
256         if (srsr & 0x00004) {
257                 printf("%sCSU", dlm);
258                 dlm = " | ";
259         }
260         if (srsr & 0x00008) {
261                 printf("%sIPP USER", dlm);
262                 dlm = " | ";
263         }
264         if (srsr & 0x00010) {
265                 if (wrsr & WRSR_SFTW) {
266                         printf("%sSOFT", dlm);
267                         dlm = " | ";
268                 }
269                 if (wrsr & WRSR_TOUT) {
270                         printf("%sWDOG", dlm);
271                         dlm = " | ";
272                 }
273         }
274         if (srsr & 0x00020) {
275                 printf("%sJTAG HIGH-Z", dlm);
276                 dlm = " | ";
277         }
278         if (srsr & 0x00040) {
279                 printf("%sJTAG SW", dlm);
280                 dlm = " | ";
281         }
282         if (srsr & 0x10000) {
283                 printf("%sWARM BOOT", dlm);
284                 dlm = " | ";
285         }
286         if (dlm[0] == '\0')
287                 printf("unknown");
288
289         printf("\n");
290 }
291
292 #ifdef CONFIG_IMX6_THERMAL
293 #include <thermal.h>
294 #include <imx_thermal.h>
295 #include <fuse.h>
296
297 static void print_temperature(void)
298 {
299         struct udevice *thermal_dev;
300         int cpu_tmp, minc, maxc, ret;
301         char const *grade_str;
302         static u32 __data thermal_calib;
303
304         puts("Temperature: ");
305         switch (get_cpu_temp_grade(&minc, &maxc)) {
306         case TEMP_AUTOMOTIVE:
307                 grade_str = "Automotive";
308                 break;
309         case TEMP_INDUSTRIAL:
310                 grade_str = "Industrial";
311                 break;
312         case TEMP_EXTCOMMERCIAL:
313                 grade_str = "Extended Commercial";
314                 break;
315         default:
316                 grade_str = "Commercial";
317         }
318         printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
319         ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
320         if (ret == 0) {
321                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
322
323                 if (ret == 0)
324                         printf(" at %dC", cpu_tmp);
325                 else
326                         puts(" - failed to read sensor data");
327         } else {
328                 puts(" - no sensor device found");
329         }
330
331         if (fuse_read(1, 6, &thermal_calib) == 0) {
332                 printf(" - calibration data 0x%08x\n", thermal_calib);
333         } else {
334                 puts(" - Failed to read thermal calib fuse\n");
335         }
336 }
337 #else
338 static inline void print_temperature(void)
339 {
340 }
341 #endif
342
343 int checkboard(void)
344 {
345         u32 cpurev = get_cpu_rev();
346         char *cpu_str = "?";
347
348         switch ((cpurev >> 12) & 0xff) {
349         case MXC_CPU_MX6SL:
350                 cpu_str = "SL";
351                 break;
352         case MXC_CPU_MX6DL:
353                 cpu_str = "DL";
354                 break;
355         case MXC_CPU_MX6SOLO:
356                 cpu_str = "SOLO";
357                 break;
358         case MXC_CPU_MX6Q:
359                 cpu_str = "Q";
360                 break;
361         case MXC_CPU_MX6UL:
362                 cpu_str = "UL";
363                 break;
364         }
365
366         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
367                 cpu_str,
368                 (cpurev & 0x000F0) >> 4,
369                 (cpurev & 0x0000F) >> 0,
370                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
371
372         print_temperature();
373         print_reset_cause();
374 #ifdef CONFIG_MX6_TEMPERATURE_HOT
375         check_cpu_temperature(1);
376 #endif
377         tx6_i2c_recover();
378         return 0;
379 }
380
381 /* serial port not initialized at this point */
382 int board_early_init_f(void)
383 {
384         return 0;
385 }
386
387 #ifndef CONFIG_MX6_TEMPERATURE_HOT
388 static bool tx6_temp_check_enabled = true;
389 #else
390 #define tx6_temp_check_enabled  0
391 #endif
392
393 static inline u8 tx6ul_mem_suffix(void)
394 {
395 #ifdef CONFIG_TX6_NAND
396         return '0';
397 #else
398         return '1';
399 #endif
400 }
401
402 /* PMIC settings */
403 #define VDD_RTC_VAL             rn5t_mV_to_regval_rtc(3000)
404 #define VDD_CORE_VAL            rn5t_mV_to_regval(1300)         /* DCDC1 */
405 #define VDD_CORE_VAL_LP         rn5t_mV_to_regval(900)
406 #define VDD_DDR_VAL             rn5t_mV_to_regval(1350)         /* DCDC3 */
407 #define VDD_DDR_VAL_LP          rn5t_mV_to_regval(1350)
408 #define VDD_HIGH_VAL            rn5t_mV_to_regval(3300)         /* DCDC4 */
409 #define VDD_HIGH_VAL_LP         rn5t_mV_to_regval(3300)
410 #define VDD_CSI_VAL             rn5t_mV_to_regval2(3300)        /* LDO4 */
411 #define VDD_CSI_VAL_LP          rn5t_mV_to_regval2(3300)
412
413 static struct pmic_regs rn5t567_regs[] = {
414         { RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, },
415         { RN5T567_DC2CTL, DC2_DC2DIS, },
416         { RN5T567_DC1DAC, VDD_CORE_VAL, },
417         { RN5T567_DC3DAC, VDD_DDR_VAL, },
418         { RN5T567_DC4DAC, VDD_HIGH_VAL, },
419         { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
420         { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
421         { RN5T567_DC4DAC_SLP, VDD_HIGH_VAL_LP, },
422         { RN5T567_LDOEN1, 0x01f, ~0x1f, },
423         { RN5T567_LDOEN2, 0x10, ~0x30, },
424         { RN5T567_LDODIS, 0x00, },
425         { RN5T567_LDO4DAC, VDD_CSI_VAL, },
426         { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
427         { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
428 };
429
430 static int pmic_addr __maybe_unused = 0x33;
431
432 int board_init(void)
433 {
434         int ret;
435
436         debug("%s@%d: \n", __func__, __LINE__);
437
438         printf("Board: Ka-Ro TXUL-001%c\n",
439                 tx6ul_mem_suffix());
440
441         get_hab_status();
442
443         ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios));
444         if (ret < 0) {
445                 printf("Failed to request tx6ul_gpios: %d\n", ret);
446         }
447         imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads));
448
449         /* Address of boot parameters */
450         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
451         gd->bd->bi_arch_number = -1;
452
453         if (ctrlc() || (wrsr & WRSR_TOUT)) {
454                 if (wrsr & WRSR_TOUT)
455                         printf("WDOG RESET detected; Skipping PMIC setup\n");
456                 else
457                         printf("<CTRL-C> detected; safeboot enabled\n");
458 #ifndef CONFIG_MX6_TEMPERATURE_HOT
459                 tx6_temp_check_enabled = false;
460 #endif
461                 return 0;
462         }
463
464         ret = tx6_pmic_init(pmic_addr, rn5t567_regs, ARRAY_SIZE(rn5t567_regs));
465         if (ret) {
466                 printf("Failed to setup PMIC voltages: %d\n", ret);
467                 hang();
468         }
469         return 0;
470 }
471
472 int dram_init(void)
473 {
474         debug("%s@%d: \n", __func__, __LINE__);
475
476         /* dram_init must store complete ramsize in gd->ram_size */
477         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
478                                 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
479         return 0;
480 }
481
482 void dram_init_banksize(void)
483 {
484         debug("%s@%d: \n", __func__, __LINE__);
485
486         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
487         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
488                         PHYS_SDRAM_1_SIZE);
489 #if CONFIG_NR_DRAM_BANKS > 1
490         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
491         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
492                         PHYS_SDRAM_2_SIZE);
493 #endif
494 }
495
496 #ifdef  CONFIG_FSL_ESDHC
497 #define TX6_SD_PAD_CTRL         (PAD_CTL_PUS_47K_UP |   \
498                                 PAD_CTL_SPEED_MED |     \
499                                 PAD_CTL_DSE_40ohm |     \
500                                 PAD_CTL_SRE_FAST)
501
502 static const iomux_v3_cfg_t mmc0_pads[] = {
503         MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
504         MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
505         MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
506         MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
507         MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
508         MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
509         /* SD1 CD */
510         MX6_PAD_NAND_CE1_B__GPIO4_IO14 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
511 };
512
513 #ifdef CONFIG_TX6_EMMC
514 static const iomux_v3_cfg_t mmc1_pads[] = {
515         MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
516         MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
517         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
518         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
519         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
520         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
521         /* eMMC RESET */
522         MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
523                                                 PAD_CTL_DSE_40ohm),
524 };
525 #endif
526
527 static struct tx6_esdhc_cfg {
528         const iomux_v3_cfg_t *pads;
529         int num_pads;
530         enum mxc_clock clkid;
531         struct fsl_esdhc_cfg cfg;
532         int cd_gpio;
533 } tx6ul_esdhc_cfg[] = {
534 #ifdef CONFIG_TX6_EMMC
535         {
536                 .pads = mmc1_pads,
537                 .num_pads = ARRAY_SIZE(mmc1_pads),
538                 .clkid = MXC_ESDHC2_CLK,
539                 .cfg = {
540                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
541                         .max_bus_width = 4,
542                 },
543                 .cd_gpio = -EINVAL,
544         },
545 #endif
546         {
547                 .pads = mmc0_pads,
548                 .num_pads = ARRAY_SIZE(mmc0_pads),
549                 .clkid = MXC_ESDHC_CLK,
550                 .cfg = {
551                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
552                         .max_bus_width = 4,
553                 },
554                 .cd_gpio = TX6UL_SD1_CD_GPIO,
555         },
556 };
557
558 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
559 {
560         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
561 }
562
563 int board_mmc_getcd(struct mmc *mmc)
564 {
565         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
566
567         if (cfg->cd_gpio < 0)
568                 return 1;
569
570         debug("SD card %d is %spresent (GPIO %d)\n",
571                 cfg - tx6ul_esdhc_cfg,
572                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
573                 cfg->cd_gpio);
574         return !gpio_get_value(cfg->cd_gpio);
575 }
576
577 int board_mmc_init(bd_t *bis)
578 {
579         int i;
580
581         debug("%s@%d: \n", __func__, __LINE__);
582
583         for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) {
584                 struct mmc *mmc;
585                 struct tx6_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
586                 int ret;
587
588                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
589                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
590
591                 if (cfg->cd_gpio >= 0) {
592                         ret = gpio_request_one(cfg->cd_gpio,
593                                         GPIOFLAG_INPUT, "MMC CD");
594                         if (ret) {
595                                 printf("Error %d requesting GPIO%d_%d\n",
596                                         ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
597                                 continue;
598                         }
599                 }
600
601                 debug("%s: Initializing MMC slot %d\n", __func__, i);
602                 fsl_esdhc_initialize(bis, &cfg->cfg);
603
604                 mmc = find_mmc_device(i);
605                 if (mmc == NULL)
606                         continue;
607                 if (board_mmc_getcd(mmc))
608                         mmc_init(mmc);
609         }
610         return 0;
611 }
612 #endif /* CONFIG_CMD_MMC */
613
614 #ifdef CONFIG_FEC_MXC
615
616 #ifndef ETH_ALEN
617 #define ETH_ALEN 6
618 #endif
619
620 int board_eth_init(bd_t *bis)
621 {
622         int ret;
623
624         debug("%s@%d: \n", __func__, __LINE__);
625
626         /* delay at least 21ms for the PHY internal POR signal to deassert */
627         udelay(22000);
628
629         imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads,
630                                         ARRAY_SIZE(tx6ul_enet1_pads));
631
632         /* Deassert RESET to the external phy */
633         gpio_set_value(TX6UL_FEC_RST_GPIO, 1);
634
635         if (getenv("ethaddr")) {
636                 ret = fecmxc_initialize_multi(bis, 0, -1, ENET_BASE_ADDR);
637                 if (ret) {
638                         printf("failed to initialize FEC0: %d\n", ret);
639                         return ret;
640                 }
641         }
642         if (getenv("eth1addr")) {
643                 ret = fecmxc_initialize_multi(bis, 1, -1, ENET2_BASE_ADDR);
644                 if (ret) {
645                         printf("failed to initialize FEC1: %d\n", ret);
646                         return ret;
647                 }
648         }
649         return 0;
650 }
651
652 static void tx6_init_mac(void)
653 {
654         u8 mac[ETH_ALEN];
655
656         imx_get_mac_from_fuse(0, mac);
657         if (!is_valid_ethaddr(mac)) {
658                 printf("No valid MAC address programmed\n");
659                 return;
660         }
661
662         printf("MAC addr from fuse: %pM\n", mac);
663         eth_setenv_enetaddr("ethaddr", mac);
664
665         imx_get_mac_from_fuse(1, mac);
666         eth_setenv_enetaddr("eth1addr", mac);
667 }
668 #else
669 static inline void tx6_init_mac(void)
670 {
671 }
672 #endif /* CONFIG_FEC_MXC */
673
674 enum {
675         LED_STATE_INIT = -1,
676         LED_STATE_OFF,
677         LED_STATE_ON,
678 };
679
680 static inline int calc_blink_rate(void)
681 {
682         if (!tx6_temp_check_enabled)
683                 return CONFIG_SYS_HZ;
684
685         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
686                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
687                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
688 }
689
690 void show_activity(int arg)
691 {
692         static int led_state = LED_STATE_INIT;
693         static int blink_rate;
694         static ulong last;
695
696         if (led_state == LED_STATE_INIT) {
697                 last = get_timer(0);
698                 gpio_set_value(TX6UL_LED_GPIO, 1);
699                 led_state = LED_STATE_ON;
700                 blink_rate = calc_blink_rate();
701         } else {
702                 if (get_timer(last) > blink_rate) {
703                         blink_rate = calc_blink_rate();
704                         last = get_timer_masked();
705                         if (led_state == LED_STATE_ON) {
706                                 gpio_set_value(TX6UL_LED_GPIO, 0);
707                         } else {
708                                 gpio_set_value(TX6UL_LED_GPIO, 1);
709                         }
710                         led_state = 1 - led_state;
711                 }
712         }
713 }
714
715 static const iomux_v3_cfg_t stk5_pads[] = {
716         /* SW controlled LED on STK5 baseboard */
717         MX6_PAD_SNVS_TAMPER9__GPIO5_IO09,
718
719         /* I2C bus on DIMM pins 40/41 */
720         MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
721         MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
722
723         /* TSC200x PEN IRQ */
724         MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL),
725 #if 0
726         /* EDT-FT5x06 Polytouch panel */
727         MX6_PAD_NAND_CS2__GPIO6_IO15 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* IRQ */
728         MX6_PAD_EIM_A16__GPIO2_IO22 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* RESET */
729         MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* WAKE */
730
731         /* USBH1 */
732         MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
733         MX6_PAD_EIM_D30__GPIO3_IO30 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
734         /* USBOTG */
735         MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* USBOTG ID */
736         MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
737         MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
738 #endif
739 };
740
741 static const struct gpio stk5_gpios[] = {
742         { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
743
744         { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
745         { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
746         { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
747         { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
748         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
749 };
750
751 #ifdef CONFIG_LCD
752 static u16 tx6_cmap[256];
753 vidinfo_t panel_info = {
754         /* set to max. size supported by SoC */
755         .vl_col = 4096,
756         .vl_row = 1024,
757
758         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
759         .cmap = tx6_cmap,
760 };
761
762 static struct fb_videomode tx6_fb_modes[] = {
763 #ifndef CONFIG_SYS_LVDS_IF
764         {
765                 /* Standard VGA timing */
766                 .name           = "VGA",
767                 .refresh        = 60,
768                 .xres           = 640,
769                 .yres           = 480,
770                 .pixclock       = KHZ2PICOS(25175),
771                 .left_margin    = 48,
772                 .hsync_len      = 96,
773                 .right_margin   = 16,
774                 .upper_margin   = 31,
775                 .vsync_len      = 2,
776                 .lower_margin   = 12,
777                 .sync           = FB_SYNC_CLK_LAT_FALL,
778         },
779         {
780                 /* Emerging ETV570 640 x 480 display. Syncs low active,
781                  * DE high active, 115.2 mm x 86.4 mm display area
782                  * VGA compatible timing
783                  */
784                 .name           = "ETV570",
785                 .refresh        = 60,
786                 .xres           = 640,
787                 .yres           = 480,
788                 .pixclock       = KHZ2PICOS(25175),
789                 .left_margin    = 114,
790                 .hsync_len      = 30,
791                 .right_margin   = 16,
792                 .upper_margin   = 32,
793                 .vsync_len      = 3,
794                 .lower_margin   = 10,
795                 .sync           = FB_SYNC_CLK_LAT_FALL,
796         },
797         {
798                 /* Emerging ET0350G0DH6 320 x 240 display.
799                  * 70.08 mm x 52.56 mm display area.
800                  */
801                 .name           = "ET0350",
802                 .refresh        = 60,
803                 .xres           = 320,
804                 .yres           = 240,
805                 .pixclock       = KHZ2PICOS(6500),
806                 .left_margin    = 68 - 34,
807                 .hsync_len      = 34,
808                 .right_margin   = 20,
809                 .upper_margin   = 18 - 3,
810                 .vsync_len      = 3,
811                 .lower_margin   = 4,
812                 .sync           = FB_SYNC_CLK_LAT_FALL,
813         },
814         {
815                 /* Emerging ET0430G0DH6 480 x 272 display.
816                  * 95.04 mm x 53.856 mm display area.
817                  */
818                 .name           = "ET0430",
819                 .refresh        = 60,
820                 .xres           = 480,
821                 .yres           = 272,
822                 .pixclock       = KHZ2PICOS(9000),
823                 .left_margin    = 2,
824                 .hsync_len      = 41,
825                 .right_margin   = 2,
826                 .upper_margin   = 2,
827                 .vsync_len      = 10,
828                 .lower_margin   = 2,
829         },
830         {
831                 /* Emerging ET0500G0DH6 800 x 480 display.
832                  * 109.6 mm x 66.4 mm display area.
833                  */
834                 .name           = "ET0500",
835                 .refresh        = 60,
836                 .xres           = 800,
837                 .yres           = 480,
838                 .pixclock       = KHZ2PICOS(33260),
839                 .left_margin    = 216 - 128,
840                 .hsync_len      = 128,
841                 .right_margin   = 1056 - 800 - 216,
842                 .upper_margin   = 35 - 2,
843                 .vsync_len      = 2,
844                 .lower_margin   = 525 - 480 - 35,
845                 .sync           = FB_SYNC_CLK_LAT_FALL,
846         },
847         {
848                 /* Emerging ETQ570G0DH6 320 x 240 display.
849                  * 115.2 mm x 86.4 mm display area.
850                  */
851                 .name           = "ETQ570",
852                 .refresh        = 60,
853                 .xres           = 320,
854                 .yres           = 240,
855                 .pixclock       = KHZ2PICOS(6400),
856                 .left_margin    = 38,
857                 .hsync_len      = 30,
858                 .right_margin   = 30,
859                 .upper_margin   = 16, /* 15 according to datasheet */
860                 .vsync_len      = 3, /* TVP -> 1>x>5 */
861                 .lower_margin   = 4, /* 4.5 according to datasheet */
862                 .sync           = FB_SYNC_CLK_LAT_FALL,
863         },
864         {
865                 /* Emerging ET0700G0DH6 800 x 480 display.
866                  * 152.4 mm x 91.44 mm display area.
867                  */
868                 .name           = "ET0700",
869                 .refresh        = 60,
870                 .xres           = 800,
871                 .yres           = 480,
872                 .pixclock       = KHZ2PICOS(33260),
873                 .left_margin    = 216 - 128,
874                 .hsync_len      = 128,
875                 .right_margin   = 1056 - 800 - 216,
876                 .upper_margin   = 35 - 2,
877                 .vsync_len      = 2,
878                 .lower_margin   = 525 - 480 - 35,
879                 .sync           = FB_SYNC_CLK_LAT_FALL,
880         },
881         {
882                 /* Emerging ET070001DM6 800 x 480 display.
883                  * 152.4 mm x 91.44 mm display area.
884                  */
885                 .name           = "ET070001DM6",
886                 .refresh        = 60,
887                 .xres           = 800,
888                 .yres           = 480,
889                 .pixclock       = KHZ2PICOS(33260),
890                 .left_margin    = 216 - 128,
891                 .hsync_len      = 128,
892                 .right_margin   = 1056 - 800 - 216,
893                 .upper_margin   = 35 - 2,
894                 .vsync_len      = 2,
895                 .lower_margin   = 525 - 480 - 35,
896                 .sync           = 0,
897         },
898 #else
899         {
900                 /* HannStar HSD100PXN1
901                  * 202.7m mm x 152.06 mm display area.
902                  */
903                 .name           = "HSD100PXN1",
904                 .refresh        = 60,
905                 .xres           = 1024,
906                 .yres           = 768,
907                 .pixclock       = KHZ2PICOS(65000),
908                 .left_margin    = 0,
909                 .hsync_len      = 0,
910                 .right_margin   = 320,
911                 .upper_margin   = 0,
912                 .vsync_len      = 0,
913                 .lower_margin   = 38,
914                 .sync           = FB_SYNC_CLK_LAT_FALL,
915         },
916 #endif
917         {
918                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
919                 .refresh        = 60,
920                 .left_margin    = 48,
921                 .hsync_len      = 96,
922                 .right_margin   = 16,
923                 .upper_margin   = 31,
924                 .vsync_len      = 2,
925                 .lower_margin   = 12,
926                 .sync           = FB_SYNC_CLK_LAT_FALL,
927         },
928 };
929
930 static int lcd_enabled = 1;
931 static int lcd_bl_polarity;
932
933 static int lcd_backlight_polarity(void)
934 {
935         return lcd_bl_polarity;
936 }
937
938 void lcd_enable(void)
939 {
940         /* HACK ALERT:
941          * global variable from common/lcd.c
942          * Set to 0 here to prevent messages from going to LCD
943          * rather than serial console
944          */
945         lcd_is_enabled = 0;
946
947         if (lcd_enabled) {
948                 karo_load_splashimage(1);
949
950                 debug("Switching LCD on\n");
951                 gpio_set_value(TX6UL_LCD_PWR_GPIO, 1);
952                 udelay(100);
953                 gpio_set_value(TX6UL_LCD_RST_GPIO, 1);
954                 udelay(300000);
955                 gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
956                         lcd_backlight_polarity());
957         }
958 }
959
960 void lcd_disable(void)
961 {
962         if (lcd_enabled) {
963                 printf("Disabling LCD\n");
964                 panel_info.vl_row = 0;
965                 lcd_enabled = 0;
966         }
967 }
968
969 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
970 #if 1
971         /* LCD RESET */
972         MX6_PAD_LCD_RESET__LCDIF_RESET,
973         /* LCD POWER_ENABLE */
974         MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
975         /* LCD Backlight (PWM) */
976         MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
977 #endif
978 #ifdef CONFIG_LCD
979         /* Display */
980         MX6_PAD_LCD_DATA00__LCDIF_DATA00,
981         MX6_PAD_LCD_DATA01__LCDIF_DATA01,
982         MX6_PAD_LCD_DATA02__LCDIF_DATA02,
983         MX6_PAD_LCD_DATA03__LCDIF_DATA03,
984         MX6_PAD_LCD_DATA04__LCDIF_DATA04,
985         MX6_PAD_LCD_DATA05__LCDIF_DATA05,
986         MX6_PAD_LCD_DATA06__LCDIF_DATA06,
987         MX6_PAD_LCD_DATA07__LCDIF_DATA07,
988         MX6_PAD_LCD_DATA08__LCDIF_DATA08,
989         MX6_PAD_LCD_DATA09__LCDIF_DATA09,
990         MX6_PAD_LCD_DATA10__LCDIF_DATA10,
991         MX6_PAD_LCD_DATA11__LCDIF_DATA11,
992         MX6_PAD_LCD_DATA12__LCDIF_DATA12,
993         MX6_PAD_LCD_DATA13__LCDIF_DATA13,
994         MX6_PAD_LCD_DATA14__LCDIF_DATA14,
995         MX6_PAD_LCD_DATA15__LCDIF_DATA15,
996         MX6_PAD_LCD_DATA16__LCDIF_DATA16,
997         MX6_PAD_LCD_DATA17__LCDIF_DATA17,
998         MX6_PAD_LCD_DATA18__LCDIF_DATA18,
999         MX6_PAD_LCD_DATA19__LCDIF_DATA19,
1000         MX6_PAD_LCD_DATA20__LCDIF_DATA20,
1001         MX6_PAD_LCD_DATA21__LCDIF_DATA21,
1002         MX6_PAD_LCD_DATA22__LCDIF_DATA22,
1003         MX6_PAD_LCD_DATA23__LCDIF_DATA23,
1004         MX6_PAD_LCD_HSYNC__LCDIF_HSYNC, /* HSYNC */
1005         MX6_PAD_LCD_VSYNC__LCDIF_VSYNC, /* VSYNC */
1006         MX6_PAD_LCD_ENABLE__LCDIF_ENABLE, /* OE_ACD */
1007         MX6_PAD_LCD_CLK__LCDIF_CLK, /* LSCLK */
1008 #endif
1009 };
1010
1011 static const struct gpio stk5_lcd_gpios[] = {
1012         { TX6UL_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1013         { TX6UL_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1014         { TX6UL_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1015 };
1016
1017 void lcd_ctrl_init(void *lcdbase)
1018 {
1019         int color_depth = 24;
1020         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1021         const char *vm;
1022         unsigned long val;
1023         int refresh = 60;
1024         struct fb_videomode *p = &tx6_fb_modes[0];
1025         struct fb_videomode fb_mode;
1026         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1027
1028         if (!lcd_enabled) {
1029                 debug("LCD disabled\n");
1030                 return;
1031         }
1032
1033         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1034                 lcd_disable();
1035                 setenv("splashimage", NULL);
1036                 return;
1037         }
1038
1039         karo_fdt_move_fdt();
1040         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1041
1042         if (video_mode == NULL) {
1043                 lcd_disable();
1044                 return;
1045         }
1046         vm = video_mode;
1047         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1048                 p = &fb_mode;
1049                 debug("Using video mode from FDT\n");
1050                 vm += strlen(vm);
1051                 if (fb_mode.xres > panel_info.vl_col ||
1052                         fb_mode.yres > panel_info.vl_row) {
1053                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1054                                 fb_mode.xres, fb_mode.yres,
1055                                 panel_info.vl_col, panel_info.vl_row);
1056                         lcd_enabled = 0;
1057                         return;
1058                 }
1059         }
1060         if (p->name != NULL)
1061                 debug("Trying compiled-in video modes\n");
1062         while (p->name != NULL) {
1063                 if (strcmp(p->name, vm) == 0) {
1064                         debug("Using video mode: '%s'\n", p->name);
1065                         vm += strlen(vm);
1066                         break;
1067                 }
1068                 p++;
1069         }
1070         if (*vm != '\0')
1071                 debug("Trying to decode video_mode: '%s'\n", vm);
1072         while (*vm != '\0') {
1073                 if (*vm >= '0' && *vm <= '9') {
1074                         char *end;
1075
1076                         val = simple_strtoul(vm, &end, 0);
1077                         if (end > vm) {
1078                                 if (!xres_set) {
1079                                         if (val > panel_info.vl_col)
1080                                                 val = panel_info.vl_col;
1081                                         p->xres = val;
1082                                         panel_info.vl_col = val;
1083                                         xres_set = 1;
1084                                 } else if (!yres_set) {
1085                                         if (val > panel_info.vl_row)
1086                                                 val = panel_info.vl_row;
1087                                         p->yres = val;
1088                                         panel_info.vl_row = val;
1089                                         yres_set = 1;
1090                                 } else if (!bpp_set) {
1091                                         switch (val) {
1092                                         case 8:
1093                                         case 16:
1094                                         case 18:
1095                                         case 24:
1096                                         case 32:
1097                                                 color_depth = val;
1098                                                 break;
1099
1100                                         default:
1101                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1102                                                         end - vm, vm, color_depth);
1103                                         }
1104                                         bpp_set = 1;
1105                                 } else if (!refresh_set) {
1106                                         refresh = val;
1107                                         refresh_set = 1;
1108                                 }
1109                         }
1110                         vm = end;
1111                 }
1112                 switch (*vm) {
1113                 case '@':
1114                         bpp_set = 1;
1115                         /* fallthru */
1116                 case '-':
1117                         yres_set = 1;
1118                         /* fallthru */
1119                 case 'x':
1120                         xres_set = 1;
1121                         /* fallthru */
1122                 case 'M':
1123                 case 'R':
1124                         vm++;
1125                         break;
1126
1127                 default:
1128                         if (*vm != '\0')
1129                                 vm++;
1130                 }
1131         }
1132         if (p->xres == 0 || p->yres == 0) {
1133                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1134                 lcd_enabled = 0;
1135                 printf("Supported video modes are:");
1136                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1137                         printf(" %s", p->name);
1138                 }
1139                 printf("\n");
1140                 return;
1141         }
1142         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1143                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1144                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1145                 lcd_enabled = 0;
1146                 return;
1147         }
1148         panel_info.vl_col = p->xres;
1149         panel_info.vl_row = p->yres;
1150
1151         switch (color_depth) {
1152         case 8:
1153                 panel_info.vl_bpix = LCD_COLOR8;
1154                 break;
1155         case 16:
1156                 panel_info.vl_bpix = LCD_COLOR16;
1157                 break;
1158         default:
1159                 panel_info.vl_bpix = LCD_COLOR32;
1160         }
1161
1162         p->pixclock = KHZ2PICOS(refresh *
1163                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1164                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1165                                 1000);
1166         debug("Pixel clock set to %lu.%03lu MHz\n",
1167                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1168
1169         if (p != &fb_mode) {
1170                 int ret;
1171
1172                 debug("Creating new display-timing node from '%s'\n",
1173                         video_mode);
1174                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1175                 if (ret)
1176                         printf("Failed to create new display-timing node from '%s': %d\n",
1177                                 video_mode, ret);
1178         }
1179
1180         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1181         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1182                                         ARRAY_SIZE(stk5_lcd_pads));
1183
1184         debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
1185                 color_depth, refresh);
1186
1187         if (karo_load_splashimage(0) == 0) {
1188                 char vmode[128];
1189
1190                 /* setup env variable for mxsfb display driver */
1191                 snprintf(vmode, sizeof(vmode),
1192                         "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
1193                         p->xres, p->yres, p->left_margin, p->right_margin,
1194                         p->upper_margin, p->lower_margin, p->hsync_len,
1195                         p->vsync_len, p->sync, p->pixclock, color_depth);
1196                 setenv("videomode", vmode);
1197
1198                 debug("Initializing LCD controller\n");
1199                 lcdif_clk_enable();
1200                 video_hw_init();
1201                 setenv("videomode", NULL);
1202         } else {
1203                 debug("Skipping initialization of LCD controller\n");
1204         }
1205 }
1206 #else
1207 #define lcd_enabled 0
1208 #endif /* CONFIG_LCD */
1209
1210 static void stk5_board_init(void)
1211 {
1212         int ret;
1213
1214         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1215         if (ret < 0) {
1216                 printf("Failed to request stk5_gpios: %d\n", ret);
1217                 return;
1218         }
1219         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1220         debug("%s@%d: \n", __func__, __LINE__);
1221 }
1222
1223 static void stk5v3_board_init(void)
1224 {
1225         debug("%s@%d: \n", __func__, __LINE__);
1226         stk5_board_init();
1227         debug("%s@%d: \n", __func__, __LINE__);
1228 }
1229
1230 static void stk5v5_board_init(void)
1231 {
1232         int ret;
1233
1234         stk5_board_init();
1235
1236         ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
1237                         "Flexcan Transceiver");
1238         if (ret) {
1239                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1240                 return;
1241         }
1242
1243         imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 |
1244                         MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL));
1245 }
1246
1247 static void tx6ul_set_cpu_clock(void)
1248 {
1249         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1250
1251         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1252                 return;
1253
1254         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1255                 printf("%s detected; skipping cpu clock change\n",
1256                         (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1257                 return;
1258         }
1259         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1260                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1261                 printf("CPU clock set to %lu.%03lu MHz\n",
1262                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1263         } else {
1264                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1265         }
1266 }
1267
1268 int board_late_init(void)
1269 {
1270         int ret = 0;
1271         const char *baseboard;
1272
1273         debug("%s@%d: \n", __func__, __LINE__);
1274
1275         env_cleanup();
1276
1277         if (tx6_temp_check_enabled)
1278                 check_cpu_temperature(1);
1279
1280         tx6ul_set_cpu_clock();
1281
1282         if (had_ctrlc())
1283                 setenv_ulong("safeboot", 1);
1284         else if (wrsr & WRSR_TOUT)
1285                 setenv_ulong("wdreset", 1);
1286         else
1287                 karo_fdt_move_fdt();
1288
1289         baseboard = getenv("baseboard");
1290         if (!baseboard)
1291                 goto exit;
1292
1293         printf("Baseboard: %s\n", baseboard);
1294
1295         if (strncmp(baseboard, "stk5", 4) == 0) {
1296                 if ((strlen(baseboard) == 4) ||
1297                         strcmp(baseboard, "stk5-v3") == 0) {
1298                         stk5v3_board_init();
1299                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1300                         const char *otg_mode = getenv("otg_mode");
1301
1302                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1303                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1304                                         otg_mode, baseboard);
1305                                 setenv("otg_mode", "none");
1306                         }
1307                         stk5v5_board_init();
1308                 } else {
1309                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1310                                 baseboard + 4);
1311                 }
1312         } else {
1313                 printf("WARNING: Unsupported baseboard: '%s'\n",
1314                         baseboard);
1315                 ret = -EINVAL;
1316         }
1317
1318 exit:
1319         debug("%s@%d: \n", __func__, __LINE__);
1320         tx6_init_mac();
1321         debug("%s@%d: \n", __func__, __LINE__);
1322
1323         clear_ctrlc();
1324         return ret;
1325 }
1326
1327 #ifdef CONFIG_SERIAL_TAG
1328 void get_board_serial(struct tag_serialnr *serialnr)
1329 {
1330         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1331         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1332
1333         serialnr->low = readl(&fuse->cfg0);
1334         serialnr->high = readl(&fuse->cfg1);
1335 }
1336 #endif
1337
1338 #if defined(CONFIG_OF_BOARD_SETUP)
1339 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1340 #include <jffs2/jffs2.h>
1341 #include <mtd_node.h>
1342 static struct node_info nodes[] = {
1343         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1344 };
1345 #else
1346 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1347 #endif
1348
1349 static const char *tx6_touchpanels[] = {
1350         "ti,tsc2007",
1351         "edt,edt-ft5x06",
1352         "eeti,egalax_ts",
1353 };
1354
1355 int ft_board_setup(void *blob, bd_t *bd)
1356 {
1357         const char *baseboard = getenv("baseboard");
1358         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1359         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1360         int ret;
1361
1362         ret = fdt_increase_size(blob, 4096);
1363         if (ret) {
1364                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1365                 return ret;
1366         }
1367         if (stk5_v5)
1368                 karo_fdt_enable_node(blob, "stk5led", 0);
1369
1370         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1371
1372         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1373                                 ARRAY_SIZE(tx6_touchpanels));
1374         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1375         karo_fdt_fixup_flexcan(blob, stk5_v5);
1376
1377         karo_fdt_update_fb_mode(blob, video_mode);
1378
1379         return 0;
1380 }
1381 #endif /* CONFIG_OF_BOARD_SETUP */