2 * Copyright (C) 2015 Lothar Waßmann <LW@KARO-electronics.de>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <fdt_support.h>
14 #include <fsl_esdhc.h>
22 #include <asm/arch/mx6-pins.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/hab.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/crm_regs.h>
27 #include <asm/arch/sys_proto.h>
29 #include "../common/karo.h"
32 #define __data __attribute__((section(".data")))
34 #define TX6UL_FEC_RST_GPIO IMX_GPIO_NR(5, 6)
35 #define TX6UL_FEC_PWR_GPIO IMX_GPIO_NR(5, 7)
36 #define TX6UL_FEC_INT_GPIO IMX_GPIO_NR(5, 5)
38 #define TX6UL_FEC2_RST_GPIO IMX_GPIO_NR(4, 28)
39 #define TX6UL_FEC2_INT_GPIO IMX_GPIO_NR(4, 27)
41 #define TX6UL_LED_GPIO IMX_GPIO_NR(5, 9)
43 #define TX6UL_LCD_PWR_GPIO IMX_GPIO_NR(5, 4)
44 #define TX6UL_LCD_RST_GPIO IMX_GPIO_NR(3, 4)
45 #define TX6UL_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(4, 16)
47 #ifdef CONFIG_SYS_I2C_SOFT
48 #define TX6UL_I2C1_SCL_GPIO CONFIG_SOFT_I2C_GPIO_SCL
49 #define TX6UL_I2C1_SDA_GPIO CONFIG_SOFT_I2C_GPIO_SDA
52 #define TX6UL_SD1_CD_GPIO IMX_GPIO_NR(4, 14)
54 #ifdef CONFIG_MX6_TEMPERATURE_MIN
55 #define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN
57 #define TEMPERATURE_MIN (-40)
59 #ifdef CONFIG_MX6_TEMPERATURE_HOT
60 #define TEMPERATURE_HOT CONFIG_MX6_TEMPERATURE_HOT
62 #define TEMPERATURE_HOT 80
65 DECLARE_GLOBAL_DATA_PTR;
67 #define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
69 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
70 #ifdef CONFIG_SECURE_BOOT
71 char __csf_data[0] __attribute__((section(".__csf_data")));
74 #define TX6UL_DEFAULT_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP | \
78 #define TX6UL_I2C_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | \
84 #define TX6UL_ENET_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH | \
85 PAD_CTL_DSE_120ohm | \
86 PAD_CTL_PUS_100K_UP | \
88 #define TX6UL_GPIO_OUT_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_LOW | \
91 #define TX6UL_GPIO_IN_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_LOW | \
95 static const iomux_v3_cfg_t const tx6ul_pads[] = {
97 #if CONFIG_MXC_UART_BASE == UART1_BASE
98 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
99 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
100 MX6_PAD_UART1_RTS_B__UART1_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
101 MX6_PAD_UART1_CTS_B__UART1_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
103 #if CONFIG_MXC_UART_BASE == UART2_BASE
104 MX6_PAD_UART2_TX_DATA__UART2_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
105 MX6_PAD_UART2_RX_DATA__UART2_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
106 MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
107 MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
109 #if CONFIG_MXC_UART_BASE == UART5_BASE
110 MX6_PAD_GPIO1_IO04__UART5_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
111 MX6_PAD_GPIO1_IO05__UART5_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
112 MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
113 MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
115 /* FEC PHY GPIO functions */
116 MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY POWER */
117 MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY RESET */
118 MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | TX6UL_GPIO_IN_PAD_CTRL, /* PHY INT */
121 static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = {
123 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm |
125 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
128 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |
132 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | TX6UL_ENET_PAD_CTRL,
133 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | TX6UL_ENET_PAD_CTRL,
134 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | TX6UL_ENET_PAD_CTRL,
135 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | TX6UL_ENET_PAD_CTRL,
136 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | TX6UL_ENET_PAD_CTRL,
137 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | TX6UL_ENET_PAD_CTRL,
138 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | TX6UL_ENET_PAD_CTRL,
141 static const iomux_v3_cfg_t const tx6ul_enet2_pads[] = {
142 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |
145 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | TX6UL_ENET_PAD_CTRL,
146 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | TX6UL_ENET_PAD_CTRL,
147 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | TX6UL_ENET_PAD_CTRL,
148 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | TX6UL_ENET_PAD_CTRL,
149 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | TX6UL_ENET_PAD_CTRL,
150 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | TX6UL_ENET_PAD_CTRL,
151 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | TX6UL_ENET_PAD_CTRL,
154 static const iomux_v3_cfg_t const tx6ul_i2c_pads[] = {
156 MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
157 TX6UL_I2C_PAD_CTRL, /* I2C SCL */
158 MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
159 TX6UL_I2C_PAD_CTRL, /* I2C SDA */
162 static const struct gpio const tx6ul_gpios[] = {
163 #ifdef CONFIG_SYS_I2C_SOFT
164 /* These two entries are used to forcefully reinitialize the I2C bus */
165 { TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
166 { TX6UL_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
168 { TX6UL_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
169 { TX6UL_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
170 { TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
173 static const struct gpio const tx6ul_fec2_gpios[] = {
174 { TX6UL_FEC2_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC2 PHY RESET", },
175 { TX6UL_FEC2_INT_GPIO, GPIOFLAG_INPUT, "FEC2 PHY INT", },
182 /* run with default environment */
183 #if defined(TX6UL_I2C1_SCL_GPIO) && defined(TX6UL_I2C1_SDA_GPIO)
184 #define SCL_BANK (TX6UL_I2C1_SCL_GPIO / 32)
185 #define SDA_BANK (TX6UL_I2C1_SDA_GPIO / 32)
186 #define SCL_BIT (1 << (TX6UL_I2C1_SCL_GPIO % 32))
187 #define SDA_BIT (1 << (TX6UL_I2C1_SDA_GPIO % 32))
189 static void * const gpio_ports[] = {
190 (void *)GPIO1_BASE_ADDR,
191 (void *)GPIO2_BASE_ADDR,
192 (void *)GPIO3_BASE_ADDR,
193 (void *)GPIO4_BASE_ADDR,
194 (void *)GPIO5_BASE_ADDR,
197 static void tx6ul_i2c_recover(void)
201 struct gpio_regs *scl_regs = gpio_ports[SCL_BANK];
202 struct gpio_regs *sda_regs = gpio_ports[SDA_BANK];
204 if ((readl(&scl_regs->gpio_psr) & SCL_BIT) &&
205 (readl(&sda_regs->gpio_psr) & SDA_BIT))
208 debug("Clearing I2C bus\n");
209 if (!(readl(&scl_regs->gpio_psr) & SCL_BIT)) {
210 printf("I2C SCL stuck LOW\n");
213 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
214 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
216 imx_iomux_v3_setup_pad(MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 |
217 MUX_CFG_SION | TX6UL_GPIO_OUT_PAD_CTRL);
219 if (!(readl(&sda_regs->gpio_psr) & SDA_BIT)) {
220 printf("I2C SDA stuck LOW\n");
223 clrbits_le32(&sda_regs->gpio_dir, SDA_BIT);
224 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
225 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
229 for (i = 0; i < 18; i++) {
230 u32 reg = readl(&scl_regs->gpio_dr) ^ SCL_BIT;
232 debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
233 writel(reg, &scl_regs->gpio_dr);
236 if (readl(&sda_regs->gpio_psr) & SDA_BIT)
238 if (!(readl(&scl_regs->gpio_psr) & SCL_BIT))
245 bool scl = !!(readl(&scl_regs->gpio_psr) & SCL_BIT);
246 bool sda = !!(readl(&sda_regs->gpio_psr) & SDA_BIT);
249 printf("I2C bus recovery succeeded\n");
251 printf("I2C bus recovery FAILED: SCL: %d SDA: %d\n",
254 imx_iomux_v3_setup_multiple_pads(tx6ul_i2c_pads,
255 ARRAY_SIZE(tx6ul_i2c_pads));
259 static inline void tx6ul_i2c_recover(void)
264 /* placed in section '.data' to prevent overwriting relocation info
267 static u32 wrsr __data;
269 #define WRSR_POR (1 << 4)
270 #define WRSR_TOUT (1 << 1)
271 #define WRSR_SFTW (1 << 0)
273 static void print_reset_cause(void)
275 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
276 void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
280 printf("Reset cause: ");
282 srsr = readl(&src_regs->srsr);
283 wrsr = readw(wdt_base + 4);
285 if (wrsr & WRSR_POR) {
286 printf("%sPOR", dlm);
289 if (srsr & 0x00004) {
290 printf("%sCSU", dlm);
293 if (srsr & 0x00008) {
294 printf("%sIPP USER", dlm);
297 if (srsr & 0x00010) {
298 if (wrsr & WRSR_SFTW) {
299 printf("%sSOFT", dlm);
302 if (wrsr & WRSR_TOUT) {
303 printf("%sWDOG", dlm);
307 if (srsr & 0x00020) {
308 printf("%sJTAG HIGH-Z", dlm);
311 if (srsr & 0x00040) {
312 printf("%sJTAG SW", dlm);
315 if (srsr & 0x10000) {
316 printf("%sWARM BOOT", dlm);
325 #ifdef CONFIG_IMX6_THERMAL
327 #include <imx_thermal.h>
330 static void print_temperature(void)
332 struct udevice *thermal_dev;
333 int cpu_tmp, minc, maxc, ret;
334 char const *grade_str;
335 static u32 __data thermal_calib;
337 puts("Temperature: ");
338 switch (get_cpu_temp_grade(&minc, &maxc)) {
339 case TEMP_AUTOMOTIVE:
340 grade_str = "Automotive";
342 case TEMP_INDUSTRIAL:
343 grade_str = "Industrial";
345 case TEMP_EXTCOMMERCIAL:
346 grade_str = "Extended Commercial";
349 grade_str = "Commercial";
351 printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
352 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
354 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
357 printf(" at %dC", cpu_tmp);
359 puts(" - failed to read sensor data");
361 puts(" - no sensor device found");
364 if (fuse_read(1, 6, &thermal_calib) == 0) {
365 printf(" - calibration data 0x%08x\n", thermal_calib);
367 puts(" - Failed to read thermal calib fuse\n");
371 static inline void print_temperature(void)
378 u32 cpurev = get_cpu_rev();
381 if (is_cpu_type(MXC_CPU_MX6SL))
383 else if (is_cpu_type(MXC_CPU_MX6DL))
385 else if (is_cpu_type(MXC_CPU_MX6SOLO))
387 else if (is_cpu_type(MXC_CPU_MX6Q))
389 else if (is_cpu_type(MXC_CPU_MX6UL))
391 else if (is_cpu_type(MXC_CPU_MX6ULL))
394 printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n",
396 (cpurev & 0x000F0) >> 4,
397 (cpurev & 0x0000F) >> 0,
398 mxc_get_clock(MXC_ARM_CLK) / 1000000);
402 #ifdef CONFIG_MX6_TEMPERATURE_HOT
403 check_cpu_temperature(1);
409 /* serial port not initialized at this point */
410 int board_early_init_f(void)
415 #ifndef CONFIG_MX6_TEMPERATURE_HOT
416 static bool tx6ul_temp_check_enabled = true;
418 #define tx6ul_temp_check_enabled 0
421 static inline u8 tx6ul_mem_suffix(void)
423 return '0' + CONFIG_SYS_SDRAM_CHIP_SIZE / 1024 * 2 +
424 IS_ENABLED(CONFIG_TX6_EMMC);
427 #ifdef CONFIG_RN5T567
429 #define VDD_RTC_VAL rn5t_mV_to_regval_rtc(3000)
430 #define VDD_CORE_VAL rn5t_mV_to_regval(1300) /* DCDC1 */
431 #define VDD_CORE_VAL_LP rn5t_mV_to_regval(900)
432 #define VDD_DDR_VAL rn5t_mV_to_regval(1350) /* DCDC3 */
433 #define VDD_DDR_VAL_LP rn5t_mV_to_regval(1350)
434 #define VDD_IO_EXT_VAL rn5t_mV_to_regval(3300) /* DCDC4 */
435 #define VDD_IO_EXT_VAL_LP rn5t_mV_to_regval(3300)
436 #define VDD_IO_INT_VAL rn5t_mV_to_regval2(3300) /* LDO1 */
437 #define VDD_IO_INT_VAL_LP rn5t_mV_to_regval2(3300)
438 #define VDD_ADC_VAL rn5t_mV_to_regval2(3300) /* LDO2 */
439 #define VDD_ADC_VAL_LP rn5t_mV_to_regval2(3300)
440 #define VDD_PMIC_VAL rn5t_mV_to_regval2(2500) /* LDO3 */
441 #define VDD_PMIC_VAL_LP rn5t_mV_to_regval2(2500)
442 #define VDD_CSI_VAL rn5t_mV_to_regval2(1800) /* LDO4 */
443 #define VDD_CSI_VAL_LP rn5t_mV_to_regval2(1800)
445 static struct pmic_regs rn5t567_regs[] = {
446 { RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, },
447 { RN5T567_DC1DAC, VDD_CORE_VAL, },
448 { RN5T567_DC3DAC, VDD_DDR_VAL, },
449 { RN5T567_DC4DAC, VDD_IO_EXT_VAL, },
450 { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
451 { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
452 { RN5T567_DC4DAC_SLP, VDD_IO_EXT_VAL_LP, },
453 { RN5T567_DC1CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
454 { RN5T567_DC2CTL, DCnCTL_DCnDIS, },
455 { RN5T567_DC3CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
456 { RN5T567_DC4CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
457 { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
458 { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
459 { RN5T567_LDO1DAC, VDD_IO_INT_VAL, },
460 { RN5T567_LDO2DAC, VDD_ADC_VAL, },
461 { RN5T567_LDO3DAC, VDD_PMIC_VAL, },
462 { RN5T567_LDO4DAC, VDD_CSI_VAL, },
463 { RN5T567_LDOEN1, 0x0f, ~0x1f, },
464 { RN5T567_LDOEN2, 0x10, ~0x30, },
465 { RN5T567_LDODIS, 0x10, ~0x1f, },
466 { RN5T567_INTPOL, 0, },
467 { RN5T567_INTEN, 0x3, },
468 { RN5T567_IREN, 0xf, },
469 { RN5T567_EN_GPIR, 0, },
472 static int pmic_addr = 0x33;
478 u32 cpurev = get_cpu_rev();
481 if (is_cpu_type(MXC_CPU_MX6UL))
482 f = ((cpurev & 0xf0) > 0x10) ? '5' : '0';
483 else if (is_cpu_type(MXC_CPU_MX6ULL))
486 debug("%s@%d: cpurev=%08x\n", __func__, __LINE__, cpurev);
488 printf("Board: Ka-Ro TXUL-%c01%c\n", f, tx6ul_mem_suffix());
492 ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios));
494 printf("Failed to request tx6ul_gpios: %d\n", ret);
496 imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads));
498 /* Address of boot parameters */
499 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
500 gd->bd->bi_arch_number = -1;
502 if (ctrlc() || (wrsr & WRSR_TOUT)) {
503 if (wrsr & WRSR_TOUT)
504 printf("WDOG RESET detected; Skipping PMIC setup\n");
506 printf("<CTRL-C> detected; safeboot enabled\n");
507 #ifndef CONFIG_MX6_TEMPERATURE_HOT
508 tx6ul_temp_check_enabled = false;
513 ret = tx6_pmic_init(pmic_addr, rn5t567_regs, ARRAY_SIZE(rn5t567_regs));
515 printf("Failed to setup PMIC voltages: %d\n", ret);
523 debug("%s@%d: \n", __func__, __LINE__);
525 /* dram_init must store complete ramsize in gd->ram_size */
526 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
527 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
531 void dram_init_banksize(void)
533 debug("%s@%d: \n", __func__, __LINE__);
535 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
536 gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
538 #if CONFIG_NR_DRAM_BANKS > 1
539 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
540 gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
545 #ifdef CONFIG_FSL_ESDHC
546 #define TX6UL_SD_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP | \
547 PAD_CTL_SPEED_MED | \
548 PAD_CTL_DSE_40ohm | \
551 static const iomux_v3_cfg_t mmc0_pads[] = {
552 MX6_PAD_SD1_CMD__USDHC1_CMD | TX6UL_SD_PAD_CTRL,
553 MX6_PAD_SD1_CLK__USDHC1_CLK | TX6UL_SD_PAD_CTRL,
554 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | TX6UL_SD_PAD_CTRL,
555 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | TX6UL_SD_PAD_CTRL,
556 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | TX6UL_SD_PAD_CTRL,
557 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | TX6UL_SD_PAD_CTRL,
559 MX6_PAD_NAND_CE1_B__GPIO4_IO14 | TX6UL_SD_PAD_CTRL,
562 #ifdef CONFIG_TX6_EMMC
563 static const iomux_v3_cfg_t mmc1_pads[] = {
564 MX6_PAD_NAND_WE_B__USDHC2_CMD | TX6UL_SD_PAD_CTRL,
565 MX6_PAD_NAND_RE_B__USDHC2_CLK | TX6UL_SD_PAD_CTRL,
566 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | TX6UL_SD_PAD_CTRL,
567 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | TX6UL_SD_PAD_CTRL,
568 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | TX6UL_SD_PAD_CTRL,
569 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | TX6UL_SD_PAD_CTRL,
571 MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
576 static struct tx6ul_esdhc_cfg {
577 const iomux_v3_cfg_t *pads;
579 enum mxc_clock clkid;
580 struct fsl_esdhc_cfg cfg;
582 } tx6ul_esdhc_cfg[] = {
583 #ifdef CONFIG_TX6_EMMC
586 .num_pads = ARRAY_SIZE(mmc1_pads),
587 .clkid = MXC_ESDHC2_CLK,
589 .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
597 .num_pads = ARRAY_SIZE(mmc0_pads),
598 .clkid = MXC_ESDHC_CLK,
600 .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
603 .cd_gpio = TX6UL_SD1_CD_GPIO,
607 static inline struct tx6ul_esdhc_cfg *to_tx6ul_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
609 return container_of(cfg, struct tx6ul_esdhc_cfg, cfg);
612 int board_mmc_getcd(struct mmc *mmc)
614 struct tx6ul_esdhc_cfg *cfg = to_tx6ul_esdhc_cfg(mmc->priv);
616 if (cfg->cd_gpio < 0)
619 debug("SD card %d is %spresent (GPIO %d)\n",
620 cfg - tx6ul_esdhc_cfg,
621 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
623 return !gpio_get_value(cfg->cd_gpio);
626 int board_mmc_init(bd_t *bis)
630 debug("%s@%d: \n", __func__, __LINE__);
632 #ifndef CONFIG_ENV_IS_IN_MMC
633 if (!(gd->flags & GD_FLG_ENV_READY)) {
634 printf("deferred ...");
638 for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) {
640 struct tx6ul_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
643 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
644 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
646 if (cfg->cd_gpio >= 0) {
647 ret = gpio_request_one(cfg->cd_gpio,
648 GPIOFLAG_INPUT, "MMC CD");
650 printf("Error %d requesting GPIO%d_%d\n",
651 ret, cfg->cd_gpio / 32,
657 debug("%s: Initializing MMC slot %d\n", __func__, i);
658 fsl_esdhc_initialize(bis, &cfg->cfg);
660 mmc = find_mmc_device(i);
663 if (board_mmc_getcd(mmc))
668 #endif /* CONFIG_FSL_ESDHC */
677 static inline int calc_blink_rate(void)
679 if (!tx6ul_temp_check_enabled)
680 return CONFIG_SYS_HZ;
682 return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
683 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
684 (TEMPERATURE_HOT - TEMPERATURE_MIN);
687 void show_activity(int arg)
689 static int led_state = LED_STATE_INIT;
690 static int blink_rate;
700 ret = gpio_set_value(TX6UL_LED_GPIO, 1);
702 led_state = LED_STATE_ERR;
704 led_state = LED_STATE_ON;
705 blink_rate = calc_blink_rate();
710 if (get_timer(last) > blink_rate) {
711 blink_rate = calc_blink_rate();
712 last = get_timer_masked();
713 if (led_state == LED_STATE_ON) {
714 gpio_set_value(TX6UL_LED_GPIO, 0);
716 gpio_set_value(TX6UL_LED_GPIO, 1);
718 led_state = 1 - led_state;
724 static const iomux_v3_cfg_t stk5_jtag_pads[] = {
725 MX6_PAD_JTAG_MOD__SJC_MOD | TX6UL_GPIO_IN_PAD_CTRL,
726 MX6_PAD_JTAG_TCK__SJC_TCK | TX6UL_GPIO_IN_PAD_CTRL,
727 MX6_PAD_JTAG_TRST_B__SJC_TRSTB | TX6UL_GPIO_IN_PAD_CTRL,
728 MX6_PAD_JTAG_TDI__SJC_TDI | TX6UL_GPIO_IN_PAD_CTRL,
729 MX6_PAD_JTAG_TDO__SJC_TDO | TX6UL_GPIO_OUT_PAD_CTRL,
730 MX6_PAD_JTAG_TMS__SJC_TMS | TX6UL_GPIO_IN_PAD_CTRL,
733 static const iomux_v3_cfg_t stk5_pads[] = {
734 /* SW controlled LED on STK5 baseboard */
735 MX6_PAD_SNVS_TAMPER9__GPIO5_IO09,
737 /* I2C bus on DIMM pins 40/41 */
738 MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
739 MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
741 /* TSC200x PEN IRQ */
742 MX6_PAD_JTAG_TMS__GPIO1_IO11 | TX6UL_GPIO_IN_PAD_CTRL,
744 /* EDT-FT5x06 Polytouch panel */
745 MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | TX6UL_GPIO_IN_PAD_CTRL, /* IRQ */
746 MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 | TX6UL_GPIO_OUT_PAD_CTRL, /* RESET */
747 MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | TX6UL_GPIO_OUT_PAD_CTRL, /* WAKE */
750 MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
751 MX6_PAD_GPIO1_IO03__USB_OTG2_OC | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
754 MX6_PAD_UART3_CTS_B__GPIO1_IO26 | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
755 MX6_PAD_UART3_RTS_B__GPIO1_IO27 | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
758 static const struct gpio stk5_gpios[] = {
759 { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
761 { IMX_GPIO_NR(1, 27), GPIOFLAG_INPUT, "USBOTG OC", },
762 { IMX_GPIO_NR(1, 26), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
766 vidinfo_t panel_info = {
767 /* set to max. size supported by SoC */
771 .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
774 static struct fb_videomode tx6ul_fb_modes[] = {
775 #ifndef CONFIG_SYS_LVDS_IF
777 /* Standard VGA timing */
782 .pixclock = KHZ2PICOS(25175),
789 .sync = FB_SYNC_CLK_LAT_FALL,
792 /* Emerging ETV570 640 x 480 display. Syncs low active,
793 * DE high active, 115.2 mm x 86.4 mm display area
794 * VGA compatible timing
800 .pixclock = KHZ2PICOS(25175),
807 .sync = FB_SYNC_CLK_LAT_FALL,
810 /* Emerging ET0350G0DH6 320 x 240 display.
811 * 70.08 mm x 52.56 mm display area.
817 .pixclock = KHZ2PICOS(6500),
818 .left_margin = 68 - 34,
821 .upper_margin = 18 - 3,
824 .sync = FB_SYNC_CLK_LAT_FALL,
827 /* Emerging ET0430G0DH6 480 x 272 display.
828 * 95.04 mm x 53.856 mm display area.
834 .pixclock = KHZ2PICOS(9000),
843 /* Emerging ET0500G0DH6 800 x 480 display.
844 * 109.6 mm x 66.4 mm display area.
850 .pixclock = KHZ2PICOS(33260),
851 .left_margin = 216 - 128,
853 .right_margin = 1056 - 800 - 216,
854 .upper_margin = 35 - 2,
856 .lower_margin = 525 - 480 - 35,
857 .sync = FB_SYNC_CLK_LAT_FALL,
860 /* Emerging ETQ570G0DH6 320 x 240 display.
861 * 115.2 mm x 86.4 mm display area.
867 .pixclock = KHZ2PICOS(6400),
871 .upper_margin = 16, /* 15 according to datasheet */
872 .vsync_len = 3, /* TVP -> 1>x>5 */
873 .lower_margin = 4, /* 4.5 according to datasheet */
874 .sync = FB_SYNC_CLK_LAT_FALL,
877 /* Emerging ET0700G0DH6 800 x 480 display.
878 * 152.4 mm x 91.44 mm display area.
884 .pixclock = KHZ2PICOS(33260),
885 .left_margin = 216 - 128,
887 .right_margin = 1056 - 800 - 216,
888 .upper_margin = 35 - 2,
890 .lower_margin = 525 - 480 - 35,
891 .sync = FB_SYNC_CLK_LAT_FALL,
894 /* Emerging ET070001DM6 800 x 480 display.
895 * 152.4 mm x 91.44 mm display area.
897 .name = "ET070001DM6",
901 .pixclock = KHZ2PICOS(33260),
902 .left_margin = 216 - 128,
904 .right_margin = 1056 - 800 - 216,
905 .upper_margin = 35 - 2,
907 .lower_margin = 525 - 480 - 35,
912 /* HannStar HSD100PXN1
913 * 202.7m mm x 152.06 mm display area.
915 .name = "HSD100PXN1",
919 .pixclock = KHZ2PICOS(65000),
926 .sync = FB_SYNC_CLK_LAT_FALL,
930 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
938 .sync = FB_SYNC_CLK_LAT_FALL,
942 static int lcd_enabled = 1;
943 static int lcd_bl_polarity;
945 static int lcd_backlight_polarity(void)
947 return lcd_bl_polarity;
950 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
953 MX6_PAD_LCD_RESET__GPIO3_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
954 /* LCD POWER_ENABLE */
955 MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
956 /* LCD Backlight (PWM) */
957 MX6_PAD_NAND_DQS__GPIO4_IO16 | TX6UL_GPIO_OUT_PAD_CTRL,
959 MX6_PAD_LCD_DATA00__LCDIF_DATA00,
960 MX6_PAD_LCD_DATA01__LCDIF_DATA01,
961 MX6_PAD_LCD_DATA02__LCDIF_DATA02,
962 MX6_PAD_LCD_DATA03__LCDIF_DATA03,
963 MX6_PAD_LCD_DATA04__LCDIF_DATA04,
964 MX6_PAD_LCD_DATA05__LCDIF_DATA05,
965 MX6_PAD_LCD_DATA06__LCDIF_DATA06,
966 MX6_PAD_LCD_DATA07__LCDIF_DATA07,
967 MX6_PAD_LCD_DATA08__LCDIF_DATA08,
968 MX6_PAD_LCD_DATA09__LCDIF_DATA09,
969 MX6_PAD_LCD_DATA10__LCDIF_DATA10,
970 MX6_PAD_LCD_DATA11__LCDIF_DATA11,
971 MX6_PAD_LCD_DATA12__LCDIF_DATA12,
972 MX6_PAD_LCD_DATA13__LCDIF_DATA13,
973 MX6_PAD_LCD_DATA14__LCDIF_DATA14,
974 MX6_PAD_LCD_DATA15__LCDIF_DATA15,
975 MX6_PAD_LCD_DATA16__LCDIF_DATA16,
976 MX6_PAD_LCD_DATA17__LCDIF_DATA17,
977 MX6_PAD_LCD_DATA18__LCDIF_DATA18,
978 MX6_PAD_LCD_DATA19__LCDIF_DATA19,
979 MX6_PAD_LCD_DATA20__LCDIF_DATA20,
980 MX6_PAD_LCD_DATA21__LCDIF_DATA21,
981 MX6_PAD_LCD_DATA22__LCDIF_DATA22,
982 MX6_PAD_LCD_DATA23__LCDIF_DATA23,
983 MX6_PAD_LCD_HSYNC__LCDIF_HSYNC, /* HSYNC */
984 MX6_PAD_LCD_VSYNC__LCDIF_VSYNC, /* VSYNC */
985 MX6_PAD_LCD_ENABLE__LCDIF_ENABLE, /* OE_ACD */
986 MX6_PAD_LCD_CLK__LCDIF_CLK, /* LSCLK */
990 static const struct gpio stk5_lcd_gpios[] = {
991 { TX6UL_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
992 { TX6UL_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
993 { TX6UL_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
996 /* run with valid env from NAND/eMMC */
997 void lcd_enable(void)
1000 * global variable from common/lcd.c
1001 * Set to 0 here to prevent messages from going to LCD
1002 * rather than serial console
1007 karo_load_splashimage(1);
1009 debug("Switching LCD on\n");
1010 gpio_set_value(TX6UL_LCD_PWR_GPIO, 1);
1012 gpio_set_value(TX6UL_LCD_RST_GPIO, 1);
1014 gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
1015 lcd_backlight_polarity());
1019 static void lcd_disable(void)
1022 printf("Disabling LCD\n");
1023 panel_info.vl_row = 0;
1028 void lcd_ctrl_init(void *lcdbase)
1030 int color_depth = 24;
1031 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1035 struct fb_videomode *p = &tx6ul_fb_modes[0];
1036 struct fb_videomode fb_mode;
1037 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1040 debug("LCD disabled\n");
1044 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1046 setenv("splashimage", NULL);
1050 karo_fdt_move_fdt();
1051 lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1053 if (video_mode == NULL) {
1058 if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1060 debug("Using video mode from FDT\n");
1062 if (fb_mode.xres > panel_info.vl_col ||
1063 fb_mode.yres > panel_info.vl_row) {
1064 printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1065 fb_mode.xres, fb_mode.yres,
1066 panel_info.vl_col, panel_info.vl_row);
1071 if (p->name != NULL)
1072 debug("Trying compiled-in video modes\n");
1073 while (p->name != NULL) {
1074 if (strcmp(p->name, vm) == 0) {
1075 debug("Using video mode: '%s'\n", p->name);
1082 debug("Trying to decode video_mode: '%s'\n", vm);
1083 while (*vm != '\0') {
1084 if (*vm >= '0' && *vm <= '9') {
1087 val = simple_strtoul(vm, &end, 0);
1090 if (val > panel_info.vl_col)
1091 val = panel_info.vl_col;
1093 panel_info.vl_col = val;
1095 } else if (!yres_set) {
1096 if (val > panel_info.vl_row)
1097 val = panel_info.vl_row;
1099 panel_info.vl_row = val;
1101 } else if (!bpp_set) {
1112 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1117 } else if (!refresh_set) {
1144 if (p->xres == 0 || p->yres == 0) {
1145 printf("Invalid video mode: %s\n", getenv("video_mode"));
1147 printf("Supported video modes are:");
1148 for (p = &tx6ul_fb_modes[0]; p->name != NULL; p++) {
1149 printf(" %s", p->name);
1154 if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1155 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1156 p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1160 panel_info.vl_col = p->xres;
1161 panel_info.vl_row = p->yres;
1163 switch (color_depth) {
1165 panel_info.vl_bpix = LCD_COLOR8;
1168 panel_info.vl_bpix = LCD_COLOR16;
1171 panel_info.vl_bpix = LCD_COLOR32;
1174 p->pixclock = KHZ2PICOS(refresh *
1175 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1176 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1178 debug("Pixel clock set to %lu.%03lu MHz\n",
1179 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1181 if (p != &fb_mode) {
1184 debug("Creating new display-timing node from '%s'\n",
1186 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1188 printf("Failed to create new display-timing node from '%s': %d\n",
1192 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1193 imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1194 ARRAY_SIZE(stk5_lcd_pads));
1196 debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
1197 color_depth, refresh);
1199 if (karo_load_splashimage(0) == 0) {
1202 /* setup env variable for mxsfb display driver */
1203 snprintf(vmode, sizeof(vmode),
1204 "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
1205 p->xres, p->yres, p->left_margin, p->right_margin,
1206 p->upper_margin, p->lower_margin, p->hsync_len,
1207 p->vsync_len, p->sync, p->pixclock, color_depth);
1208 setenv("videomode", vmode);
1210 debug("Initializing LCD controller\n");
1213 setenv("videomode", NULL);
1215 debug("Skipping initialization of LCD controller\n");
1219 #define lcd_enabled 0
1220 #endif /* CONFIG_LCD */
1222 #ifndef CONFIG_ENV_IS_IN_MMC
1223 static void tx6ul_mmc_init(void)
1226 if (board_mmc_init(gd->bd) < 0)
1227 cpu_mmc_init(gd->bd);
1228 print_mmc_devices(',');
1231 static inline void tx6ul_mmc_init(void)
1236 static void stk5_board_init(void)
1240 ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1242 printf("Failed to request stk5_gpios: %d\n", ret);
1246 imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1247 if (getenv_yesno("jtag_enable") != 0) {
1248 /* true if unset or set to one of: 'yYtT1' */
1249 imx_iomux_v3_setup_multiple_pads(stk5_jtag_pads, ARRAY_SIZE(stk5_jtag_pads));
1252 debug("%s@%d: \n", __func__, __LINE__);
1255 static void stk5v3_board_init(void)
1257 debug("%s@%d: \n", __func__, __LINE__);
1259 debug("%s@%d: \n", __func__, __LINE__);
1263 static void stk5v5_board_init(void)
1270 ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
1271 "Flexcan Transceiver");
1273 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1277 imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 |
1278 TX6UL_GPIO_OUT_PAD_CTRL);
1281 static void tx6ul_set_cpu_clock(void)
1283 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1285 if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1288 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1289 printf("%s detected; skipping cpu clock change\n",
1290 (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1293 if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1294 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1295 printf("CPU clock set to %lu.%03lu MHz\n",
1296 cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1298 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1302 int board_late_init(void)
1304 const char *baseboard;
1306 debug("%s@%d: \n", __func__, __LINE__);
1310 if (tx6ul_temp_check_enabled)
1311 check_cpu_temperature(1);
1313 tx6ul_set_cpu_clock();
1316 setenv_ulong("safeboot", 1);
1317 else if (wrsr & WRSR_TOUT)
1318 setenv_ulong("wdreset", 1);
1320 karo_fdt_move_fdt();
1322 baseboard = getenv("baseboard");
1326 printf("Baseboard: %s\n", baseboard);
1328 if (strncmp(baseboard, "stk5", 4) == 0) {
1329 if ((strlen(baseboard) == 4) ||
1330 strcmp(baseboard, "stk5-v3") == 0) {
1331 stk5v3_board_init();
1332 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1333 const char *otg_mode = getenv("otg_mode");
1335 if (otg_mode && strcmp(otg_mode, "host") == 0) {
1336 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1337 otg_mode, baseboard);
1338 setenv("otg_mode", "none");
1340 stk5v5_board_init();
1342 printf("WARNING: Unsupported STK5 board rev.: %s\n",
1345 } else if (strncmp(baseboard, "ulmb-", 5) == 0) {
1346 const char *otg_mode = getenv("otg_mode");
1348 if (otg_mode && strcmp(otg_mode, "host") == 0) {
1349 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1350 otg_mode, baseboard);
1351 setenv("otg_mode", "none");
1355 printf("WARNING: Unsupported baseboard: '%s'\n",
1362 debug("%s@%d: \n", __func__, __LINE__);
1368 #ifdef CONFIG_FEC_MXC
1374 static void tx6ul_init_mac(void)
1377 const char *baseboard = getenv("baseboard");
1379 imx_get_mac_from_fuse(0, mac);
1380 if (!is_valid_ethaddr(mac)) {
1381 printf("No valid MAC address programmed\n");
1384 printf("MAC addr from fuse: %pM\n", mac);
1385 if (!getenv("ethaddr"))
1386 eth_setenv_enetaddr("ethaddr", mac);
1388 if (!baseboard || strncmp(baseboard, "stk5", 4) == 0) {
1389 setenv("eth1addr", NULL);
1392 if (getenv("eth1addr"))
1394 imx_get_mac_from_fuse(1, mac);
1395 eth_setenv_enetaddr("eth1addr", mac);
1398 int board_eth_init(bd_t *bis)
1404 /* delay at least 21ms for the PHY internal POR signal to deassert */
1407 imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads,
1408 ARRAY_SIZE(tx6ul_enet1_pads));
1410 /* Deassert RESET to the external phys */
1411 gpio_set_value(TX6UL_FEC_RST_GPIO, 1);
1413 if (getenv("ethaddr")) {
1414 ret = fecmxc_initialize_multi(bis, 0, 0, ENET_BASE_ADDR);
1416 printf("failed to initialize FEC0: %d\n", ret);
1420 if (getenv("eth1addr")) {
1421 ret = gpio_request_array(tx6ul_fec2_gpios,
1422 ARRAY_SIZE(tx6ul_fec2_gpios));
1424 printf("Failed to request tx6ul_fec2_gpios: %d\n", ret);
1426 imx_iomux_v3_setup_multiple_pads(tx6ul_enet2_pads,
1427 ARRAY_SIZE(tx6ul_enet2_pads));
1429 writel(0x00100000, 0x020c80e4); /* assert ENET2_125M_EN */
1431 /* Minimum PHY reset duration */
1433 gpio_set_value(TX6UL_FEC2_RST_GPIO, 1);
1434 /* Wait for PHY internal POR to finish */
1437 ret = fecmxc_initialize_multi(bis, 1, 2, ENET2_BASE_ADDR);
1439 printf("failed to initialize FEC1: %d\n", ret);
1445 #endif /* CONFIG_FEC_MXC */
1447 #ifdef CONFIG_SERIAL_TAG
1448 void get_board_serial(struct tag_serialnr *serialnr)
1450 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1451 struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1453 serialnr->low = readl(&fuse->cfg0);
1454 serialnr->high = readl(&fuse->cfg1);
1458 #if defined(CONFIG_OF_BOARD_SETUP)
1459 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1460 #include <jffs2/jffs2.h>
1461 #include <mtd_node.h>
1462 static struct node_info nodes[] = {
1463 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1466 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1469 static const char *tx6ul_touchpanels[] = {
1475 int ft_board_setup(void *blob, bd_t *bd)
1477 const char *baseboard = getenv("baseboard");
1478 int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1479 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1482 ret = fdt_increase_size(blob, 4096);
1484 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1488 karo_fdt_enable_node(blob, "stk5led", 0);
1490 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1492 karo_fdt_fixup_touchpanel(blob, tx6ul_touchpanels,
1493 ARRAY_SIZE(tx6ul_touchpanels));
1494 karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1495 karo_fdt_fixup_flexcan(blob, stk5_v5);
1497 karo_fdt_update_fb_mode(blob, video_mode, "/lcd-panel");
1501 #endif /* CONFIG_OF_BOARD_SETUP */