karo: tx6ul: disable PMIC init
[karo-tx-uboot.git] / board / karo / tx6 / tx6ul.c
1 /*
2  * Copyright (C) 2015 Lothar WaƟmann <LW@KARO-electronics.de>
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  *
6  */
7 #include <common.h>
8 #include <errno.h>
9 #include <libfdt.h>
10 #include <fdt_support.h>
11 #include <lcd.h>
12 #include <netdev.h>
13 #include <mmc.h>
14 #include <fsl_esdhc.h>
15 #include <video_fb.h>
16 #include <ipu.h>
17 #include <mxcfb.h>
18 #include <i2c.h>
19 #include <linux/fb.h>
20 #include <asm/io.h>
21 #include <asm/gpio.h>
22 #include <asm/arch/mx6-pins.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/hab.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/crm_regs.h>
27 #include <asm/arch/sys_proto.h>
28
29 #include "../common/karo.h"
30 #include "pmic.h"
31
32 #define __data __attribute__((section(".data")))
33
34 #define TX6UL_FEC_RST_GPIO              IMX_GPIO_NR(5, 6)
35 #define TX6UL_FEC_PWR_GPIO              IMX_GPIO_NR(5, 7)
36 #define TX6UL_FEC_INT_GPIO              IMX_GPIO_NR(5, 5)
37 #define TX6UL_LED_GPIO                  IMX_GPIO_NR(5, 9)
38
39 #define TX6UL_LCD_PWR_GPIO              IMX_GPIO_NR(5, 4)
40 #define TX6UL_LCD_RST_GPIO              IMX_GPIO_NR(3, 4)
41 #define TX6UL_LCD_BACKLIGHT_GPIO        IMX_GPIO_NR(4, 16)
42
43 #define TX6UL_I2C1_SCL_GPIO             IMX_GPIO_NR(5, 0)
44 #define TX6UL_I2C1_SDA_GPIO             IMX_GPIO_NR(5, 1)
45
46 #define TX6UL_SD1_CD_GPIO               IMX_GPIO_NR(4, 14)
47
48 #ifdef CONFIG_MX6_TEMPERATURE_MIN
49 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
50 #else
51 #define TEMPERATURE_MIN                 (-40)
52 #endif
53 #ifdef CONFIG_MX6_TEMPERATURE_HOT
54 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
55 #else
56 #define TEMPERATURE_HOT                 80
57 #endif
58
59 DECLARE_GLOBAL_DATA_PTR;
60
61 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
62
63 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
64 #ifdef CONFIG_SECURE_BOOT
65 char __csf_data[0] __attribute__((section(".__csf_data")));
66 #endif
67
68 static const iomux_v3_cfg_t const tx6ul_pads[] = {
69         /* UART pads */
70 #if CONFIG_MXC_UART_BASE == UART1_BASE
71         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX,
72         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX,
73         MX6_PAD_UART1_RTS_B__UART1_DCE_RTS,
74         MX6_PAD_UART1_CTS_B__UART1_DCE_CTS,
75 #endif
76 #if CONFIG_MXC_UART_BASE == UART2_BASE
77         MX6_PAD_UART2_TX_DATA__UART2_DCE_TX,
78         MX6_PAD_UART2_RX_DATA__UART2_DCE_RX,
79         MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS,
80         MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS,
81 #endif
82 #if CONFIG_MXC_UART_BASE == UART5_BASE
83         MX6_PAD_GPIO1_IO04__UART5_DCE_TX,
84         MX6_PAD_GPIO1_IO05__UART5_DCE_RX,
85         MX6_PAD_GPIO1_IO08__UART5_DCE_RTS,
86         MX6_PAD_GPIO1_IO09__UART5_DCE_CTS,
87 #endif
88         /* internal I2C */
89         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION, /* I2C SCL */
90         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION, /* I2C SDA */
91
92         /* FEC PHY GPIO functions */
93         MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_CFG_SION, /* PHY POWER */
94         MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | MUX_CFG_SION, /* PHY RESET */
95         MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
96                                                         PAD_CTL_DSE_40ohm), /* PHY INT */
97 };
98
99 #define TX6_ENET_PAD_CTRL       (PAD_CTL_SPEED_HIGH |   \
100                                 PAD_CTL_DSE_48ohm |     \
101                                 PAD_CTL_PUS_100K_UP |   \
102                                 PAD_CTL_SRE_FAST)
103 #define TX6_GPIO_OUT_PAD_CTRL   (PAD_CTL_SPEED_LOW |    \
104                                 PAD_CTL_DSE_60ohm |     \
105                                 PAD_CTL_SRE_SLOW)
106 #define TX6_GPIO_IN_PAD_CTRL    (PAD_CTL_SPEED_LOW |    \
107                                 PAD_CTL_PUS_47K_UP)
108
109 static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = {
110         /* FEC functions */
111         MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_48ohm |
112                                 PAD_CTL_SPEED_MED),
113         MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
114                                 PAD_CTL_DSE_48ohm |
115                                 PAD_CTL_SPEED_MED),
116         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_CFG_SION |
117                                 MUX_PAD_CTRL(PAD_CTL_SPEED_MED |
118                                 PAD_CTL_DSE_40ohm |
119                                 PAD_CTL_SRE_FAST),
120         MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
121         MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
122         MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
123         MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
124         MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
125         MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
126         MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
127
128         MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_CFG_SION |
129                                 MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |
130                                 PAD_CTL_DSE_48ohm |
131                                 PAD_CTL_SRE_FAST),
132         MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
133         MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
134         MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
135         MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
136         MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
137         MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
138         MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
139 };
140
141 #define TX6_I2C_PAD_CTRL        (PAD_CTL_PUS_22K_UP |   \
142                                 PAD_CTL_SPEED_MED |     \
143                                 PAD_CTL_DSE_34ohm |     \
144                                 PAD_CTL_SRE_FAST)
145
146 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
147         /* internal I2C */
148         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
149         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
150 };
151
152 static const struct gpio const tx6ul_gpios[] = {
153         /* These two entries are used to forcefully reinitialize the I2C bus */
154         { TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
155         { TX6UL_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
156
157         { TX6UL_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
158         { TX6UL_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
159         { TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
160 };
161
162 static int pmic_addr __maybe_unused __data = 0x3c;
163
164 #define GPIO_DR 0
165 #define GPIO_DIR 4
166 #define GPIO_PSR 8
167
168 static void tx6_i2c_recover(void)
169 {
170         int i;
171         int bad = 0;
172 #define SCL_BIT         (1 << (TX6UL_I2C1_SCL_GPIO % 32))
173 #define SDA_BIT         (1 << (TX6UL_I2C1_SDA_GPIO % 32))
174 #define I2C_GPIO_BASE   (GPIO1_BASE_ADDR + TX6UL_I2C1_SCL_GPIO / 32 * 0x4000)
175
176         if ((readl(I2C_GPIO_BASE + GPIO_PSR) &
177                         (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
178                 return;
179
180         debug("Clearing I2C bus\n");
181         if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SCL_BIT)) {
182                 printf("I2C SCL stuck LOW\n");
183                 bad++;
184
185                 writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
186                         I2C_GPIO_BASE + GPIO_DR);
187                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
188                         I2C_GPIO_BASE + GPIO_DIR);
189         }
190         if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)) {
191                 printf("I2C SDA stuck LOW\n");
192                 bad++;
193
194                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) & ~SDA_BIT,
195                         I2C_GPIO_BASE + GPIO_DIR);
196                 writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
197                         I2C_GPIO_BASE + GPIO_DR);
198                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
199                         I2C_GPIO_BASE + GPIO_DIR);
200
201                 imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
202                                                 ARRAY_SIZE(tx6_i2c_gpio_pads));
203                 udelay(10);
204
205                 for (i = 0; i < 18; i++) {
206                         u32 reg = readl(I2C_GPIO_BASE + GPIO_DR) ^ SCL_BIT;
207
208                         debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
209                         writel(reg, I2C_GPIO_BASE + GPIO_DR);
210                         udelay(10);
211                         if (reg & SCL_BIT &&
212                                 readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)
213                                 break;
214                 }
215         }
216         if (bad) {
217                 u32 reg = readl(I2C_GPIO_BASE + GPIO_PSR);
218
219                 if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
220                         printf("I2C bus recovery succeeded\n");
221                 } else {
222                         printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
223                                 SCL_BIT | SDA_BIT);
224                 }
225         }
226         debug("Setting up I2C Pads\n");
227 }
228
229 /* placed in section '.data' to prevent overwriting relocation info
230  * overlayed with bss
231  */
232 static u32 wrsr __data;
233
234 #define WRSR_POR                        (1 << 4)
235 #define WRSR_TOUT                       (1 << 1)
236 #define WRSR_SFTW                       (1 << 0)
237
238 static void print_reset_cause(void)
239 {
240         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
241         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
242         u32 srsr;
243         char *dlm = "";
244
245         printf("Reset cause: ");
246
247         srsr = readl(&src_regs->srsr);
248         wrsr = readw(wdt_base + 4);
249
250         if (wrsr & WRSR_POR) {
251                 printf("%sPOR", dlm);
252                 dlm = " | ";
253         }
254         if (srsr & 0x00004) {
255                 printf("%sCSU", dlm);
256                 dlm = " | ";
257         }
258         if (srsr & 0x00008) {
259                 printf("%sIPP USER", dlm);
260                 dlm = " | ";
261         }
262         if (srsr & 0x00010) {
263                 if (wrsr & WRSR_SFTW) {
264                         printf("%sSOFT", dlm);
265                         dlm = " | ";
266                 }
267                 if (wrsr & WRSR_TOUT) {
268                         printf("%sWDOG", dlm);
269                         dlm = " | ";
270                 }
271         }
272         if (srsr & 0x00020) {
273                 printf("%sJTAG HIGH-Z", dlm);
274                 dlm = " | ";
275         }
276         if (srsr & 0x00040) {
277                 printf("%sJTAG SW", dlm);
278                 dlm = " | ";
279         }
280         if (srsr & 0x10000) {
281                 printf("%sWARM BOOT", dlm);
282                 dlm = " | ";
283         }
284         if (dlm[0] == '\0')
285                 printf("unknown");
286
287         printf("\n");
288 }
289
290 #ifdef CONFIG_IMX6_THERMAL
291 #include <thermal.h>
292 #include <imx_thermal.h>
293 #include <fuse.h>
294
295 static void print_temperature(void)
296 {
297         struct udevice *thermal_dev;
298         int cpu_tmp, minc, maxc, ret;
299         char const *grade_str;
300         static u32 __data thermal_calib;
301
302         puts("Temperature: ");
303         switch (get_cpu_temp_grade(&minc, &maxc)) {
304         case TEMP_AUTOMOTIVE:
305                 grade_str = "Automotive";
306                 break;
307         case TEMP_INDUSTRIAL:
308                 grade_str = "Industrial";
309                 break;
310         case TEMP_EXTCOMMERCIAL:
311                 grade_str = "Extended Commercial";
312                 break;
313         default:
314                 grade_str = "Commercial";
315         }
316         printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
317         ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
318         if (ret == 0) {
319                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
320
321                 if (ret == 0)
322                         printf(" at %dC", cpu_tmp);
323                 else
324                         puts(" - failed to read sensor data");
325         } else {
326                 puts(" - no sensor device found");
327         }
328
329         if (fuse_read(1, 6, &thermal_calib) == 0) {
330                 printf(" - calibration data 0x%08x\n", thermal_calib);
331         } else {
332                 puts(" - Failed to read thermal calib fuse\n");
333         }
334 }
335 #else
336 static inline void print_temperature(void)
337 {
338 }
339 #endif
340
341 int checkboard(void)
342 {
343         u32 cpurev = get_cpu_rev();
344         char *cpu_str = "?";
345
346         switch ((cpurev >> 12) & 0xff) {
347         case MXC_CPU_MX6SL:
348                 cpu_str = "SL";
349                 break;
350         case MXC_CPU_MX6DL:
351                 cpu_str = "DL";
352                 break;
353         case MXC_CPU_MX6SOLO:
354                 cpu_str = "SOLO";
355                 break;
356         case MXC_CPU_MX6Q:
357                 cpu_str = "Q";
358                 break;
359         case MXC_CPU_MX6UL:
360                 cpu_str = "UL";
361                 break;
362         }
363
364         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
365                 cpu_str,
366                 (cpurev & 0x000F0) >> 4,
367                 (cpurev & 0x0000F) >> 0,
368                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
369
370         print_temperature();
371         print_reset_cause();
372 #ifdef CONFIG_MX6_TEMPERATURE_HOT
373         check_cpu_temperature(1);
374 #endif
375         tx6_i2c_recover();
376         return 0;
377 }
378
379 /* serial port not initialized at this point */
380 int board_early_init_f(void)
381 {
382         return 0;
383 }
384
385 #ifndef CONFIG_MX6_TEMPERATURE_HOT
386 static bool tx6_temp_check_enabled = true;
387 #else
388 #define tx6_temp_check_enabled  0
389 #endif
390
391 static inline u8 tx6ul_mem_suffix(void)
392 {
393 #ifdef CONFIG_TX6_NAND
394         return '0';
395 #else
396         return '1';
397 #endif
398 }
399
400 int board_init(void)
401 {
402         int ret;
403
404         debug("%s@%d: \n", __func__, __LINE__);
405
406         printf("Board: Ka-Ro TXUL-001%c\n",
407                 tx6ul_mem_suffix());
408
409         get_hab_status();
410
411         ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios));
412         if (ret < 0) {
413                 printf("Failed to request tx6ul_gpios: %d\n", ret);
414         }
415         imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads));
416
417         /* Address of boot parameters */
418         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
419         gd->bd->bi_arch_number = -1;
420
421         if (ctrlc() || (wrsr & WRSR_TOUT)) {
422                 if (wrsr & WRSR_TOUT)
423                         printf("WDOG RESET detected; Skipping PMIC setup\n");
424                 else
425                         printf("<CTRL-C> detected; safeboot enabled\n");
426 #ifndef CONFIG_MX6_TEMPERATURE_HOT
427                 tx6_temp_check_enabled = false;
428 #endif
429                 return 0;
430         }
431 #if 0
432         ret = tx6_pmic_init(pmic_addr);
433         if (ret) {
434                 printf("Failed to setup PMIC voltages: %d\n", ret);
435                 hang();
436         }
437 #endif
438         return 0;
439 }
440
441 int dram_init(void)
442 {
443         debug("%s@%d: \n", __func__, __LINE__);
444
445         /* dram_init must store complete ramsize in gd->ram_size */
446         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
447                                 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
448         return 0;
449 }
450
451 void dram_init_banksize(void)
452 {
453         debug("%s@%d: \n", __func__, __LINE__);
454
455         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
456         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
457                         PHYS_SDRAM_1_SIZE);
458 #if CONFIG_NR_DRAM_BANKS > 1
459         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
460         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
461                         PHYS_SDRAM_2_SIZE);
462 #endif
463 }
464
465 #ifdef  CONFIG_FSL_ESDHC
466 #define TX6_SD_PAD_CTRL         (PAD_CTL_PUS_47K_UP |   \
467                                 PAD_CTL_SPEED_MED |     \
468                                 PAD_CTL_DSE_40ohm |     \
469                                 PAD_CTL_SRE_FAST)
470
471 static const iomux_v3_cfg_t mmc0_pads[] = {
472         MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
473         MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
474         MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
475         MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
476         MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
477         MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
478         /* SD1 CD */
479         MX6_PAD_NAND_CE1_B__GPIO4_IO14 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
480 };
481
482 #ifdef CONFIG_TX6_EMMC
483 static const iomux_v3_cfg_t mmc1_pads[] = {
484         MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
485         MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
486         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
487         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
488         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
489         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
490         /* eMMC RESET */
491         MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
492                                                 PAD_CTL_DSE_40ohm),
493 };
494 #endif
495
496 static struct tx6_esdhc_cfg {
497         const iomux_v3_cfg_t *pads;
498         int num_pads;
499         enum mxc_clock clkid;
500         struct fsl_esdhc_cfg cfg;
501         int cd_gpio;
502 } tx6ul_esdhc_cfg[] = {
503 #ifdef CONFIG_TX6_EMMC
504         {
505                 .pads = mmc1_pads,
506                 .num_pads = ARRAY_SIZE(mmc1_pads),
507                 .clkid = MXC_ESDHC2_CLK,
508                 .cfg = {
509                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
510                         .max_bus_width = 4,
511                 },
512                 .cd_gpio = -EINVAL,
513         },
514 #endif
515         {
516                 .pads = mmc0_pads,
517                 .num_pads = ARRAY_SIZE(mmc0_pads),
518                 .clkid = MXC_ESDHC_CLK,
519                 .cfg = {
520                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
521                         .max_bus_width = 4,
522                 },
523                 .cd_gpio = TX6UL_SD1_CD_GPIO,
524         },
525 };
526
527 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
528 {
529         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
530 }
531
532 int board_mmc_getcd(struct mmc *mmc)
533 {
534         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
535
536         if (cfg->cd_gpio < 0)
537                 return 1;
538
539         debug("SD card %d is %spresent (GPIO %d)\n",
540                 cfg - tx6ul_esdhc_cfg,
541                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
542                 cfg->cd_gpio);
543         return !gpio_get_value(cfg->cd_gpio);
544 }
545
546 int board_mmc_init(bd_t *bis)
547 {
548         int i;
549
550         debug("%s@%d: \n", __func__, __LINE__);
551
552         for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) {
553                 struct mmc *mmc;
554                 struct tx6_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
555                 int ret;
556
557                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
558                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
559
560                 if (cfg->cd_gpio >= 0) {
561                         ret = gpio_request_one(cfg->cd_gpio,
562                                         GPIOFLAG_INPUT, "MMC CD");
563                         if (ret) {
564                                 printf("Error %d requesting GPIO%d_%d\n",
565                                         ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
566                                 continue;
567                         }
568                 }
569
570                 debug("%s: Initializing MMC slot %d\n", __func__, i);
571                 fsl_esdhc_initialize(bis, &cfg->cfg);
572
573                 mmc = find_mmc_device(i);
574                 if (mmc == NULL)
575                         continue;
576                 if (board_mmc_getcd(mmc))
577                         mmc_init(mmc);
578         }
579         return 0;
580 }
581 #endif /* CONFIG_CMD_MMC */
582
583 #ifdef CONFIG_FEC_MXC
584
585 #ifndef ETH_ALEN
586 #define ETH_ALEN 6
587 #endif
588
589 int board_eth_init(bd_t *bis)
590 {
591         int ret;
592
593         debug("%s@%d: \n", __func__, __LINE__);
594
595         /* delay at least 21ms for the PHY internal POR signal to deassert */
596         udelay(22000);
597
598         imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads,
599                                         ARRAY_SIZE(tx6ul_enet1_pads));
600
601         /* Deassert RESET to the external phy */
602         gpio_set_value(TX6UL_FEC_RST_GPIO, 1);
603
604         if (getenv("ethaddr")) {
605                 ret = fecmxc_initialize_multi(bis, 0, -1, ENET_BASE_ADDR);
606                 if (ret) {
607                         printf("failed to initialize FEC0: %d\n", ret);
608                         return ret;
609                 }
610         }
611         if (getenv("eth1addr")) {
612                 ret = fecmxc_initialize_multi(bis, 1, -1, ENET2_BASE_ADDR);
613                 if (ret) {
614                         printf("failed to initialize FEC1: %d\n", ret);
615                         return ret;
616                 }
617         }
618         return 0;
619 }
620
621 static void tx6_init_mac(void)
622 {
623         u8 mac[ETH_ALEN];
624
625         imx_get_mac_from_fuse(0, mac);
626         if (!is_valid_ethaddr(mac)) {
627                 printf("No valid MAC address programmed\n");
628                 return;
629         }
630
631         printf("MAC addr from fuse: %pM\n", mac);
632         eth_setenv_enetaddr("ethaddr", mac);
633
634         imx_get_mac_from_fuse(1, mac);
635         eth_setenv_enetaddr("eth1addr", mac);
636 }
637 #else
638 static inline void tx6_init_mac(void)
639 {
640 }
641 #endif /* CONFIG_FEC_MXC */
642
643 enum {
644         LED_STATE_INIT = -1,
645         LED_STATE_OFF,
646         LED_STATE_ON,
647 };
648
649 static inline int calc_blink_rate(void)
650 {
651         if (!tx6_temp_check_enabled)
652                 return CONFIG_SYS_HZ;
653
654         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
655                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
656                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
657 }
658
659 void show_activity(int arg)
660 {
661         static int led_state = LED_STATE_INIT;
662         static int blink_rate;
663         static ulong last;
664
665         if (led_state == LED_STATE_INIT) {
666                 last = get_timer(0);
667                 gpio_set_value(TX6UL_LED_GPIO, 1);
668                 led_state = LED_STATE_ON;
669                 blink_rate = calc_blink_rate();
670         } else {
671                 if (get_timer(last) > blink_rate) {
672                         blink_rate = calc_blink_rate();
673                         last = get_timer_masked();
674                         if (led_state == LED_STATE_ON) {
675                                 gpio_set_value(TX6UL_LED_GPIO, 0);
676                         } else {
677                                 gpio_set_value(TX6UL_LED_GPIO, 1);
678                         }
679                         led_state = 1 - led_state;
680                 }
681         }
682 }
683
684 static const iomux_v3_cfg_t stk5_pads[] = {
685         /* SW controlled LED on STK5 baseboard */
686         MX6_PAD_SNVS_TAMPER9__GPIO5_IO09,
687
688         /* I2C bus on DIMM pins 40/41 */
689         MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
690         MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
691
692         /* TSC200x PEN IRQ */
693         MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL),
694 #if 0
695         /* EDT-FT5x06 Polytouch panel */
696         MX6_PAD_NAND_CS2__GPIO6_IO15 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* IRQ */
697         MX6_PAD_EIM_A16__GPIO2_IO22 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* RESET */
698         MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* WAKE */
699
700         /* USBH1 */
701         MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
702         MX6_PAD_EIM_D30__GPIO3_IO30 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
703         /* USBOTG */
704         MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* USBOTG ID */
705         MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
706         MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
707 #endif
708 };
709
710 static const struct gpio stk5_gpios[] = {
711         { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
712
713         { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
714         { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
715         { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
716         { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
717         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
718 };
719
720 #ifdef CONFIG_LCD
721 static u16 tx6_cmap[256];
722 vidinfo_t panel_info = {
723         /* set to max. size supported by SoC */
724         .vl_col = 1920,
725         .vl_row = 1080,
726
727         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
728         .cmap = tx6_cmap,
729 };
730
731 static struct fb_videomode tx6_fb_modes[] = {
732 #ifndef CONFIG_SYS_LVDS_IF
733         {
734                 /* Standard VGA timing */
735                 .name           = "VGA",
736                 .refresh        = 60,
737                 .xres           = 640,
738                 .yres           = 480,
739                 .pixclock       = KHZ2PICOS(25175),
740                 .left_margin    = 48,
741                 .hsync_len      = 96,
742                 .right_margin   = 16,
743                 .upper_margin   = 31,
744                 .vsync_len      = 2,
745                 .lower_margin   = 12,
746                 .sync           = FB_SYNC_CLK_LAT_FALL,
747         },
748         {
749                 /* Emerging ETV570 640 x 480 display. Syncs low active,
750                  * DE high active, 115.2 mm x 86.4 mm display area
751                  * VGA compatible timing
752                  */
753                 .name           = "ETV570",
754                 .refresh        = 60,
755                 .xres           = 640,
756                 .yres           = 480,
757                 .pixclock       = KHZ2PICOS(25175),
758                 .left_margin    = 114,
759                 .hsync_len      = 30,
760                 .right_margin   = 16,
761                 .upper_margin   = 32,
762                 .vsync_len      = 3,
763                 .lower_margin   = 10,
764                 .sync           = FB_SYNC_CLK_LAT_FALL,
765         },
766         {
767                 /* Emerging ET0350G0DH6 320 x 240 display.
768                  * 70.08 mm x 52.56 mm display area.
769                  */
770                 .name           = "ET0350",
771                 .refresh        = 60,
772                 .xres           = 320,
773                 .yres           = 240,
774                 .pixclock       = KHZ2PICOS(6500),
775                 .left_margin    = 68 - 34,
776                 .hsync_len      = 34,
777                 .right_margin   = 20,
778                 .upper_margin   = 18 - 3,
779                 .vsync_len      = 3,
780                 .lower_margin   = 4,
781                 .sync           = FB_SYNC_CLK_LAT_FALL,
782         },
783         {
784                 /* Emerging ET0430G0DH6 480 x 272 display.
785                  * 95.04 mm x 53.856 mm display area.
786                  */
787                 .name           = "ET0430",
788                 .refresh        = 60,
789                 .xres           = 480,
790                 .yres           = 272,
791                 .pixclock       = KHZ2PICOS(9000),
792                 .left_margin    = 2,
793                 .hsync_len      = 41,
794                 .right_margin   = 2,
795                 .upper_margin   = 2,
796                 .vsync_len      = 10,
797                 .lower_margin   = 2,
798         },
799         {
800                 /* Emerging ET0500G0DH6 800 x 480 display.
801                  * 109.6 mm x 66.4 mm display area.
802                  */
803                 .name           = "ET0500",
804                 .refresh        = 60,
805                 .xres           = 800,
806                 .yres           = 480,
807                 .pixclock       = KHZ2PICOS(33260),
808                 .left_margin    = 216 - 128,
809                 .hsync_len      = 128,
810                 .right_margin   = 1056 - 800 - 216,
811                 .upper_margin   = 35 - 2,
812                 .vsync_len      = 2,
813                 .lower_margin   = 525 - 480 - 35,
814                 .sync           = FB_SYNC_CLK_LAT_FALL,
815         },
816         {
817                 /* Emerging ETQ570G0DH6 320 x 240 display.
818                  * 115.2 mm x 86.4 mm display area.
819                  */
820                 .name           = "ETQ570",
821                 .refresh        = 60,
822                 .xres           = 320,
823                 .yres           = 240,
824                 .pixclock       = KHZ2PICOS(6400),
825                 .left_margin    = 38,
826                 .hsync_len      = 30,
827                 .right_margin   = 30,
828                 .upper_margin   = 16, /* 15 according to datasheet */
829                 .vsync_len      = 3, /* TVP -> 1>x>5 */
830                 .lower_margin   = 4, /* 4.5 according to datasheet */
831                 .sync           = FB_SYNC_CLK_LAT_FALL,
832         },
833         {
834                 /* Emerging ET0700G0DH6 800 x 480 display.
835                  * 152.4 mm x 91.44 mm display area.
836                  */
837                 .name           = "ET0700",
838                 .refresh        = 60,
839                 .xres           = 800,
840                 .yres           = 480,
841                 .pixclock       = KHZ2PICOS(33260),
842                 .left_margin    = 216 - 128,
843                 .hsync_len      = 128,
844                 .right_margin   = 1056 - 800 - 216,
845                 .upper_margin   = 35 - 2,
846                 .vsync_len      = 2,
847                 .lower_margin   = 525 - 480 - 35,
848                 .sync           = FB_SYNC_CLK_LAT_FALL,
849         },
850         {
851                 /* Emerging ET070001DM6 800 x 480 display.
852                  * 152.4 mm x 91.44 mm display area.
853                  */
854                 .name           = "ET070001DM6",
855                 .refresh        = 60,
856                 .xres           = 800,
857                 .yres           = 480,
858                 .pixclock       = KHZ2PICOS(33260),
859                 .left_margin    = 216 - 128,
860                 .hsync_len      = 128,
861                 .right_margin   = 1056 - 800 - 216,
862                 .upper_margin   = 35 - 2,
863                 .vsync_len      = 2,
864                 .lower_margin   = 525 - 480 - 35,
865                 .sync           = 0,
866         },
867 #else
868         {
869                 /* HannStar HSD100PXN1
870                  * 202.7m mm x 152.06 mm display area.
871                  */
872                 .name           = "HSD100PXN1",
873                 .refresh        = 60,
874                 .xres           = 1024,
875                 .yres           = 768,
876                 .pixclock       = KHZ2PICOS(65000),
877                 .left_margin    = 0,
878                 .hsync_len      = 0,
879                 .right_margin   = 320,
880                 .upper_margin   = 0,
881                 .vsync_len      = 0,
882                 .lower_margin   = 38,
883                 .sync           = FB_SYNC_CLK_LAT_FALL,
884         },
885 #endif
886         {
887                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
888                 .refresh        = 60,
889                 .left_margin    = 48,
890                 .hsync_len      = 96,
891                 .right_margin   = 16,
892                 .upper_margin   = 31,
893                 .vsync_len      = 2,
894                 .lower_margin   = 12,
895                 .sync           = FB_SYNC_CLK_LAT_FALL,
896         },
897 };
898
899 static int lcd_enabled = 1;
900 static int lcd_bl_polarity;
901
902 static int lcd_backlight_polarity(void)
903 {
904         return lcd_bl_polarity;
905 }
906
907 void lcd_enable(void)
908 {
909         /* HACK ALERT:
910          * global variable from common/lcd.c
911          * Set to 0 here to prevent messages from going to LCD
912          * rather than serial console
913          */
914         lcd_is_enabled = 0;
915
916         if (lcd_enabled) {
917                 karo_load_splashimage(1);
918
919                 debug("Switching LCD on\n");
920                 gpio_set_value(TX6UL_LCD_PWR_GPIO, 1);
921                 udelay(100);
922                 gpio_set_value(TX6UL_LCD_RST_GPIO, 1);
923                 udelay(300000);
924                 gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
925                         lcd_backlight_polarity());
926         }
927 }
928
929 void lcd_disable(void)
930 {
931         if (lcd_enabled) {
932                 printf("Disabling LCD\n");
933 //              ipuv3_fb_shutdown();
934         }
935 }
936
937 void lcd_panel_disable(void)
938 {
939         if (lcd_enabled) {
940                 debug("Switching LCD off\n");
941                 gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
942                         !lcd_backlight_polarity());
943                 gpio_set_value(TX6UL_LCD_RST_GPIO, 0);
944                 gpio_set_value(TX6UL_LCD_PWR_GPIO, 0);
945         }
946 }
947
948 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
949 #if 1
950         /* LCD RESET */
951         MX6_PAD_LCD_RESET__LCDIF_RESET,
952         /* LCD POWER_ENABLE */
953         MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
954         /* LCD Backlight (PWM) */
955         MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
956 #endif
957 #ifdef CONFIG_LCD
958         /* Display */
959         MX6_PAD_LCD_DATA00__LCDIF_DATA00,
960         MX6_PAD_LCD_DATA01__LCDIF_DATA01,
961         MX6_PAD_LCD_DATA02__LCDIF_DATA02,
962         MX6_PAD_LCD_DATA03__LCDIF_DATA03,
963         MX6_PAD_LCD_DATA04__LCDIF_DATA04,
964         MX6_PAD_LCD_DATA05__LCDIF_DATA05,
965         MX6_PAD_LCD_DATA06__LCDIF_DATA06,
966         MX6_PAD_LCD_DATA07__LCDIF_DATA07,
967         MX6_PAD_LCD_DATA08__LCDIF_DATA08,
968         MX6_PAD_LCD_DATA09__LCDIF_DATA09,
969         MX6_PAD_LCD_DATA10__LCDIF_DATA10,
970         MX6_PAD_LCD_DATA11__LCDIF_DATA11,
971         MX6_PAD_LCD_DATA12__LCDIF_DATA12,
972         MX6_PAD_LCD_DATA13__LCDIF_DATA13,
973         MX6_PAD_LCD_DATA14__LCDIF_DATA14,
974         MX6_PAD_LCD_DATA15__LCDIF_DATA15,
975         MX6_PAD_LCD_DATA16__LCDIF_DATA16,
976         MX6_PAD_LCD_DATA17__LCDIF_DATA17,
977         MX6_PAD_LCD_DATA18__LCDIF_DATA18,
978         MX6_PAD_LCD_DATA19__LCDIF_DATA19,
979         MX6_PAD_LCD_DATA20__LCDIF_DATA20,
980         MX6_PAD_LCD_DATA21__LCDIF_DATA21,
981         MX6_PAD_LCD_DATA22__LCDIF_DATA22,
982         MX6_PAD_LCD_DATA23__LCDIF_DATA23,
983         MX6_PAD_LCD_HSYNC__LCDIF_HSYNC, /* HSYNC */
984         MX6_PAD_LCD_VSYNC__LCDIF_VSYNC, /* VSYNC */
985         MX6_PAD_LCD_ENABLE__LCDIF_ENABLE, /* OE_ACD */
986         MX6_PAD_LCD_CLK__LCDIF_CLK, /* LSCLK */
987 #endif
988 };
989
990 static const struct gpio stk5_lcd_gpios[] = {
991 //      { TX6UL_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
992         { TX6UL_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
993         { TX6UL_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
994 };
995
996 void lcd_ctrl_init(void *lcdbase)
997 {
998         int color_depth = 24;
999         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1000         const char *vm;
1001         unsigned long val;
1002         int refresh = 60;
1003         struct fb_videomode *p = &tx6_fb_modes[0];
1004         struct fb_videomode fb_mode;
1005         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1006         int pix_fmt;
1007         int lcd_bus_width;
1008
1009         if (!lcd_enabled) {
1010                 debug("LCD disabled\n");
1011                 return;
1012         }
1013
1014         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1015                 debug("Disabling LCD\n");
1016                 lcd_enabled = 0;
1017                 setenv("splashimage", NULL);
1018                 return;
1019         }
1020
1021         karo_fdt_move_fdt();
1022         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1023
1024         if (video_mode == NULL) {
1025                 debug("Disabling LCD\n");
1026                 lcd_enabled = 0;
1027                 return;
1028         }
1029         vm = video_mode;
1030         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1031                 p = &fb_mode;
1032                 debug("Using video mode from FDT\n");
1033                 vm += strlen(vm);
1034                 if (fb_mode.xres > panel_info.vl_col ||
1035                         fb_mode.yres > panel_info.vl_row) {
1036                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1037                                 fb_mode.xres, fb_mode.yres,
1038                                 panel_info.vl_col, panel_info.vl_row);
1039                         lcd_enabled = 0;
1040                         return;
1041                 }
1042         }
1043         if (p->name != NULL)
1044                 debug("Trying compiled-in video modes\n");
1045         while (p->name != NULL) {
1046                 if (strcmp(p->name, vm) == 0) {
1047                         debug("Using video mode: '%s'\n", p->name);
1048                         vm += strlen(vm);
1049                         break;
1050                 }
1051                 p++;
1052         }
1053         if (*vm != '\0')
1054                 debug("Trying to decode video_mode: '%s'\n", vm);
1055         while (*vm != '\0') {
1056                 if (*vm >= '0' && *vm <= '9') {
1057                         char *end;
1058
1059                         val = simple_strtoul(vm, &end, 0);
1060                         if (end > vm) {
1061                                 if (!xres_set) {
1062                                         if (val > panel_info.vl_col)
1063                                                 val = panel_info.vl_col;
1064                                         p->xres = val;
1065                                         panel_info.vl_col = val;
1066                                         xres_set = 1;
1067                                 } else if (!yres_set) {
1068                                         if (val > panel_info.vl_row)
1069                                                 val = panel_info.vl_row;
1070                                         p->yres = val;
1071                                         panel_info.vl_row = val;
1072                                         yres_set = 1;
1073                                 } else if (!bpp_set) {
1074                                         switch (val) {
1075                                         case 32:
1076                                         case 24:
1077                                                 if (is_lvds())
1078                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
1079                                                 /* fallthru */
1080                                         case 16:
1081                                         case 8:
1082                                                 color_depth = val;
1083                                                 break;
1084
1085                                         case 18:
1086                                                 if (is_lvds()) {
1087                                                         color_depth = val;
1088                                                         break;
1089                                                 }
1090                                                 /* fallthru */
1091                                         default:
1092                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1093                                                         end - vm, vm, color_depth);
1094                                         }
1095                                         bpp_set = 1;
1096                                 } else if (!refresh_set) {
1097                                         refresh = val;
1098                                         refresh_set = 1;
1099                                 }
1100                         }
1101                         vm = end;
1102                 }
1103                 switch (*vm) {
1104                 case '@':
1105                         bpp_set = 1;
1106                         /* fallthru */
1107                 case '-':
1108                         yres_set = 1;
1109                         /* fallthru */
1110                 case 'x':
1111                         xres_set = 1;
1112                         /* fallthru */
1113                 case 'M':
1114                 case 'R':
1115                         vm++;
1116                         break;
1117
1118                 default:
1119                         if (*vm != '\0')
1120                                 vm++;
1121                 }
1122         }
1123         if (p->xres == 0 || p->yres == 0) {
1124                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1125                 lcd_enabled = 0;
1126                 printf("Supported video modes are:");
1127                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1128                         printf(" %s", p->name);
1129                 }
1130                 printf("\n");
1131                 return;
1132         }
1133         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1134                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1135                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1136                 lcd_enabled = 0;
1137                 return;
1138         }
1139         panel_info.vl_col = p->xres;
1140         panel_info.vl_row = p->yres;
1141
1142         switch (color_depth) {
1143         case 8:
1144                 panel_info.vl_bpix = LCD_COLOR8;
1145                 break;
1146         case 16:
1147                 panel_info.vl_bpix = LCD_COLOR16;
1148                 break;
1149         default:
1150                 panel_info.vl_bpix = LCD_COLOR32;
1151         }
1152
1153         p->pixclock = KHZ2PICOS(refresh *
1154                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1155                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1156                                 1000);
1157         debug("Pixel clock set to %lu.%03lu MHz\n",
1158                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1159
1160         if (p != &fb_mode) {
1161                 int ret;
1162
1163                 debug("Creating new display-timing node from '%s'\n",
1164                         video_mode);
1165                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1166                 if (ret)
1167                         printf("Failed to create new display-timing node from '%s': %d\n",
1168                                 video_mode, ret);
1169         }
1170
1171         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1172         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1173                                         ARRAY_SIZE(stk5_lcd_pads));
1174
1175         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1176         switch (lcd_bus_width) {
1177         case 24:
1178                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1179                 break;
1180
1181         case 18:
1182                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1183                 break;
1184
1185         case 16:
1186                 if (!is_lvds()) {
1187                         pix_fmt = IPU_PIX_FMT_RGB565;
1188                         break;
1189                 }
1190                 /* fallthru */
1191         default:
1192                 lcd_enabled = 0;
1193                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1194                         lcd_bus_width);
1195                 return;
1196         }
1197         if (is_lvds()) {
1198                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1199                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1200                 uint32_t gpr2;
1201                 uint32_t gpr3;
1202
1203                 if (lvds_chan_mask == 0) {
1204                         printf("No LVDS channel active\n");
1205                         lcd_enabled = 0;
1206                         return;
1207                 }
1208
1209                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1210                 if (lcd_bus_width == 24)
1211                         gpr2 |= (1 << 5) | (1 << 7);
1212                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1213                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1214                 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1215                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1216
1217                 gpr3 = readl(IOMUXC_BASE_ADDR + 0xc);
1218                 gpr3 &= ~((3 << 8) | (3 << 6));
1219                 writel(gpr3, IOMUXC_BASE_ADDR + 0xc);
1220         }
1221         if (karo_load_splashimage(0) == 0) {
1222 #if 0
1223                 int ret;
1224
1225                 debug("Initializing LCD controller\n");
1226                 ret = ipuv3_fb_init(p, 0, pix_fmt,
1227                                 is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
1228                                 di_clk_rate, -1);
1229                 if (ret) {
1230                         printf("Failed to initialize FB driver: %d\n", ret);
1231                         lcd_enabled = 0;
1232                 }
1233 #else
1234                 lcd_enabled = pix_fmt * 0;
1235 #endif
1236         } else {
1237                 debug("Skipping initialization of LCD controller\n");
1238         }
1239 }
1240 #else
1241 #define lcd_enabled 0
1242 #endif /* CONFIG_LCD */
1243
1244 static void stk5_board_init(void)
1245 {
1246         int ret;
1247
1248         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1249         if (ret < 0) {
1250                 printf("Failed to request stk5_gpios: %d\n", ret);
1251                 return;
1252         }
1253         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1254 debug("%s@%d: \n", __func__, __LINE__);
1255 }
1256
1257 static void stk5v3_board_init(void)
1258 {
1259 debug("%s@%d: \n", __func__, __LINE__);
1260         stk5_board_init();
1261 debug("%s@%d: \n", __func__, __LINE__);
1262 }
1263
1264 static void stk5v5_board_init(void)
1265 {
1266         int ret;
1267
1268         stk5_board_init();
1269
1270         ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
1271                         "Flexcan Transceiver");
1272         if (ret) {
1273                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1274                 return;
1275         }
1276
1277         imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 |
1278                         MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL));
1279 }
1280
1281 static void tx6ul_set_cpu_clock(void)
1282 {
1283         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1284
1285         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1286                 return;
1287
1288         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1289                 printf("%s detected; skipping cpu clock change\n",
1290                         (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1291                 return;
1292         }
1293         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1294                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1295                 printf("CPU clock set to %lu.%03lu MHz\n",
1296                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1297         } else {
1298                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1299         }
1300 }
1301
1302 int board_late_init(void)
1303 {
1304         int ret = 0;
1305         const char *baseboard;
1306
1307         debug("%s@%d: \n", __func__, __LINE__);
1308
1309         env_cleanup();
1310
1311         if (tx6_temp_check_enabled)
1312                 check_cpu_temperature(1);
1313
1314         tx6ul_set_cpu_clock();
1315
1316         if (had_ctrlc())
1317                 setenv_ulong("safeboot", 1);
1318         else if (wrsr & WRSR_TOUT)
1319                 setenv_ulong("wdreset", 1);
1320         else
1321                 karo_fdt_move_fdt();
1322
1323         baseboard = getenv("baseboard");
1324         if (!baseboard)
1325                 goto exit;
1326
1327         printf("Baseboard: %s\n", baseboard);
1328
1329         if (strncmp(baseboard, "stk5", 4) == 0) {
1330                 if ((strlen(baseboard) == 4) ||
1331                         strcmp(baseboard, "stk5-v3") == 0) {
1332                         stk5v3_board_init();
1333                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1334                         const char *otg_mode = getenv("otg_mode");
1335
1336                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1337                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1338                                         otg_mode, baseboard);
1339                                 setenv("otg_mode", "none");
1340                         }
1341                         stk5v5_board_init();
1342                 } else {
1343                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1344                                 baseboard + 4);
1345                 }
1346         } else {
1347                 printf("WARNING: Unsupported baseboard: '%s'\n",
1348                         baseboard);
1349                 ret = -EINVAL;
1350         }
1351
1352 exit:
1353 debug("%s@%d: \n", __func__, __LINE__);
1354         tx6_init_mac();
1355 debug("%s@%d: \n", __func__, __LINE__);
1356
1357         clear_ctrlc();
1358         return ret;
1359 }
1360
1361 #ifdef CONFIG_SERIAL_TAG
1362 void get_board_serial(struct tag_serialnr *serialnr)
1363 {
1364         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1365         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1366
1367         serialnr->low = readl(&fuse->cfg0);
1368         serialnr->high = readl(&fuse->cfg1);
1369 }
1370 #endif
1371
1372 #if defined(CONFIG_OF_BOARD_SETUP)
1373 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1374 #include <jffs2/jffs2.h>
1375 #include <mtd_node.h>
1376 static struct node_info nodes[] = {
1377         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1378 };
1379 #else
1380 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1381 #endif
1382
1383 static const char *tx6_touchpanels[] = {
1384         "ti,tsc2007",
1385         "edt,edt-ft5x06",
1386         "eeti,egalax_ts",
1387 };
1388
1389 int ft_board_setup(void *blob, bd_t *bd)
1390 {
1391         const char *baseboard = getenv("baseboard");
1392         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1393         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1394         int ret;
1395
1396         ret = fdt_increase_size(blob, 4096);
1397         if (ret) {
1398                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1399                 return ret;
1400         }
1401         if (stk5_v5)
1402                 karo_fdt_enable_node(blob, "stk5led", 0);
1403
1404         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1405         fdt_fixup_ethernet(blob);
1406
1407         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1408                                 ARRAY_SIZE(tx6_touchpanels));
1409         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1410         karo_fdt_fixup_flexcan(blob, stk5_v5);
1411
1412         karo_fdt_update_fb_mode(blob, video_mode);
1413
1414         return 0;
1415 }
1416 #endif /* CONFIG_OF_BOARD_SETUP */