2 #include <configs/tx6dl.h>
3 #include <asm/arch/imx-regs.h>
5 #define DEBUG_LED_BIT 20
6 #define LED_GPIO_BASE GPIO2_BASE_ADDR
7 #define LED_MUX_OFFSET 0x0ec
8 #define LED_MUX_MODE 0x15
10 #define SDRAM_CLK CONFIG_SYS_SDRAM_CLK
12 #ifdef PHYS_SDRAM_2_SIZE
13 #define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
15 #define SDRAM_SIZE PHYS_SDRAM_1_SIZE
18 #define CPU_2_BE_32(l) \
19 ((((l) << 24) & 0xFF000000) | \
20 (((l) << 8) & 0x00FF0000) | \
21 (((l) >> 8) & 0x0000FF00) | \
22 (((l) >> 24) & 0x000000FF))
24 #define CHECK_DCD_ADDR(a) ( \
25 ((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ || \
26 ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ || \
27 ((a) >= 0x020C8000 && (a) <= 0x020C8FFF) /* ANALOG */ || \
28 ((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ || \
29 ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ || \
30 ((a) >= 0x08000000 && (a) <= 0x0FFEFFFF) /* EIM (CS0) */ || \
31 ((a) >= 0x10000000 && (a) <= 0xFFFFFFFF) /* SDRAM */)
33 .macro mxc_dcd_item addr, val
34 .ifne CHECK_DCD_ADDR(\addr)
35 .word CPU_2_BE_32(\addr), CPU_2_BE_32(\val)
37 .error "Address \addr not accessible from DCD"
41 #define MXC_DCD_ITEM(addr, val) mxc_dcd_item addr, val
43 #define MXC_DCD_CMD_SZ_BYTE 1
44 #define MXC_DCD_CMD_SZ_SHORT 2
45 #define MXC_DCD_CMD_SZ_WORD 4
46 #define MXC_DCD_CMD_FLAG_WRITE 0x0
47 #define MXC_DCD_CMD_FLAG_CLR 0x1
48 #define MXC_DCD_CMD_FLAG_SET 0x3
49 #define MXC_DCD_CMD_FLAG_CHK_ANY (1 << 0)
50 #define MXC_DCD_CMD_FLAG_CHK_SET (1 << 1)
51 #define MXC_DCD_CMD_FLAG_CHK_CLR (0 << 1)
53 #define MXC_DCD_CMD_WRT(type, flags, next) \
54 .word CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type))
56 #define MXC_DCD_CMD_CHK(type, flags, addr, mask) \
57 .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)),\
58 CPU_2_BE_32(addr), CPU_2_BE_32(mask)
60 #define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \
61 .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\
62 CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
64 #define MXC_DCD_CMD_NOP \
65 .word CPU_2_BE_32((0xc0 << 24) | (4 << 8))
67 #define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
68 #define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
70 .macro CK_VAL, name, clks, offs, max
74 .ifle \clks - \offs - \max
75 .set \name, \clks - \offs
77 .error "Value \clks out of range for parameter \name"
82 .macro NS_VAL, name, ns, offs, max
86 CK_VAL \name, NS_TO_CK(\ns), \offs, \max
90 .macro CK_MAX, name, ck1, ck2, offs, max
92 CK_VAL \name, \ck1, \offs, \max
94 CK_VAL \name, \ck2, \offs, \max
98 #define MDMISC_DDR_TYPE_DDR3 0
99 #define MDMISC_DDR_TYPE_LPDDR2 1
100 #define MDMISC_DDR_TYPE_DDR2 2
102 #define DIV_ROUND_UP(m,d) (((m) + (d) - 1) / (d))
104 #define MDOR_CLK_PERIOD_ns 15258 /* base clock for MDOR values */
107 #if SDRAM_SIZE > PHYS_SDRAM_1_SIZE
108 #define BANK_ADDR_BITS 2
110 #define BANK_ADDR_BITS 1
112 #define SDRAM_BURST_LENGTH 8
116 #define ADDR_MIRROR 1
117 #define DDR_TYPE MDMISC_DDR_TYPE_DDR3
119 /* 512/1024MiB SDRAM: NT5CB128M16P-CG */
121 NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */
122 CK_MAX tXS, tRFC + 1 + NS_TO_CK(10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
123 CK_MAX tXP, 3, NS_TO_CK(6), 1, 7 /* clks - 1 (0..7) */ /* max(6ns, 3*CK) */
124 CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */
125 NS_VAL tFAW, 45, 1, 31 /* clks - 1 (0..31) */
126 CK_VAL tCL, 8, 3, 8 /* clks - 3 (0..8) CAS Latency */
129 NS_VAL tRCD, 14, 1, 7 /* clks - 1 (0..7) */
130 NS_VAL tRP, 14, 1, 7 /* clks - 1 (0..7) */
131 NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) */
132 NS_VAL tRAS, 36, 1, 31 /* clks - 1 (0..31) */
133 CK_VAL tRPA, 0, 0, 1 /* clks (0..1) */
134 NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */
135 CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */
136 CK_VAL tCWL, 6, 2, 6 /* clks - 2 (0..6) */
139 CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */
140 CK_MAX tRTP, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
141 CK_MAX tWTR, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
142 CK_MAX tRRD, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
145 CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
146 #define tSDE_RST (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2)
147 #define tRST_CKE (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2)
150 NS_VAL tAOFPD, 9, 1, 7 /* clks - 1 (0..7) */
151 NS_VAL tAONPD, 9, 1, 7 /* clks - 1 (0..7) */
152 CK_VAL tANPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
153 CK_VAL tAXPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
154 CK_VAL tODTLon tCWL, 1, 7 /* clks - 1 (0..7) */
155 CK_VAL tODTLoff tCWL, 1, 31 /* clks - 1 (0..31) */
158 CK_MAX tCKE, NS_TO_CK(6), 3, 1, 7
159 CK_MAX tCKSRX, NS_TO_CK(10), 5, 0, 7
160 CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7
167 #define MDPDC_VAL_0 ( \
172 (BOTH_CS_PD << 6) | \
177 #define MDPDC_VAL_1 (MDPDC_VAL_0 | \
182 #define ROW_ADDR_BITS 14
183 #define COL_ADDR_BITS 10
186 .set mr0_val, ((1 << 8) /* DLL Reset */ | \
187 ((tWR + 1 - 4) << 9) | \
188 (((tCL + 3) - 4) << 4))
190 .set mr0_val, ((1 << 8) /* DLL Reset */ | \
191 (((tWR + 1) / 2) << 9) | \
192 (((tCL + 3) - 4) << 4))
195 #define MDSCR_MRS_VAL(cs, mr, val) (((val) << 16) | \
196 (1 << 15) /* CON REQ */ | \
197 (3 << 4) /* MRS command */ | \
201 #define mr1_val 0x0040
202 #define mr2_val 0x0408
204 #define MDCFG0_VAL ( \
212 #define MDCFG1_VAL ( \
222 #define MDCFG2_VAL ( \
228 #define BURST_LEN (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
230 #if PHYS_SDRAM_1_WIDTH == 64
231 #define MDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \
232 ((COL_ADDR_BITS - 9) << 20) | \
233 (BURST_LEN << 19) | \
234 (2 << 16) | /* SDRAM bus width */ \
235 ((-1) << (32 - BANK_ADDR_BITS)))
237 #define MDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \
238 ((COL_ADDR_BITS - 9) << 20) | \
239 (BURST_LEN << 19) | \
240 (1 << 16) | /* SDRAM bus width */ \
241 ((-1) << (32 - BANK_ADDR_BITS)))
244 #define MDMISC_VAL ((ADDR_MIRROR << 19) | \
251 #define MDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
253 #define MDOTC_VAL ((tAOFPD << 27) | \
264 .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
280 .long CONFIG_U_BOOT_IMG_SIZE
284 #define DCD_VERSION 0x40
286 #define CLKCTL_CCGR0 0x68
287 #define CLKCTL_CCGR1 0x6c
288 #define CLKCTL_CCGR2 0x70
289 #define CLKCTL_CCGR3 0x74
290 #define CLKCTL_CCGR4 0x78
291 #define CLKCTL_CCGR5 0x7c
292 #define CLKCTL_CCGR6 0x80
293 #define CLKCTL_CCGR7 0x84
294 #define CLKCTL_CMEOR 0x88
296 #define DDR_SEL_VAL 3
300 #define DDR_SEL_SHIFT 18
301 #define DDR_MODE_SHIFT 17
309 #define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT)
310 #define DDR_MODE_MASK (1 << DDR_MODE_SHIFT)
311 #define DSE_MASK (DSE_VAL << DSE_SHIFT)
312 #define ODT_MASK (ODT_VAL << ODT_SHIFT)
314 #define DQM_MASK (DDR_MODE_MASK | DSE_MASK)
315 #define SDQS_MASK DSE_MASK
316 #define SDODT_MASK (DSE_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
317 #define SDCLK_MASK (DDR_MODE_MASK | DSE_MASK)
318 #define SDCKE_MASK ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
319 #define DDR_ADDR_MASK 0
320 #define DDR_CTRL_MASK (DDR_MODE_MASK | DSE_MASK)
322 #define CCM_CCR 0x020c4000
323 #define CCM_CS2CDR 0x020c402c
324 #define CCM_CCGR0 0x020c4068
325 #define CCM_CCGR1 0x020c406c
326 #define CCM_CCGR2 0x020c4070
327 #define CCM_CCGR3 0x020c4074
328 #define CCM_CCGR4 0x020c4078
329 #define CCM_CCGR5 0x020c407c
330 #define CCM_CCGR6 0x020c4080
331 #define CCM_ANALOG_PLL_ENET 0x020c80e0
332 #define MMDC1_MDCTL 0x021b0000
333 #define MMDC1_MDPDC 0x021b0004
334 #define MMDC1_MDOTC 0x021b0008
335 #define MMDC1_MDCFG0 0x021b000c
336 #define MMDC1_MDCFG1 0x021b0010
337 #define MMDC1_MDCFG2 0x021b0014
338 #define MMDC1_MDMISC 0x021b0018
339 #define MMDC1_MDSCR 0x021b001c
340 #define MMDC1_MDREF 0x021b0020
341 #define MMDC1_MDRWD 0x021b002c
342 #define MMDC1_MDOR 0x021b0030
343 #define MMDC1_MDASP 0x021b0040
344 #define MMDC1_MAPSR 0x021b0404
345 #define MMDC1_MPZQHWCTRL 0x021b0800
346 #define MMDC1_MPWLGCR 0x021b0808
347 #define MMDC1_MPODTCTRL 0x021b0818
348 #define MMDC1_MPRDDQBY0DL 0x021b081c
349 #define MMDC1_MPRDDQBY1DL 0x021b0820
350 #define MMDC1_MPRDDQBY2DL 0x021b0824
351 #define MMDC1_MPRDDQBY3DL 0x021b0828
352 #define MMDC1_MPDGCTRL0 0x021b083c
353 #define MMDC1_MPRDDLCTL 0x021b0848
354 #define MMDC1_MPWRDLCTL 0x021b0850
355 #define MMDC1_MPRDDLHWCTL 0x021b0860
356 #define MMDC1_MPWRDLHWCTL 0x021b0864
357 #define MMDC1_MPPDCMPR2 0x021b0890
358 #define MMDC1_MPMUR0 0x021b08b8
359 #define MMDC2_MPZQHWCTRL 0x021b4800
360 #define MMDC2_MPWLGCR 0x021b4808
361 #define MMDC2_MPODTCTRL 0x021b4818
362 #define MMDC2_MPRDDQBY0DL 0x021b481c
363 #define MMDC2_MPRDDQBY1DL 0x021b4820
364 #define MMDC2_MPRDDQBY2DL 0x021b4824
365 #define MMDC2_MPRDDQBY3DL 0x021b4828
366 #define MMDC2_MPDGCTRL0 0x021b483c
367 #define MMDC2_MPRDDLCTL 0x021b4848
368 #define MMDC2_MPWRDLCTL 0x021b4850
369 #define MMDC2_MPRDDLHWCTL 0x021b4860
370 #define MMDC2_MPWRDLHWCTL 0x021b4864
371 #define MMDC2_MPMUR0 0x021b48b8
374 #define IOMUXC_GPR1 0x020e0004
375 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17 0x020e024c
376 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 0x020e02a8
377 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6 0x020e02ac
378 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 0x020e02c0
379 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 0x020e02c4
380 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE 0x020e02d4
381 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE 0x020e02d8
382 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B 0x020e02dc
383 #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY 0x020e02e0
384 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B 0x020e02e4
385 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B 0x020e02ec
386 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD 0x020e02f4
387 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK 0x020e02f8
388 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 0x020e02fc
389 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 0x020e0300
390 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 0x020e0304
391 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 0x020e0308
392 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 0x020e030c
393 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 0x020e0310
394 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 0x020e0314
395 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 0x020e0318
396 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P 0x020e050c
397 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 0x020e0510
398 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 0x020e0514
399 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P 0x020e0518
400 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P 0x020e051c
401 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 0x020e0520
402 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P 0x020e0524
403 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 0x020e0528
404 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 0x020e052c
405 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 0x020e0530
406 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 0x020e0534
407 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 0x020e0538
408 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 0x020e053c
409 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 0x020e0540
410 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 0x020e0544
411 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 0x020e0548
412 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 0x020e054c
413 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 0x020e0550
414 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 0x020e0554
415 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 0x020e0558
416 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 0x020e055c
417 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 0x020e0560
418 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 0x020e0564
419 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15 0x020e0568
420 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS 0x020e056c
421 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS 0x020e0578
422 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET 0x020e057c
423 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 0x020e0580
424 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 0x020e0584
425 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P 0x020e0588
426 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 0x020e058c
427 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 0x020e0590
428 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P 0x020e0594
429 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 0x020e0598
430 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 0x020e059c
431 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 0x020e05a0
432 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P 0x020e05a8
433 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x020e05ac
434 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P 0x020e05b0
435 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x020e05b4
436 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P 0x020e05b8
437 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 0x020e05bc
438 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P 0x020e05c0
439 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 0x020e05c4
440 #define IOMUXC_SW_PAD_CTL_GRP_B7DS 0x020e0748
441 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x020e074c
442 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x020e0750
443 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0 0x020e0754
444 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x020e0758
445 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1 0x020e075c
446 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2 0x020e0760
447 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3 0x020e0764
448 #define IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x020e0768
449 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4 0x020e076c
450 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x020e0770
451 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x020e0774
452 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5 0x020e0778
453 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6 0x020e077c
454 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7 0x020e0780
455 #define IOMUXC_SW_PAD_CTL_GRP_B0DS 0x020e0784
456 #define IOMUXC_SW_PAD_CTL_GRP_B1DS 0x020e0788
457 #define IOMUXC_SW_PAD_CTL_GRP_CTLDS 0x020e078c
458 #define IOMUXC_SW_PAD_CTL_GRP_B2DS 0x020e0794
459 #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 0x020e0798
460 #define IOMUXC_SW_PAD_CTL_GRP_B3DS 0x020e079c
461 #define IOMUXC_SW_PAD_CTL_GRP_B4DS 0x020e07a0
462 #define IOMUXC_SW_PAD_CTL_GRP_B5DS 0x020e07a4
463 #define IOMUXC_SW_PAD_CTL_GRP_B6DS 0x020e07a8
464 #define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT 0x020e091c
465 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e0920
469 #define IOMUXC_GPR1 0x020e0004
470 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17 0x020e0218
471 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 0x020e0330
472 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6 0x020e032c
473 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 0x020e0314
474 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 0x020e0318
475 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE 0x020e0270
476 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE 0x020e026c
477 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B 0x020e02a8
478 #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY 0x020e02a4
479 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B 0x020e0274
480 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B 0x020e027c
481 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD 0x020e033c
482 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK 0x020e0338
483 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 0x020e0284
484 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 0x020e0288
485 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 0x020e028c
486 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 0x020e0290
487 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 0x020e0294
488 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 0x020e0298
489 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 0x020e029c
490 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 0x020e02a0
491 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P 0x020e04d0
492 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 0x020e0484
493 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 0x020e0480
494 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P 0x020e04cc
495 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P 0x020e04c8
496 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 0x020e047c
497 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P 0x020e04c4
498 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 0x020e0478
499 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 0x020e0424
500 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 0x020e0428
501 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 0x020e0444
502 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 0x020e0448
503 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 0x020e044c
504 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 0x020e0450
505 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 0x020e0454
506 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 0x020e0458
507 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 0x020e045c
508 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 0x020e0460
509 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 0x020e042c
510 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 0x020e0430
511 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 0x020e0434
512 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 0x020e0438
513 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 0x020e043c
514 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15 0x020e0440
515 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS 0x020e0464
516 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS 0x020e0490
517 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET 0x020e0494
518 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 0x020e0498
519 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 0x020e049c
520 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P 0x020e04ac
521 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 0x020e04a0
522 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 0x020e04a4
523 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P 0x020e04b0
524 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 0x020e04a8
525 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 0x020e04b4
526 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 0x020e04b8
527 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P 0x020e04bc
528 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x020e0470
529 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P 0x020e04c0
530 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x020e0474
531 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P 0x020e04d4
532 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 0x020e0488
533 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P 0x020e04d8
534 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 0x020e048c
535 #define IOMUXC_SW_PAD_CTL_GRP_B7DS 0x020e0748
536 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x020e074c
537 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x020e0750
538 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x020e0754
539 #define IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x020e0754
540 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x020e075c
541 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x020e0760
542 #define IOMUXC_SW_PAD_CTL_GRP_B0DS 0x020e0784
543 #define IOMUXC_SW_PAD_CTL_GRP_B1DS 0x020e0788
544 #define IOMUXC_SW_PAD_CTL_GRP_CTLDS 0x020e078c
545 #define IOMUXC_SW_PAD_CTL_GRP_B2DS 0x020e0794
546 #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 0x020e0798
547 #define IOMUXC_SW_PAD_CTL_GRP_B3DS 0x020e079c
548 #define IOMUXC_SW_PAD_CTL_GRP_B4DS 0x020e07a0
549 #define IOMUXC_SW_PAD_CTL_GRP_B5DS 0x020e07a4
550 #define IOMUXC_SW_PAD_CTL_GRP_B6DS 0x020e07a8
551 #define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT 0x020e091c
552 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e0920
557 .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION)
559 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_reset)
560 /* RESET_OUT GPIO_7_12 */
561 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO17, 0x00000005)
563 MXC_DCD_ITEM(CCM_CS2CDR, 0x006336c1) /* CS2CDR default: 0x007236c1 */
565 MXC_DCD_ITEM(CCM_ANALOG_PLL_ENET, 0x00002001) /* ENET PLL */
567 /* enable all relevant clocks... */
568 MXC_DCD_ITEM(CCM_CCGR0, 0xf0c03f3f) /* default: 0xf0c03f0f APBH-DMA */
569 MXC_DCD_ITEM(CCM_CCGR1, 0xf0fc0c00) /* default: 0xf0fc0000 */
570 MXC_DCD_ITEM(CCM_CCGR2, 0xfc3ff0cc) /* default: 0xfc3ff00c I2C1 */
571 MXC_DCD_ITEM(CCM_CCGR3, 0x3ff00000) /* default: 0x3ff00000 */
572 MXC_DCD_ITEM(CCM_CCGR4, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */
573 MXC_DCD_ITEM(CCM_CCGR5, 0xff033f0f) /* default: 0xf0033f0f UART1 */
574 MXC_DCD_ITEM(CCM_CCGR6, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */
577 MXC_DCD_ITEM(IOMUXC_GPR1, 0x48640005) /* default: 0x48400005 ENET_CLK output */
578 /* UART1 pad config */
579 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7, 0x00000001) /* UART1 TXD */
580 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6, 0x00000001) /* UART1 RXD */
581 MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000003) /* UART1 RXD INPUT_SEL */
582 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0, 0x00000001) /* UART1 CTS */
583 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1, 0x00000001) /* UART1 RTS */
584 MXC_DCD_ITEM(IOMUXC_UART1_UART_RTS_B_SELECT_INPUT, 0x00000003) /* UART1 RTS INPUT_SEL */
587 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CLE, 0x00000000) /* NANDF_CLE: NANDF_CLE */
588 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_ALE, 0x00000000) /* NANDF_ALE: NANDF_ALE */
589 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B, 0x00000000) /* NANDF_WP_B: NANDF_WPn */
590 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_READY, 0x00000000) /* NANDF_RB0: NANDF_READY0 */
591 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B, 0x00000000) /* NANDF_CS0: NANDF_CS0 */
592 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD4_CMD, 0x00000001) /* SD4_CMD: NANDF_RDn */
593 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD4_CLK, 0x00000001) /* SD4_CLK: NANDF_WRn */
594 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00, 0x00000000) /* NANDF_D0: NANDF_D0 */
595 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01, 0x00000000) /* NANDF_D1: NANDF_D1 */
596 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02, 0x00000000) /* NANDF_D2: NANDF_D2 */
597 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03, 0x00000000) /* NANDF_D3: NANDF_D3 */
598 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04, 0x00000000) /* NANDF_D4: NANDF_D4 */
599 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05, 0x00000000) /* NANDF_D5: NANDF_D5 */
600 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06, 0x00000000) /* NANDF_D6: NANDF_D6 */
601 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07, 0x00000000) /* NANDF_D7: NANDF_D7 */
604 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B, 0x00000000) /* NANDF_CS2: NANDF_CS2 */
606 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, DQM_MASK)
607 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, DQM_MASK)
608 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, DQM_MASK)
609 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, DQM_MASK)
610 #if PHYS_SDRAM_1_WIDTH == 64
611 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4, DQM_MASK)
612 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5, DQM_MASK)
613 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6, DQM_MASK)
614 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7, DQM_MASK)
618 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00, DDR_ADDR_MASK)
619 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01, DDR_ADDR_MASK)
620 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02, DDR_ADDR_MASK)
621 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03, DDR_ADDR_MASK)
622 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04, DDR_ADDR_MASK)
623 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05, DDR_ADDR_MASK)
624 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06, DDR_ADDR_MASK)
625 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07, DDR_ADDR_MASK)
626 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08, DDR_ADDR_MASK)
627 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09, DDR_ADDR_MASK)
628 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10, DDR_ADDR_MASK)
629 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11, DDR_ADDR_MASK)
630 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12, DDR_ADDR_MASK)
631 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13, DDR_ADDR_MASK)
632 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14, DDR_ADDR_MASK)
633 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15, DDR_ADDR_MASK)
635 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS, DDR_CTRL_MASK)
637 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS, DDR_CTRL_MASK)
638 /* DRAM_SDCLK[0..1] */
639 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P, SDCLK_MASK)
640 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P, SDCLK_MASK)
642 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET, DDR_CTRL_MASK)
643 /* DRAM_SDCKE[0..1] */
644 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0, SDCKE_MASK)
645 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1, SDCKE_MASK)
646 /* DRAM_SDBA[0..2] */
647 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0, 0x00000000)
648 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1, 0x00000000)
649 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2, 0x00000000)
650 /* DRAM_SDODT[0..1] */
651 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0, SDODT_MASK)
652 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1, SDODT_MASK)
654 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B0DS, DSE_MASK)
655 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B1DS, DSE_MASK)
656 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B2DS, DSE_MASK)
657 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B3DS, DSE_MASK)
658 #if PHYS_SDRAM_1_WIDTH == 64
659 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B4DS, DSE_MASK)
660 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B5DS, DSE_MASK)
661 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B6DS, DSE_MASK)
662 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B7DS, DSE_MASK)
665 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_ADDDS, DSE_MASK)
667 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL, DDR_MODE_MASK)
669 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPKE, 0x00000000)
671 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE, DDR_MODE_MASK)
673 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_CTLDS, DSE_MASK)
675 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE, DDR_SEL_MASK)
677 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPK, 1 << PUE_SHIFT)
679 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRHYS, 0x00000000)
683 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0, ODT_MASK)
684 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1, ODT_MASK)
685 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2, ODT_MASK)
686 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3, ODT_MASK)
687 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4, ODT_MASK)
688 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5, ODT_MASK)
689 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6, ODT_MASK)
690 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7, ODT_MASK)
693 /* SDRAM initialization */
694 /* MPRDDQBY[0..7]DL */
695 MXC_DCD_ITEM(MMDC1_MPRDDQBY0DL, 0x33333333)
696 MXC_DCD_ITEM(MMDC1_MPRDDQBY1DL, 0x33333333)
697 MXC_DCD_ITEM(MMDC1_MPRDDQBY2DL, 0x33333333)
698 MXC_DCD_ITEM(MMDC1_MPRDDQBY3DL, 0x33333333)
699 #if PHYS_SDRAM_1_WIDTH == 64
700 MXC_DCD_ITEM(MMDC2_MPRDDQBY0DL, 0x33333333)
701 MXC_DCD_ITEM(MMDC2_MPRDDQBY1DL, 0x33333333)
702 MXC_DCD_ITEM(MMDC2_MPRDDQBY2DL, 0x33333333)
703 MXC_DCD_ITEM(MMDC2_MPRDDQBY3DL, 0x33333333)
706 MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL | 2) /* reset MMDC FSM */
708 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDMISC, 0x00000002)
709 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack)
711 /* MSDSCR Conf Req */
712 MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008000)
714 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDSCR, 0x00004000)
715 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_calib)
717 MXC_DCD_ITEM(MMDC1_MDCTL, MDCTL_VAL)
719 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, 0x40000000)
720 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib)
722 MXC_DCD_ITEM(MMDC1_MDCFG0, MDCFG0_VAL)
723 MXC_DCD_ITEM(MMDC1_MDCFG1, MDCFG1_VAL)
724 MXC_DCD_ITEM(MMDC1_MDCFG2, MDCFG2_VAL)
725 MXC_DCD_ITEM(MMDC1_MDRWD, 0x000026d2) /* MDRWD */
726 MXC_DCD_ITEM(MMDC1_MDOR, MDOR_VAL)
727 MXC_DCD_ITEM(MMDC1_MDOTC, MDOTC_VAL)
728 MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_0)
729 MXC_DCD_ITEM(MMDC1_MDASP, 0x00000017) /* MDASP */
732 MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 0, mr0_val))
733 MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 1, mr1_val))
734 MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 2, mr2_val))
735 MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0))
736 #if BANK_ADDR_BITS > 1
738 MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 0, mr0_val))
739 MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 1, mr1_val))
740 MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 2, mr2_val))
741 MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */
744 MXC_DCD_ITEM(MMDC1_MDREF, 0x0000c000) /* disable refresh */
746 MXC_DCD_ITEM(MMDC1_MPODTCTRL, 0x00011112) /* MPODTCTRL */
747 #if PHYS_SDRAM_1_WIDTH == 64
748 MXC_DCD_ITEM(MMDC2_MPODTCTRL, 0x00011112)
751 /* DDR3 calibration */
752 MXC_DCD_ITEM(MMDC1_MPPDCMPR2, 0x00000003) /* select default compare pattern for DQ calibration */
753 MXC_DCD_ITEM(MMDC1_MAPSR, 0x00011007)
756 MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008010) /* precharge all */
757 MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008040) /* MRS: ZQ calibration */
759 MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa139002b)
760 #if PHYS_SDRAM_1_WIDTH == 64
761 MXC_DCD_ITEM(MMDC2_MPZQHWCTRL, 0xa138002b)
765 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPZQHWCTRL, 0x00010000)
766 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib)
769 MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1380000)
770 #if PHYS_SDRAM_1_WIDTH == 64
771 MXC_DCD_ITEM(MMDC2_MPZQHWCTRL, 0xa1380000)
774 MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
775 MXC_DCD_ITEM(MMDC1_MDSCR, 0x00808231) /* MRS: start write leveling */
777 MXC_DCD_ITEM(MMDC1_MPWLGCR, 0x00000001) /* initiate Write leveling */
779 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWLGCR, 0x00000001)
780 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWLGCR, 0x00000f00)
781 #if PHYS_SDRAM_1_WIDTH == 64
782 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWLGCR, 0x00000001)
783 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWLGCR, 0x00000f00)
785 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset)
787 MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa138002b)
788 #if PHYS_SDRAM_1_WIDTH == 64
789 MXC_DCD_ITEM(MMDC2_MPZQHWCTRL, 0xa138002b)
792 MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: end write leveling */
794 /* DQS gating calibration */
795 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK | 0x7000) /* enable Pullups on DQS pads */
796 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK | 0x7000)
797 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK | 0x7000)
798 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK | 0x7000)
799 #if PHYS_SDRAM_1_WIDTH == 64
800 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK | 0x7000)
801 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK | 0x7000)
802 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK | 0x7000)
803 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK | 0x7000)
805 MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL | (7 << 6) | (3 << 16)) /* RALAT/WALAT max. */
807 MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */
808 MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
810 MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
811 MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
812 MXC_DCD_ITEM(MMDC1_MPMUR0, 0x00000800)
813 #if PHYS_SDRAM_1_WIDTH == 64
814 MXC_DCD_ITEM(MMDC2_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
815 MXC_DCD_ITEM(MMDC2_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
816 MXC_DCD_ITEM(MMDC2_MPMUR0, 0x00000800)
819 MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue fifo reset */
821 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000)
822 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset2)
823 MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue 2nd fifo reset */
825 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000)
826 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib)
827 MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x50800000) /* choose 32 wait cycles and start DQS calib. */
829 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x10000000)
830 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x00001000)
831 #if PHYS_SDRAM_1_WIDTH == 64
832 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPDGCTRL0, 0x10000000)
833 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPDGCTRL0, 0x00001000)
835 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib)
837 /* DRAM_SDQS[0..7] pad config */
838 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK)
839 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK)
840 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK)
841 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK)
842 #if PHYS_SDRAM_1_WIDTH == 64
843 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK)
844 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK)
845 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK)
846 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK)
849 MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL)
851 /* Read delay calibration */
852 MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
853 MXC_DCD_ITEM(MMDC1_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_RD_DL_EN */
855 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x00000010)
856 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000000f)
857 #if PHYS_SDRAM_1_WIDTH == 64
858 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x00000010)
859 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x0000000f)
861 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib)
863 MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
864 MXC_DCD_ITEM(MMDC1_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
866 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x00000010)
867 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000000f)
868 #if PHYS_SDRAM_1_WIDTH == 64
869 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x00000010)
870 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x0000000f)
872 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack_clr)
874 MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
875 MXC_DCD_ITEM(MMDC1_MDREF, 0x00005800) /* MDREF */
876 MXC_DCD_ITEM(MMDC1_MAPSR, 0x00011006) /* MAPSR */
877 MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_1)
879 /* MDSCR: Normal operation */
880 MXC_DCD_ITEM(MMDC1_MDSCR, 0x00000000)
883 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDSCR, 0x00004000)
885 .ifgt dcd_end - dcd_start - 1768
886 .error "DCD too large!"