2 #include <configs/tx6q.h>
3 #include <asm/arch/imx-regs.h>
5 #define DEBUG_LED_BIT 20
6 #define LED_GPIO_BASE GPIO2_BASE_ADDR
7 #define LED_MUX_OFFSET 0x0ec
8 #define LED_MUX_MODE 0x15
10 #define SDRAM_CLK CONFIG_SYS_SDRAM_CLK
12 #ifdef PHYS_SDRAM_2_SIZE
13 #define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
15 #define SDRAM_SIZE PHYS_SDRAM_1_SIZE
18 #define CPU_2_BE_32(l) \
19 ((((l) << 24) & 0xFF000000) | \
20 (((l) << 8) & 0x00FF0000) | \
21 (((l) >> 8) & 0x0000FF00) | \
22 (((l) >> 24) & 0x000000FF))
24 #define CHECK_DCD_ADDR(a) ( \
25 ((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ || \
26 ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ || \
27 ((a) >= 0x020C8000 && (a) <= 0x020C8FFF) /* ANALOG */ || \
28 ((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ || \
29 ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ || \
30 ((a) >= 0x08000000 && (a) <= 0x0FFEFFFF) /* EIM (CS0) */ || \
31 ((a) >= 0x10000000 && (a) <= 0xFFFFFFFF) /* SDRAM */)
33 .macro mxc_dcd_item addr, val
34 .ifne CHECK_DCD_ADDR(\addr)
35 .word CPU_2_BE_32(\addr), CPU_2_BE_32(\val)
37 .error "Address \addr not accessible from DCD"
41 #define MXC_DCD_ITEM(addr, val) mxc_dcd_item addr, val
43 #define MXC_DCD_CMD_SZ_BYTE 1
44 #define MXC_DCD_CMD_SZ_SHORT 2
45 #define MXC_DCD_CMD_SZ_WORD 4
46 #define MXC_DCD_CMD_FLAG_WRITE 0x0
47 #define MXC_DCD_CMD_FLAG_CLR 0x1
48 #define MXC_DCD_CMD_FLAG_SET 0x3
49 #define MXC_DCD_CMD_FLAG_CHK_ANY (1 << 0)
50 #define MXC_DCD_CMD_FLAG_CHK_SET (1 << 1)
51 #define MXC_DCD_CMD_FLAG_CHK_CLR (0 << 1)
53 #define MXC_DCD_CMD_WRT(type, flags, next) \
54 .word CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type))
56 #define MXC_DCD_CMD_CHK(type, flags, addr, mask) \
57 .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)),\
58 CPU_2_BE_32(addr), CPU_2_BE_32(mask)
60 #define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \
61 .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\
62 CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
64 #define MXC_DCD_CMD_NOP \
65 .word CPU_2_BE_32((0xc0 << 24) | (4 << 8))
67 #define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
68 #define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
70 .macro CK_VAL, name, clks, offs, max
74 .ifle \clks - \offs - \max
75 .set \name, \clks - \offs
77 .error "Value \clks out of range for parameter \name"
82 .macro NS_VAL, name, ns, offs, max
86 CK_VAL \name, NS_TO_CK(\ns), \offs, \max
90 .macro CK_MAX, name, ck1, ck2, offs, max
92 CK_VAL \name, \ck1, \offs, \max
94 CK_VAL \name, \ck2, \offs, \max
98 #define MDMISC_DDR_TYPE_DDR3 0
99 #define MDMISC_DDR_TYPE_LPDDR2 1
100 #define MDMISC_DDR_TYPE_DDR2 2
102 #define DIV_ROUND_UP(m,d) (((m) + (d) - 1) / (d))
104 #define MDOR_CLK_PERIOD_ns 15258 /* base clock for MDOR values */
107 #if SDRAM_SIZE > PHYS_SDRAM_1_SIZE
108 #define BANK_ADDR_BITS 2
110 #define BANK_ADDR_BITS 1
112 #define SDRAM_BURST_LENGTH 8
116 #define ADDR_MIRROR 1
117 #define DDR_TYPE MDMISC_DDR_TYPE_DDR3
119 /* 512/1024MiB SDRAM: NT5CB128M16P-CG */
121 NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */
122 CK_MAX tXS, tRFC + 1 + NS_TO_CK(10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
123 CK_MAX tXP, 3, NS_TO_CK(6), 1, 7 /* clks - 1 (0..7) */ /* max(6ns, 3*CK) */
124 CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */
125 NS_VAL tFAW, 45, 1, 31 /* clks - 1 (0..31) */
126 CK_VAL tCL, 8, 3, 8 /* clks - 3 (0..8) CAS Latency */
129 NS_VAL tRCD, 14, 1, 7 /* clks - 1 (0..7) */
130 NS_VAL tRP, 14, 1, 7 /* clks - 1 (0..7) */
131 NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) */
132 NS_VAL tRAS, 36, 1, 31 /* clks - 1 (0..31) */
133 CK_VAL tRPA, 0, 0, 1 /* clks (0..1) */
134 NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */
135 CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */
136 CK_VAL tCWL, 6, 2, 6 /* clks - 2 (0..6) */
139 CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */
140 CK_MAX tRTP, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
141 CK_MAX tWTR, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
142 CK_MAX tRRD, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
145 CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
146 #define tSDE_RST (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2)
147 #define tRST_CKE (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2)
150 NS_VAL tAOFPD, 9, 1, 7 /* clks - 1 (0..7) */
151 NS_VAL tAONPD, 9, 1, 7 /* clks - 1 (0..7) */
152 CK_VAL tANPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
153 CK_VAL tAXPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
154 CK_VAL tODTLon tCWL, 1, 7 /* clks - 1 (0..7) */
155 CK_VAL tODTLoff tCWL, 1, 31 /* clks - 1 (0..31) */
158 CK_MAX tCKE, NS_TO_CK(6), 3, 1, 7
159 CK_MAX tCKSRX, NS_TO_CK(10), 5, 0, 7
160 CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7
167 #define MDPDC_VAL_0 ( \
172 (BOTH_CS_PD << 6) | \
177 #define MDPDC_VAL_1 (MDPDC_VAL_0 | \
182 #define ROW_ADDR_BITS 14
183 #define COL_ADDR_BITS 10
186 .set mr0_val, ((1 << 8) /* DLL Reset */ | \
187 ((tWR + 1 - 4) << 9) | \
188 (((tCL + 3) - 4) << 4))
190 .set mr0_val, ((1 << 8) /* DLL Reset */ | \
191 (((tWR + 1) / 2) << 9) | \
192 (((tCL + 3) - 4) << 4))
195 #define MDSCR_MRS_VAL(cs, mr, val) (((val) << 16) | \
196 (1 << 15) /* CON REQ */ | \
197 (3 << 4) /* MRS command */ | \
201 #define mr1_val 0x0040
202 #define mr2_val 0x0408
204 #define MDCFG0_VAL ( \
212 #define MDCFG1_VAL ( \
222 #define MDCFG2_VAL ( \
228 #define BURST_LEN (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
229 #define MDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \
230 ((COL_ADDR_BITS - 9) << 20) | \
231 (BURST_LEN << 19) | \
232 (2 << 16) | /* SDRAM bus width */ \
233 ((-1) << (32 - BANK_ADDR_BITS)))
235 #define MDMISC_VAL ((ADDR_MIRROR << 19) | \
242 #define MDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
244 #define MDOTC_VAL ((tAOFPD << 27) | \
255 .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
271 .long CONFIG_U_BOOT_IMG_SIZE
275 #define DCD_VERSION 0x40
277 #define CLKCTL_CCGR0 0x68
278 #define CLKCTL_CCGR1 0x6c
279 #define CLKCTL_CCGR2 0x70
280 #define CLKCTL_CCGR3 0x74
281 #define CLKCTL_CCGR4 0x78
282 #define CLKCTL_CCGR5 0x7c
283 #define CLKCTL_CCGR6 0x80
284 #define CLKCTL_CCGR7 0x84
285 #define CLKCTL_CMEOR 0x88
287 #define DDR_SEL_VAL 3
291 #define DDR_SEL_SHIFT 18
292 #define DDR_MODE_SHIFT 17
300 #define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT)
301 #define DDR_MODE_MASK (1 << DDR_MODE_SHIFT)
302 #define DSE_MASK (DSE_VAL << DSE_SHIFT)
303 #define ODT_MASK (ODT_VAL << ODT_SHIFT)
305 #define DQM_MASK (DDR_MODE_MASK | DSE_MASK)
306 #define SDQS_MASK DSE_MASK
307 #define SDODT_MASK (DSE_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
308 #define SDCLK_MASK (DDR_MODE_MASK | DSE_MASK)
309 #define SDCKE_MASK ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
310 #define DDR_ADDR_MASK 0
311 #define DDR_CTRL_MASK (DDR_MODE_MASK | DSE_MASK)
314 .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION)
316 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_reset)
317 /* RESET_OUT GPIO_7_12 */
318 MXC_DCD_ITEM(0x020e024c, 0x00000005)
320 MXC_DCD_ITEM(0x020c402c, 0x006336c1) /* CS2CDR default: 0x007236c1 */
322 MXC_DCD_ITEM(0x020c80e0, 0x00002001) /* ENET PLL */
324 /* enable all relevant clocks... */
325 MXC_DCD_ITEM(0x020c4068, 0xf0c03f3f) /* default: 0xf0c03f0f APBH-DMA */
326 MXC_DCD_ITEM(0x020c406c, 0xf0fc0c00) /* default: 0xf0fc0000 */
327 MXC_DCD_ITEM(0x020c4070, 0xfc3ff0cc) /* default: 0xfc3ff00c I2C1 */
328 MXC_DCD_ITEM(0x020c4074, 0x3ff00000) /* default: 0x3ff00000 */
329 MXC_DCD_ITEM(0x020c4078, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */
330 MXC_DCD_ITEM(0x020c407c, 0xff033f0f) /* default: 0xf0033f0f UART1 */
331 MXC_DCD_ITEM(0x020c4080, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */
334 MXC_DCD_ITEM(0x020e0004, 0x48640005) /* default: 0x48400005 ENET_CLK output */
335 /* UART1 pad config */
336 MXC_DCD_ITEM(0x020e02a8, 0x00000001) /* UART1 TXD */
337 MXC_DCD_ITEM(0x020e02ac, 0x00000001) /* UART1 RXD */
338 MXC_DCD_ITEM(0x020e0920, 0x00000003) /* UART1 RXD INPUT_SEL */
339 MXC_DCD_ITEM(0x020e02c0, 0x00000001) /* UART1 CTS */
340 MXC_DCD_ITEM(0x020e02c4, 0x00000001) /* UART1 RTS */
341 MXC_DCD_ITEM(0x020e091c, 0x00000003) /* UART1 RTS INPUT_SEL */
344 MXC_DCD_ITEM(0x020e02d4, 0x00000000) /* NANDF_CLE: NANDF_CLE */
345 MXC_DCD_ITEM(0x020e02d8, 0x00000000) /* NANDF_ALE: NANDF_ALE */
346 MXC_DCD_ITEM(0x020e02dc, 0x00000000) /* NANDF_WP_B: NANDF_WPn */
347 MXC_DCD_ITEM(0x020e02e0, 0x00000000) /* NANDF_RB0: NANDF_READY0 */
348 MXC_DCD_ITEM(0x020e02e4, 0x00000000) /* NANDF_CS0: NANDF_CS0 */
349 MXC_DCD_ITEM(0x020e02f4, 0x00000001) /* SD4_CMD: NANDF_RDn */
350 MXC_DCD_ITEM(0x020e02f8, 0x00000001) /* SD4_CLK: NANDF_WRn */
351 MXC_DCD_ITEM(0x020e02fc, 0x00000000) /* NANDF_D0: NANDF_D0 */
352 MXC_DCD_ITEM(0x020e0300, 0x00000000) /* NANDF_D1: NANDF_D1 */
353 MXC_DCD_ITEM(0x020e0304, 0x00000000) /* NANDF_D2: NANDF_D2 */
354 MXC_DCD_ITEM(0x020e0308, 0x00000000) /* NANDF_D3: NANDF_D3 */
355 MXC_DCD_ITEM(0x020e030c, 0x00000000) /* NANDF_D4: NANDF_D4 */
356 MXC_DCD_ITEM(0x020e0310, 0x00000000) /* NANDF_D5: NANDF_D5 */
357 MXC_DCD_ITEM(0x020e0314, 0x00000000) /* NANDF_D6: NANDF_D6 */
358 MXC_DCD_ITEM(0x020e0318, 0x00000000) /* NANDF_D7: NANDF_D7 */
361 MXC_DCD_ITEM(0x020e02ec, 0x00000000) /* NANDF_CS2: NANDF_CS2 */
363 MXC_DCD_ITEM(0x020e05ac, DQM_MASK)
364 MXC_DCD_ITEM(0x020e05b4, DQM_MASK)
365 MXC_DCD_ITEM(0x020e0528, DQM_MASK)
366 MXC_DCD_ITEM(0x020e0520, DQM_MASK)
367 MXC_DCD_ITEM(0x020e0514, DQM_MASK)
368 MXC_DCD_ITEM(0x020e0510, DQM_MASK)
369 MXC_DCD_ITEM(0x020e05bc, DQM_MASK)
370 MXC_DCD_ITEM(0x020e05c4, DQM_MASK)
372 MXC_DCD_ITEM(0x020e052c, DDR_ADDR_MASK)
373 MXC_DCD_ITEM(0x020e0530, DDR_ADDR_MASK)
374 MXC_DCD_ITEM(0x020e0534, DDR_ADDR_MASK)
375 MXC_DCD_ITEM(0x020e0538, DDR_ADDR_MASK)
376 MXC_DCD_ITEM(0x020e053c, DDR_ADDR_MASK)
377 MXC_DCD_ITEM(0x020e0540, DDR_ADDR_MASK)
378 MXC_DCD_ITEM(0x020e0544, DDR_ADDR_MASK)
379 MXC_DCD_ITEM(0x020e0548, DDR_ADDR_MASK)
380 MXC_DCD_ITEM(0x020e054c, DDR_ADDR_MASK)
381 MXC_DCD_ITEM(0x020e0550, DDR_ADDR_MASK)
382 MXC_DCD_ITEM(0x020e0554, DDR_ADDR_MASK)
383 MXC_DCD_ITEM(0x020e0558, DDR_ADDR_MASK)
384 MXC_DCD_ITEM(0x020e055c, DDR_ADDR_MASK)
385 MXC_DCD_ITEM(0x020e0560, DDR_ADDR_MASK)
386 MXC_DCD_ITEM(0x020e0564, DDR_ADDR_MASK)
387 MXC_DCD_ITEM(0x020e0568, DDR_ADDR_MASK)
389 MXC_DCD_ITEM(0x020e056c, DDR_CTRL_MASK)
391 MXC_DCD_ITEM(0x020e0578, DDR_CTRL_MASK)
392 /* DRAM_SDCLK[0..1] */
393 MXC_DCD_ITEM(0x020e0588, SDCLK_MASK)
394 MXC_DCD_ITEM(0x020e0594, SDCLK_MASK)
396 MXC_DCD_ITEM(0x020e057c, DDR_CTRL_MASK)
397 /* DRAM_SDCKE[0..1] */
398 MXC_DCD_ITEM(0x020e0590, SDCKE_MASK)
399 MXC_DCD_ITEM(0x020e0598, SDCKE_MASK)
400 /* DRAM_SDBA[0..2] */
401 MXC_DCD_ITEM(0x020e0580, 0x00000000)
402 MXC_DCD_ITEM(0x020e0584, 0x00000000)
403 MXC_DCD_ITEM(0x020e058c, 0x00000000)
404 /* DRAM_SDODT[0..1] */
405 MXC_DCD_ITEM(0x020e059c, SDODT_MASK)
406 MXC_DCD_ITEM(0x020e05a0, SDODT_MASK)
408 MXC_DCD_ITEM(0x020e0784, DSE_MASK)
409 MXC_DCD_ITEM(0x020e0788, DSE_MASK)
410 MXC_DCD_ITEM(0x020e0794, DSE_MASK)
411 MXC_DCD_ITEM(0x020e079c, DSE_MASK)
412 MXC_DCD_ITEM(0x020e07a0, DSE_MASK)
413 MXC_DCD_ITEM(0x020e07a4, DSE_MASK)
414 MXC_DCD_ITEM(0x020e07a8, DSE_MASK)
415 MXC_DCD_ITEM(0x020e0748, DSE_MASK)
417 MXC_DCD_ITEM(0x020e074c, DSE_MASK)
419 MXC_DCD_ITEM(0x020e0750, DDR_MODE_MASK)
421 MXC_DCD_ITEM(0x020e0758, 0x00000000)
423 MXC_DCD_ITEM(0x020e0774, DDR_MODE_MASK)
425 MXC_DCD_ITEM(0x020e078c, DSE_MASK)
427 MXC_DCD_ITEM(0x020e0798, DDR_SEL_MASK)
429 MXC_DCD_ITEM(0x020e0768, 1 << PUE_SHIFT)
431 MXC_DCD_ITEM(0x020e0770, 0x00000000)
433 MXC_DCD_ITEM(0x020e0754, ODT_MASK)
434 MXC_DCD_ITEM(0x020e075c, ODT_MASK)
435 MXC_DCD_ITEM(0x020e0760, ODT_MASK)
436 MXC_DCD_ITEM(0x020e0764, ODT_MASK)
437 MXC_DCD_ITEM(0x020e076c, ODT_MASK)
438 MXC_DCD_ITEM(0x020e0778, ODT_MASK)
439 MXC_DCD_ITEM(0x020e077c, ODT_MASK)
440 MXC_DCD_ITEM(0x020e0780, ODT_MASK)
442 /* SDRAM initialization */
443 /* MPRDDQBY[0..7]DL */
444 MXC_DCD_ITEM(0x021b081c, 0x33333333)
445 MXC_DCD_ITEM(0x021b481c, 0x33333333)
446 MXC_DCD_ITEM(0x021b0820, 0x33333333)
447 MXC_DCD_ITEM(0x021b4820, 0x33333333)
448 MXC_DCD_ITEM(0x021b0824, 0x33333333)
449 MXC_DCD_ITEM(0x021b4824, 0x33333333)
450 MXC_DCD_ITEM(0x021b0828, 0x33333333)
451 MXC_DCD_ITEM(0x021b4828, 0x33333333)
453 MXC_DCD_ITEM(0x021b0018, MDMISC_VAL | 2) /* reset MMDC FSM */
455 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0018, 0x00000002)
456 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack)
458 /* MSDSCR Conf Req */
459 MXC_DCD_ITEM(0x021b001c, 0x00008000)
461 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, 0x021b001c, 0x00004000)
462 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_calib)
464 MXC_DCD_ITEM(0x021b0000, MDCTL_VAL)
466 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, 0x021b0018, 0x40000000)
467 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib)
469 MXC_DCD_ITEM(0x021b000c, MDCFG0_VAL)
470 MXC_DCD_ITEM(0x021b0010, MDCFG1_VAL)
471 MXC_DCD_ITEM(0x021b0014, MDCFG2_VAL)
472 MXC_DCD_ITEM(0x021b002c, 0x000026d2) /* MDRWD */
473 MXC_DCD_ITEM(0x021b0030, MDOR_VAL)
474 MXC_DCD_ITEM(0x021b0008, MDOTC_VAL)
475 MXC_DCD_ITEM(0x021b0004, MDPDC_VAL_0)
476 MXC_DCD_ITEM(0x021b0040, 0x00000027) /* MDASP */
479 MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 0, mr0_val))
480 MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 1, mr1_val))
481 MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 2, mr2_val))
482 MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 3, 0))
483 #if BANK_ADDR_BITS > 1
485 MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 0, mr0_val))
486 MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 1, mr1_val))
487 MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 2, mr2_val))
488 MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */
490 MXC_DCD_ITEM(0x021b0020, 0x0000c000) /* disable refresh */
492 MXC_DCD_ITEM(0x021b0818, 0x00011112) /* MPODTCTRL */
493 MXC_DCD_ITEM(0x021b4818, 0x00011112)
495 /* DDR3 calibration */
496 MXC_DCD_ITEM(0x021b0890, 0x00000003) /* select default compare pattern for DQ calibration */
497 MXC_DCD_ITEM(0x021b0404, 0x00011007)
500 MXC_DCD_ITEM(0x021b001c, 0x04008010) /* precharge all */
501 MXC_DCD_ITEM(0x021b001c, 0x04008040) /* MRS: ZQ calibration */
503 MXC_DCD_ITEM(0x021b4800, 0xa138002b)
504 MXC_DCD_ITEM(0x021b0800, 0xa139002b)
506 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0800, 0x00010000)
507 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib)
510 MXC_DCD_ITEM(0x021b4800, 0xa1380000)
511 MXC_DCD_ITEM(0x021b0800, 0xa1380000)
513 MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
514 MXC_DCD_ITEM(0x021b001c, 0x00808231) /* MRS: start write leveling */
516 MXC_DCD_ITEM(0x021b0808, 0x00000001) /* initiate Write leveling */
518 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0808, 0x00000001)
519 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0808, 0x00000f00)
520 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4808, 0x00000001)
521 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4808, 0x00000f00)
522 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset)
524 MXC_DCD_ITEM(0x021b0800, 0xa138002b)
525 MXC_DCD_ITEM(0x021b4800, 0xa138002b)
527 MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: end write leveling */
529 /* DQS gating calibration */
530 MXC_DCD_ITEM(0x020e05a8, SDQS_MASK | 0x7000) /* enable Pullups on DQS pads */
531 MXC_DCD_ITEM(0x020e05b0, SDQS_MASK | 0x7000)
532 MXC_DCD_ITEM(0x020e0524, SDQS_MASK | 0x7000)
533 MXC_DCD_ITEM(0x020e051c, SDQS_MASK | 0x7000)
534 MXC_DCD_ITEM(0x020e0518, SDQS_MASK | 0x7000)
535 MXC_DCD_ITEM(0x020e050c, SDQS_MASK | 0x7000)
536 MXC_DCD_ITEM(0x020e05b8, SDQS_MASK | 0x7000)
537 MXC_DCD_ITEM(0x020e05c0, SDQS_MASK | 0x7000)
538 MXC_DCD_ITEM(0x021b0018, MDMISC_VAL | (7 << 6) | (3 << 16)) /* RALAT/WALAT max. */
540 MXC_DCD_ITEM(0x021b001c, 0x00008020) /* issue one refresh cycle */
541 MXC_DCD_ITEM(0x021b001c, 0x04008050) /* precharge all to bank 0 */
543 MXC_DCD_ITEM(0x021b0848, 0x40404040) /* DQ RD Delay default values */
544 MXC_DCD_ITEM(0x021b4848, 0x40404040)
545 MXC_DCD_ITEM(0x021b0850, 0x40404040) /* DQ WR Delay default values */
546 MXC_DCD_ITEM(0x021b4850, 0x40404040)
547 MXC_DCD_ITEM(0x021b48b8, 0x00000800)
548 MXC_DCD_ITEM(0x021b08b8, 0x00000800)
550 MXC_DCD_ITEM(0x021b083c, 0x80000000) /* issue fifo reset */
552 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x80000000)
553 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset2)
554 MXC_DCD_ITEM(0x021b083c, 0x80000000) /* issue 2nd fifo reset */
556 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x80000000)
557 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib)
558 MXC_DCD_ITEM(0x021b083c, 0x50800000) /* choose 32 wait cycles and start DQS calib. */
560 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x10000000)
561 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x00001000)
562 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b483c, 0x10000000)
563 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b483c, 0x00001000)
564 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib)
566 /* DRAM_SDQS[0..7] pad config */
567 MXC_DCD_ITEM(0x020e05a8, SDQS_MASK)
568 MXC_DCD_ITEM(0x020e05b0, SDQS_MASK)
569 MXC_DCD_ITEM(0x020e0524, SDQS_MASK)
570 MXC_DCD_ITEM(0x020e051c, SDQS_MASK)
571 MXC_DCD_ITEM(0x020e0518, SDQS_MASK)
572 MXC_DCD_ITEM(0x020e050c, SDQS_MASK)
573 MXC_DCD_ITEM(0x020e05b8, SDQS_MASK)
574 MXC_DCD_ITEM(0x020e05c0, SDQS_MASK)
576 MXC_DCD_ITEM(0x021b0018, MDMISC_VAL)
578 /* Read delay calibration */
579 MXC_DCD_ITEM(0x021b001c, 0x04008050) /* precharge all to bank 0 */
580 MXC_DCD_ITEM(0x021b0860, 0x00000030) /* MPRDDLHWCTL: HW_RD_DL_EN */
582 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0860, 0x00000010)
583 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4860, 0x00000010)
584 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0860, 0x0000000f)
585 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4860, 0x0000000f)
586 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib)
588 MXC_DCD_ITEM(0x021b001c, 0x04008050) /* precharge all to bank 0 */
589 MXC_DCD_ITEM(0x021b0864, 0x00000030) /* start WR DL calibration */
591 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0864, 0x00000010)
592 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4864, 0x00000010)
593 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0864, 0x0000000f)
594 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4864, 0x0000000f)
595 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack_clr)
597 MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
598 MXC_DCD_ITEM(0x021b0020, 0x00005800) /* MDREF */
599 MXC_DCD_ITEM(0x021b0404, 0x00011006) /* MAPSR */
600 MXC_DCD_ITEM(0x021b0004, MDPDC_VAL_1)
602 /* MDSCR: Normal operation */
603 MXC_DCD_ITEM(0x021b001c, 0x00000000)
605 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b001c, 0x00004000)
607 .ifgt dcd_end - dcd_start - 1768
608 .error "DCD too large!"