board/karo/tx6q/tx6q.c

   1 /*
   2  * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22 //#define DEBUG
  23 //#define TIMER_TEST
  24
  25 #include <common.h>
  26 #include <errno.h>
  27 #include <libfdt.h>
  28 #include <fdt_support.h>
  29 #include <lcd.h>
  30 #include <netdev.h>
  31 #include <mmc.h>
  32 #include <fsl_esdhc.h>
  33 #include <video_fb.h>
  34 #include <ipu.h>
  35 #include <mx2fb.h>
  36 #include <linux/fb.h>
  37 #include <i2c.h>
  38 #include <asm/io.h>
  39 #include <asm/gpio.h>
  40 #include <asm/arch/iomux-mx6.h>
  41 #include <asm/arch/clock.h>
  42 #include <asm/arch/imx-regs.h>
  43 #include <asm/arch/crm_regs.h>
  44 #include <asm/arch/sys_proto.h>
  45
  46 #include "../common/karo.h"
  47
  48 #define TX6Q_FEC_RST_GPIO               IMX_GPIO_NR(7, 6)
  49 #define TX6Q_FEC_PWR_GPIO               IMX_GPIO_NR(3, 20)
  50 #define TX6Q_FEC_INT_GPIO               IMX_GPIO_NR(2, 4)
  51 #define TX6Q_LED_GPIO                   IMX_GPIO_NR(2, 20)
  52
  53 #define TX6Q_LCD_PWR_GPIO               IMX_GPIO_NR(2, 31)
  54 #define TX6Q_LCD_RST_GPIO               IMX_GPIO_NR(3, 29)
  55 #define TX6Q_LCD_BACKLIGHT_GPIO         IMX_GPIO_NR(1, 1)
  56
  57 #define TX6Q_RESET_OUT_GPIO             IMX_GPIO_NR(7, 12)
  58
  59 #define TEMPERATURE_MIN                 -40
  60 #define TEMPERATURE_HOT                 80
  61 #define TEMPERATURE_MAX                 125
  62
  63 DECLARE_GLOBAL_DATA_PTR;
  64
  65 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  66
  67 static const iomux_v3_cfg_t tx6q_pads[] = {
  68         /* NAND flash pads */
  69         MX6Q_PAD_NANDF_CLE__RAWNAND_CLE,
  70         MX6Q_PAD_NANDF_ALE__RAWNAND_ALE,
  71         MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN,
  72         MX6Q_PAD_NANDF_RB0__RAWNAND_READY0,
  73         MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N,
  74         MX6Q_PAD_SD4_CMD__RAWNAND_RDN,
  75         MX6Q_PAD_SD4_CLK__RAWNAND_WRN,
  76         MX6Q_PAD_NANDF_D0__RAWNAND_D0,
  77         MX6Q_PAD_NANDF_D1__RAWNAND_D1,
  78         MX6Q_PAD_NANDF_D2__RAWNAND_D2,
  79         MX6Q_PAD_NANDF_D3__RAWNAND_D3,
  80         MX6Q_PAD_NANDF_D4__RAWNAND_D4,
  81         MX6Q_PAD_NANDF_D5__RAWNAND_D5,
  82         MX6Q_PAD_NANDF_D6__RAWNAND_D6,
  83         MX6Q_PAD_NANDF_D7__RAWNAND_D7,
  84
  85         /* RESET_OUT */
  86         MX6Q_PAD_GPIO_17__GPIO_7_12,
  87
  88         /* UART pads */
  89 #if CONFIG_MXC_UART_BASE == UART1_BASE
  90         MX6Q_PAD_SD3_DAT7__UART1_TXD,
  91         MX6Q_PAD_SD3_DAT6__UART1_RXD,
  92         MX6Q_PAD_SD3_DAT1__UART1_RTS,
  93         MX6Q_PAD_SD3_DAT0__UART1_CTS,
  94 #endif
  95 #if CONFIG_MXC_UART_BASE == UART2_BASE
  96         MX6Q_PAD_SD4_DAT4__UART2_RXD,
  97         MX6Q_PAD_SD4_DAT7__UART2_TXD,
  98         MX6Q_PAD_SD4_DAT5__UART2_RTS,
  99         MX6Q_PAD_SD4_DAT6__UART2_CTS,
 100 #endif
 101 #if CONFIG_MXC_UART_BASE == UART3_BASE
 102         MX6Q_PAD_EIM_D24__UART3_TXD,
 103         MX6Q_PAD_EIM_D25__UART3_RXD,
 104         MX6Q_PAD_SD3_RST__UART3_RTS,
 105         MX6Q_PAD_SD3_DAT3__UART3_CTS,
 106 #endif
 107         /* internal I2C */
 108         MX6Q_PAD_EIM_D28__I2C1_SDA,
 109         MX6Q_PAD_EIM_D21__I2C1_SCL,
 110
 111         /* FEC PHY GPIO functions */
 112         MX6Q_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */
 113         MX6Q_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */
 114         MX6Q_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */
 115 };
 116
 117 static const iomux_v3_cfg_t tx6q_fec_pads[] = {
 118         /* FEC functions */
 119         MX6Q_PAD_ENET_MDC__ENET_MDC,
 120         MX6Q_PAD_ENET_MDIO__ENET_MDIO,
 121         MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
 122         MX6Q_PAD_ENET_RX_ER__ENET_RX_ER,
 123         MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN,
 124         MX6Q_PAD_ENET_RXD1__ENET_RDATA_1,
 125         MX6Q_PAD_ENET_RXD0__ENET_RDATA_0,
 126         MX6Q_PAD_ENET_TX_EN__ENET_TX_EN,
 127         MX6Q_PAD_ENET_TXD1__ENET_TDATA_1,
 128         MX6Q_PAD_ENET_TXD0__ENET_TDATA_0,
 129 };
 130
 131 static const struct gpio tx6q_gpios[] = {
 132         { TX6Q_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
 133         { TX6Q_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 134         { TX6Q_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 135         { TX6Q_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
 136 };
 137
 138 /*
 139  * Functions
 140  */
 141 /* placed in section '.data' to prevent overwriting relocation info
 142  * overlayed with bss
 143  */
 144 static u32 wrsr __attribute__((section(".data")));
 145
 146 #define WRSR_POR                        (1 << 4)
 147 #define WRSR_TOUT                       (1 << 1)
 148 #define WRSR_SFTW                       (1 << 0)
 149
 150 static void print_reset_cause(void)
 151 {
 152         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 153         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 154         u32 srsr;
 155         char *dlm = "";
 156
 157         printf("Reset cause: ");
 158
 159         srsr = readl(&src_regs->srsr);
 160         wrsr = readw(wdt_base + 4);
 161
 162         if (wrsr & WRSR_POR) {
 163                 printf("%sPOR", dlm);
 164                 dlm = " | ";
 165         }
 166         if (srsr & 0x00004) {
 167                 printf("%sCSU", dlm);
 168                 dlm = " | ";
 169         }
 170         if (srsr & 0x00008) {
 171                 printf("%sIPP USER", dlm);
 172                 dlm = " | ";
 173         }
 174         if (srsr & 0x00010) {
 175                 if (wrsr & WRSR_SFTW) {
 176                         printf("%sSOFT", dlm);
 177                         dlm = " | ";
 178                 }
 179                 if (wrsr & WRSR_TOUT) {
 180                         printf("%sWDOG", dlm);
 181                         dlm = " | ";
 182                 }
 183         }
 184         if (srsr & 0x00020) {
 185                 printf("%sJTAG HIGH-Z", dlm);
 186                 dlm = " | ";
 187         }
 188         if (srsr & 0x00040) {
 189                 printf("%sJTAG SW", dlm);
 190                 dlm = " | ";
 191         }
 192         if (srsr & 0x10000) {
 193                 printf("%sWARM BOOT", dlm);
 194                 dlm = " | ";
 195         }
 196         if (dlm[0] == '\0')
 197                 printf("unknown");
 198
 199         printf("\n");
 200 }
 201
 202 int read_cpu_temperature(void);
 203 int check_cpu_temperature(int boot);
 204
 205 static void print_cpuinfo(void)
 206 {
 207         u32 cpurev = get_cpu_rev();
 208         char *cpu_str = "?";
 209
 210         switch ((cpurev >> 12) & 0xff) {
 211         case MXC_CPU_MX6SL:
 212                 cpu_str = "SL";
 213                 break;
 214         case MXC_CPU_MX6DL:
 215                 cpu_str = "DL";
 216                 break;
 217         case MXC_CPU_MX6SOLO:
 218                 cpu_str = "SOLO";
 219                 break;
 220         case MXC_CPU_MX6Q:
 221                 cpu_str = "Q";
 222                 break;
 223         }
 224
 225         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
 226                 cpu_str,
 227                 (cpurev & 0x000F0) >> 4,
 228                 (cpurev & 0x0000F) >> 0,
 229                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 230
 231         print_reset_cause();
 232         check_cpu_temperature(1);
 233 }
 234
 235 #define LTC3676_DVB2A           0x0C
 236 #define LTC3676_DVB2B           0x0D
 237 #define LTC3676_DVB4A           0x10
 238 #define LTC3676_DVB4B           0x11
 239
 240 #define VDD_SOC_mV              (1375 + 50)
 241 #define VDD_CORE_mV             (1375 + 50)
 242
 243 #define mV_to_regval(mV)        (((mV) * 360 / 330 - 825 + 1) / 25)
 244 #define regval_to_mV(v)         (((v) * 25 + 825) * 330 / 360)
 245
 246 static int setup_pmic_voltages(void)
 247 {
 248         int ret;
 249         unsigned char value;
 250
 251         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 252
 253         ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
 254         if (ret != 0) {
 255                 printf("Failed to initialize I2C\n");
 256                 return ret;
 257         }
 258
 259         ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
 260         if (ret) {
 261                 printf("%s: i2c_read error: %d\n", __func__, ret);
 262                 return ret;
 263         }
 264
 265         /* VDDCORE/VDDSOC default 1.375V is not enough, considering
 266            pfuze tolerance and IR drop and ripple, need increase
 267            to 1.425V for SabreSD */
 268
 269         value = 0x39; /* VB default value & PGOOD not forced when slewing */
 270         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB2B, 1, &value, 1);
 271         if (ret) {
 272                 printf("%s: failed to write PMIC DVB2B register: %d\n",
 273                         __func__, ret);
 274                 return ret;
 275         }
 276         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB4B, 1, &value, 1);
 277         if (ret) {
 278                 printf("%s: failed to write PMIC DVB4B register: %d\n",
 279                         __func__, ret);
 280                 return ret;
 281         }
 282
 283         value = mV_to_regval(VDD_SOC_mV);
 284         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB2A, 1, &value, 1);
 285         if (ret) {
 286                 printf("%s: failed to write PMIC DVB2A register: %d\n",
 287                         __func__, ret);
 288                 return ret;
 289         }
 290         printf("VDDSOC  set to %dmV\n", regval_to_mV(value));
 291
 292         value = mV_to_regval(VDD_CORE_mV);
 293         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB4A, 1, &value, 1);
 294         if (ret) {
 295                 printf("%s: failed to write PMIC DVB4A register: %d\n",
 296                         __func__, ret);
 297                 return ret;
 298         }
 299         printf("VDDCORE set to %dmV\n", regval_to_mV(value));
 300         return 0;
 301 }
 302
 303 int board_early_init_f(void)
 304 {
 305         gpio_request_array(tx6q_gpios, ARRAY_SIZE(tx6q_gpios));
 306         imx_iomux_v3_setup_multiple_pads(tx6q_pads, ARRAY_SIZE(tx6q_pads));
 307
 308         return 0;
 309 }
 310
 311 int board_init(void)
 312 {
 313         int ret;
 314
 315         /* Address of boot parameters */
 316         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 317 #if 1
 318         gd->bd->bi_arch_number = 4429;
 319 #endif
 320         ret = setup_pmic_voltages();
 321         if (ret) {
 322                 printf("Failed to setup PMIC voltages\n");
 323                 hang();
 324         }
 325         return 0;
 326 }
 327
 328 int dram_init(void)
 329 {
 330         /* dram_init must store complete ramsize in gd->ram_size */
 331         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 332                                 PHYS_SDRAM_1_SIZE);
 333         return 0;
 334 }
 335
 336 void dram_init_banksize(void)
 337 {
 338         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 339         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 340                         PHYS_SDRAM_1_SIZE);
 341 #if CONFIG_NR_DRAM_BANKS > 1
 342         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 343         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 344                         PHYS_SDRAM_2_SIZE);
 345 #endif
 346 }
 347
 348 #ifdef  CONFIG_CMD_MMC
 349 static const iomux_v3_cfg_t mmc0_pads[] = {
 350         MX6Q_PAD_SD1_CMD__USDHC1_CMD,
 351         MX6Q_PAD_SD1_CLK__USDHC1_CLK,
 352         MX6Q_PAD_SD1_DAT0__USDHC1_DAT0,
 353         MX6Q_PAD_SD1_DAT1__USDHC1_DAT1,
 354         MX6Q_PAD_SD1_DAT2__USDHC1_DAT2,
 355         MX6Q_PAD_SD1_DAT3__USDHC1_DAT3,
 356         /* SD1 CD */
 357         MX6Q_PAD_SD3_CMD__GPIO_7_2,
 358 };
 359
 360 static const iomux_v3_cfg_t mmc1_pads[] = {
 361         MX6Q_PAD_SD2_CMD__USDHC2_CMD,
 362         MX6Q_PAD_SD2_CLK__USDHC2_CLK,
 363         MX6Q_PAD_SD2_DAT0__USDHC2_DAT0,
 364         MX6Q_PAD_SD2_DAT1__USDHC2_DAT1,
 365         MX6Q_PAD_SD2_DAT2__USDHC2_DAT2,
 366         MX6Q_PAD_SD2_DAT3__USDHC2_DAT3,
 367         /* SD2 CD */
 368         MX6Q_PAD_SD3_CLK__GPIO_7_3,
 369 };
 370
 371 static struct tx6q_esdhc_cfg {
 372         const iomux_v3_cfg_t *pads;
 373         int num_pads;
 374         enum mxc_clock clkid;
 375         struct fsl_esdhc_cfg cfg;
 376 } tx6q_esdhc_cfg[] = {
 377         {
 378                 .pads = mmc0_pads,
 379                 .num_pads = ARRAY_SIZE(mmc0_pads),
 380                 .clkid = MXC_ESDHC_CLK,
 381                 .cfg = {
 382                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
 383                         .cd_gpio = IMX_GPIO_NR(7, 2),
 384                         .wp_gpio = -EINVAL,
 385                 },
 386         },
 387         {
 388                 .pads = mmc1_pads,
 389                 .num_pads = ARRAY_SIZE(mmc1_pads),
 390                 .clkid = MXC_ESDHC2_CLK,
 391                 .cfg = {
 392                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
 393                         .cd_gpio = IMX_GPIO_NR(7, 3),
 394                         .wp_gpio = -EINVAL,
 395                 },
 396         },
 397 };
 398
 399 static inline struct tx6q_esdhc_cfg *to_tx6q_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 400 {
 401         void *p = cfg;
 402
 403         return p - offsetof(struct tx6q_esdhc_cfg, cfg);
 404 }
 405
 406 int board_mmc_getcd(struct mmc *mmc)
 407 {
 408         struct fsl_esdhc_cfg *cfg = mmc->priv;
 409
 410         if (cfg->cd_gpio < 0)
 411                 return cfg->cd_gpio;
 412
 413         debug("SD card %d is %spresent\n",
 414                 to_tx6q_esdhc_cfg(cfg) - tx6q_esdhc_cfg, gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
 415         return !gpio_get_value(cfg->cd_gpio);
 416 }
 417
 418 int board_mmc_init(bd_t *bis)
 419 {
 420         int i;
 421
 422         for (i = 0; i < ARRAY_SIZE(tx6q_esdhc_cfg); i++) {
 423                 struct mmc *mmc;
 424                 struct fsl_esdhc_cfg *cfg = &tx6q_esdhc_cfg[i].cfg;
 425
 426                 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
 427                         break;
 428
 429                 cfg->sdhc_clk = mxc_get_clock(tx6q_esdhc_cfg[i].clkid);
 430                 imx_iomux_v3_setup_multiple_pads(tx6q_esdhc_cfg[i].pads,
 431                                                 tx6q_esdhc_cfg[i].num_pads);
 432
 433                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 434                 fsl_esdhc_initialize(bis, cfg);
 435
 436                 mmc = find_mmc_device(i);
 437                 if (mmc == NULL)
 438                         continue;
 439                 if (board_mmc_getcd(mmc) > 0)
 440                         mmc_init(mmc);
 441         }
 442         return 0;
 443 }
 444 #endif /* CONFIG_CMD_MMC */
 445
 446 #ifdef CONFIG_FEC_MXC
 447
 448 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
 449                         PAD_CTL_SRE_FAST)
 450 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
 451 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 452
 453 #ifndef ETH_ALEN
 454 #define ETH_ALEN 6
 455 #endif
 456
 457 int board_eth_init(bd_t *bis)
 458 {
 459         int ret;
 460
 461         /* delay at least 21ms for the PHY internal POR signal to deassert */
 462         udelay(22000);
 463
 464         imx_iomux_v3_setup_multiple_pads(tx6q_fec_pads, ARRAY_SIZE(tx6q_fec_pads));
 465
 466         /* Deassert RESET to the external phy */
 467         gpio_set_value(TX6Q_FEC_RST_GPIO, 1);
 468
 469         ret = cpu_eth_init(bis);
 470         if (ret)
 471                 printf("cpu_eth_init() failed: %d\n", ret);
 472
 473         return ret;
 474 }
 475 #endif /* CONFIG_FEC_MXC */
 476
 477 enum {
 478         LED_STATE_INIT = -1,
 479         LED_STATE_OFF,
 480         LED_STATE_ON,
 481 };
 482
 483 static inline int calc_blink_rate(int tmp)
 484 {
 485         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
 486                 (tmp - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
 487                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
 488 }
 489
 490 void show_activity(int arg)
 491 {
 492         static int led_state = LED_STATE_INIT;
 493         static int blink_rate;
 494         static ulong last;
 495
 496         if (led_state == LED_STATE_INIT) {
 497                 last = get_timer(0);
 498                 gpio_set_value(TX6Q_LED_GPIO, 1);
 499                 led_state = LED_STATE_ON;
 500                 blink_rate = calc_blink_rate(check_cpu_temperature(0));
 501         } else {
 502                 if (get_timer(last) > blink_rate) {
 503                         blink_rate = calc_blink_rate(check_cpu_temperature(0));
 504                         last = get_timer_masked();
 505                         if (led_state == LED_STATE_ON) {
 506                                 gpio_set_value(TX6Q_LED_GPIO, 0);
 507                         } else {
 508                                 gpio_set_value(TX6Q_LED_GPIO, 1);
 509                         }
 510                         led_state = 1 - led_state;
 511                 }
 512         }
 513 }
 514
 515 static const iomux_v3_cfg_t stk5_pads[] = {
 516         /* SW controlled LED on STK5 baseboard */
 517         MX6Q_PAD_EIM_A18__GPIO_2_20,
 518
 519         /* LCD data pins */
 520         MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
 521         MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
 522         MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
 523         MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
 524         MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
 525         MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
 526         MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
 527         MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
 528         MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
 529         MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
 530         MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
 531         MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
 532         MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
 533         MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
 534         MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
 535         MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
 536         MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
 537         MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
 538         MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
 539         MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
 540         MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
 541         MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
 542         MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
 543         MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
 544         MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */
 545         MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */
 546         MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
 547         MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
 548
 549         /* I2C bus on DIMM pins 40/41 */
 550         MX6Q_PAD_GPIO_6__I2C3_SDA,
 551         MX6Q_PAD_GPIO_3__I2C3_SCL,
 552
 553         /* TSC200x PEN IRQ */
 554         MX6Q_PAD_EIM_D26__GPIO_3_26,
 555
 556         /* EDT-FT5x06 Polytouch panel */
 557         MX6Q_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */
 558         MX6Q_PAD_EIM_A16__GPIO_2_22, /* RESET */
 559         MX6Q_PAD_EIM_A17__GPIO_2_21, /* WAKE */
 560
 561         /* USBH1 */
 562         MX6Q_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */
 563         MX6Q_PAD_EIM_D30__GPIO_3_30, /* OC */
 564         /* USBOTG */
 565         MX6Q_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */
 566         MX6Q_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */
 567         MX6Q_PAD_GPIO_8__GPIO_1_8, /* OC */
 568
 569         /* DEBUG */
 570         MX6Q_PAD_GPIO_0__CCM_CLKO,
 571         MX6Q_PAD_NANDF_CS2__CCM_CLKO2,
 572 };
 573
 574 static const struct gpio stk5_gpios[] = {
 575         { TX6Q_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 576
 577         { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", },
 578         { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
 579         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 580         { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
 581         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 582 };
 583
 584 #ifdef CONFIG_LCD
 585 vidinfo_t panel_info = {
 586         /* set to max. size supported by SoC */
 587         .vl_col = 1920,
 588         .vl_row = 1080,
 589
 590         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 591 };
 592
 593 static struct fb_videomode tx6q_fb_mode = {
 594         /* Standard VGA timing */
 595         .name           = "VGA",
 596         .refresh        = 60,
 597         .xres           = 640,
 598         .yres           = 480,
 599         .pixclock       = KHZ2PICOS(25175),
 600         .left_margin    = 48,
 601         .hsync_len      = 96,
 602         .right_margin   = 16,
 603         .upper_margin   = 31,
 604         .vsync_len      = 2,
 605         .lower_margin   = 12,
 606         .sync           = FB_SYNC_CLK_LAT_FALL,
 607         .vmode          = FB_VMODE_NONINTERLACED,
 608 };
 609
 610 static int lcd_enabled = 1;
 611
 612 void lcd_enable(void)
 613 {
 614         /* HACK ALERT:
 615          * global variable from common/lcd.c
 616          * Set to 0 here to prevent messages from going to LCD
 617          * rather than serial console
 618          */
 619         lcd_is_enabled = 0;
 620
 621         karo_load_splashimage(1);
 622         if (lcd_enabled) {
 623                 debug("Switching LCD on\n");
 624                 gpio_set_value(TX6Q_LCD_PWR_GPIO, 1);
 625                 udelay(100);
 626                 gpio_set_value(TX6Q_LCD_RST_GPIO, 1);
 627                 udelay(300000);
 628                 gpio_set_value(TX6Q_LCD_BACKLIGHT_GPIO, 0);
 629         }
 630 }
 631
 632 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 633         /* LCD RESET */
 634         MX6Q_PAD_EIM_D29__GPIO_3_29,
 635         /* LCD POWER_ENABLE */
 636         MX6Q_PAD_EIM_EB3__GPIO_2_31,
 637         /* LCD Backlight (PWM) */
 638         MX6Q_PAD_GPIO_1__GPIO_1_1,
 639
 640         /* Display */
 641         MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
 642         MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15,
 643         MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2,
 644         MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3,
 645         MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
 646         MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
 647         MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
 648         MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
 649         MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
 650         MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
 651         MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
 652         MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
 653         MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
 654         MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
 655         MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
 656         MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
 657         MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
 658         MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
 659         MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
 660         MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
 661         MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
 662         MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
 663         MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
 664         MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
 665         MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
 666         MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
 667         MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
 668         MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
 669
 670         /* LVDS option */
 671         MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
 672         MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
 673         MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
 674         MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
 675         MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
 676         MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
 677         MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
 678         MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
 679         MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
 680         MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
 681 };
 682
 683 static const struct gpio stk5_lcd_gpios[] = {
 684         { TX6Q_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
 685         { TX6Q_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
 686         { TX6Q_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 687 };
 688
 689 void lcd_ctrl_init(void *lcdbase)
 690 {
 691         int color_depth = 24;
 692         char *vm;
 693         unsigned long val;
 694         int refresh = 60;
 695         struct fb_videomode *p = &tx6q_fb_mode;
 696         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 697         int pix_fmt = 0;
 698         ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
 699         unsigned long di_clk_rate = 65000000;
 700
 701         if (!lcd_enabled) {
 702                 debug("LCD disabled\n");
 703                 return;
 704         }
 705
 706         if (tstc() || (wrsr & WRSR_TOUT)) {
 707                 debug("Disabling LCD\n");
 708                 lcd_enabled = 0;
 709                 return;
 710         }
 711
 712         vm = getenv("video_mode");
 713         if (vm == NULL) {
 714                 debug("Disabling LCD\n");
 715                 lcd_enabled = 0;
 716                 return;
 717         }
 718         while (*vm != '\0') {
 719                 if (*vm >= '0' && *vm <= '9') {
 720                         char *end;
 721
 722                         val = simple_strtoul(vm, &end, 0);
 723                         if (end > vm) {
 724                                 if (!xres_set) {
 725                                         if (val > panel_info.vl_col)
 726                                                 val = panel_info.vl_col;
 727                                         p->xres = val;
 728                                         panel_info.vl_col = val;
 729                                         xres_set = 1;
 730                                 } else if (!yres_set) {
 731                                         if (val > panel_info.vl_row)
 732                                                 val = panel_info.vl_row;
 733                                         p->yres = val;
 734                                         panel_info.vl_row = val;
 735                                         yres_set = 1;
 736                                 } else if (!bpp_set) {
 737                                         switch (val) {
 738                                         case 24:
 739                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666)
 740                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
 741                                                 /* fallthru */
 742                                         case 16:
 743                                         case 8:
 744                                                 color_depth = val;
 745                                                 break;
 746
 747                                         case 18:
 748                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666) {
 749                                                         color_depth = val;
 750                                                         break;
 751                                                 }
 752                                                 /* fallthru */
 753                                         default:
 754                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
 755                                                         end - vm, vm, color_depth);
 756                                         }
 757                                         bpp_set = 1;
 758                                 } else if (!refresh_set) {
 759                                         refresh = val;
 760                                         refresh_set = 1;
 761                                 }
 762                         }
 763                         vm = end;
 764                 }
 765                 switch (*vm) {
 766                 case '@':
 767                         bpp_set = 1;
 768                         /* fallthru */
 769                 case '-':
 770                         yres_set = 1;
 771                         /* fallthru */
 772                 case 'x':
 773                         xres_set = 1;
 774                         /* fallthru */
 775                 case 'M':
 776                 case 'R':
 777                         vm++;
 778                         break;
 779
 780                 default:
 781                         if (!pix_fmt) {
 782                                 char *tmp;
 783
 784                                 if (strncmp(vm, "LVDS", 4) == 0) {
 785                                         pix_fmt = IPU_PIX_FMT_LVDS666;
 786                                         di_clk_parent = DI_PCLK_LDB;
 787                                 } else {
 788                                         pix_fmt = IPU_PIX_FMT_RGB24;
 789                                 }
 790                                 tmp = strchr(vm, ':');
 791                                 if (tmp)
 792                                         vm = tmp;
 793                         }
 794                         if (*vm != '\0')
 795                                 vm++;
 796                 }
 797         }
 798         switch (color_depth) {
 799         case 8:
 800                 panel_info.vl_bpix = 3;
 801                 break;
 802
 803         case 16:
 804                 panel_info.vl_bpix = 4;
 805                 break;
 806
 807         case 18:
 808         case 24:
 809                 panel_info.vl_bpix = 5;
 810         }
 811
 812         p->pixclock = KHZ2PICOS(refresh *
 813                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
 814                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
 815                 / 1000);
 816         debug("Pixel clock set to %lu.%03lu MHz\n",
 817                 PICOS2KHZ(p->pixclock) / 1000,
 818                 PICOS2KHZ(p->pixclock) % 1000);
 819
 820         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
 821         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
 822                                         ARRAY_SIZE(stk5_lcd_pads));
 823
 824         debug("Initializing FB driver\n");
 825         if (!pix_fmt)
 826                 pix_fmt = IPU_PIX_FMT_RGB24;
 827         else if (pix_fmt == IPU_PIX_FMT_LVDS666) {
 828                 writel(0x01, IOMUXC_BASE_ADDR + 8);
 829         } else if (pix_fmt == IPU_PIX_FMT_LVDS888) {
 830                 writel(0x21, IOMUXC_BASE_ADDR + 8);
 831         }
 832         if (pix_fmt != IPU_PIX_FMT_RGB24) {
 833                 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 834                 /* enable LDB & DI0 clock */
 835                 writel(readl(&ccm_regs->CCGR3) | (3 << 12) | (3 << 2),
 836                         &ccm_regs->CCGR3);
 837         }
 838
 839         if (karo_load_splashimage(0) == 0) {
 840                 debug("Initializing LCD controller\n");
 841                 ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
 842         } else {
 843                 debug("Skipping initialization of LCD controller\n");
 844         }
 845 }
 846 #else
 847 #define lcd_enabled 0
 848 #endif /* CONFIG_LCD */
 849
 850 static void stk5_board_init(void)
 851 {
 852         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
 853         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
 854 }
 855
 856 static void stk5v3_board_init(void)
 857 {
 858         stk5_board_init();
 859 }
 860
 861 static void stk5v5_board_init(void)
 862 {
 863         stk5_board_init();
 864
 865         gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
 866                         "Flexcan Transceiver");
 867         imx_iomux_v3_setup_pad(MX6Q_PAD_DISP0_DAT0__GPIO_4_21);
 868 }
 869
 870 static void tx6q_set_cpu_clock(void)
 871 {
 872         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
 873
 874         if (tstc() || (wrsr & WRSR_TOUT))
 875                 return;
 876
 877         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
 878                 return;
 879
 880         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
 881                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
 882                 printf("CPU clock set to %lu.%03lu MHz\n",
 883                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
 884         } else {
 885                 printf("Failed to set CPU clock to %lu MHz\n", cpu_clk);
 886         }
 887 }
 888
 889 static void tx6_init_mac(void)
 890 {
 891         u8 mac[ETH_ALEN];
 892         char mac_str[ETH_ALEN * 3] = "";
 893
 894         imx_get_mac_from_fuse(-1, mac);
 895         if (!is_valid_ether_addr(mac)) {
 896                 printf("No valid MAC address programmed\n");
 897                 return;
 898         }
 899
 900         snprintf(mac_str, sizeof(mac_str), "%02x:%02x:%02x:%02x:%02x:%02x",
 901                 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 902         setenv("ethaddr", mac_str);
 903         printf("MAC addr from fuse: %02x:%02x:%02x:%02x:%02x:%02x\n",
 904                 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 905 }
 906
 907 int board_late_init(void)
 908 {
 909         int ret = 0;
 910         const char *baseboard;
 911
 912         tx6q_set_cpu_clock();
 913         karo_fdt_move_fdt();
 914
 915         baseboard = getenv("baseboard");
 916         if (!baseboard)
 917                 goto exit;
 918
 919         printf("Baseboard: %s\n", baseboard);
 920
 921         if (strncmp(baseboard, "stk5", 4) == 0) {
 922                 if ((strlen(baseboard) == 4) ||
 923                         strcmp(baseboard, "stk5-v3") == 0) {
 924                         stk5v3_board_init();
 925                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
 926                         stk5v5_board_init();
 927                 } else {
 928                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
 929                                 baseboard + 4);
 930                 }
 931         } else {
 932                 printf("WARNING: Unsupported baseboard: '%s'\n",
 933                         baseboard);
 934                 ret = -EINVAL;
 935         }
 936
 937 exit:
 938         tx6_init_mac();
 939
 940         gpio_set_value(TX6Q_RESET_OUT_GPIO, 1);
 941         return ret;
 942 }
 943
 944 #define iomux_field(v,f)        (((iomux_v3_cfg_t)(v) << f##_SHIFT) & f##_MASK)
 945
 946 #define chk_iomux_field(f1,f2)  ({                                      \
 947         iomux_v3_cfg_t __c = iomux_field(~0, f1);                       \
 948         if (__c & f2##_MASK) {                                          \
 949                 printf("%18s[%016llx] overlaps with:\n%18s[%016llx]\n", \
 950                         #f1, f1##_MASK,                                 \
 951                         #f2, f2##_MASK);                                \
 952         }                                                               \
 953         (__c & f2##_MASK) != 0;                                         \
 954 })
 955
 956 #define chk_iomux_bit(f1,f2)    ({                                      \
 957         iomux_v3_cfg_t __c = iomux_field(~0, f1);                       \
 958         if (__c & f2) {                                                 \
 959                 printf("%18s[%016llx] overlaps with:\n%18s[%016llx]\n", \
 960                         #f1, f1##_MASK,                                 \
 961                         #f2, (iomux_v3_cfg_t)f2);                       \
 962         }                                                               \
 963         (__c & f2) != 0;                                                \
 964 })
 965
 966 int checkboard(void)
 967 {
 968         print_cpuinfo();
 969
 970         printf("Board: Ka-Ro TX6Q\n");
 971
 972 #ifdef TIMER_TEST
 973         {
 974                 struct mxc_gpt {
 975                         unsigned int control;
 976                         unsigned int prescaler;
 977                         unsigned int status;
 978                         unsigned int nouse[6];
 979                         unsigned int counter;
 980                 };
 981                 const int us_delay = 10;
 982                 unsigned long start = get_timer(0);
 983                 unsigned long last = gd->arch.tbl;
 984                 unsigned long loop = 0;
 985                 unsigned long cnt = 0;
 986                 static struct mxc_gpt *timer_base = (struct mxc_gpt *)GPT1_BASE_ADDR;
 987
 988                 printf("GPT prescaler=%u\n", readl(&timer_base->prescaler) + 1);
 989                 printf("clock tick rate: %lu.%03lukHz\n",
 990                         gd->arch.timer_rate_hz / 1000, gd->arch.timer_rate_hz % 1000);
 991                 printf("ticks/us=%lu\n", gd->arch.timer_rate_hz / CONFIG_SYS_HZ / 1000);
 992
 993                 while (!tstc()) {
 994                         unsigned long elapsed = get_timer(start);
 995                         unsigned long diff = gd->arch.tbl - last;
 996
 997                         loop++;
 998                         last = gd->arch.tbl;
 999
1000                         printf("loop %4lu: t=%08lx diff=%08lx steps=%6lu elapsed time: %4lu",
1001                                 loop, gd->arch.tbl, diff, cnt, elapsed / CONFIG_SYS_HZ);
1002                         cnt = 0;
1003                         while (get_timer(elapsed + start) < CONFIG_SYS_HZ) {
1004                                 cnt++;
1005                                 udelay(us_delay);
1006                         }
1007                         printf(" counter=%08x udelay(%u)=%lu.%03luus\n",
1008                                 readl(&timer_base->counter), us_delay,
1009                                 1000000000 / cnt / 1000, 1000000000 / cnt % 1000);
1010                 }
1011         }
1012 #endif
1013         return 0;
1014 }
1015
1016 #ifdef CONFIG_SERIAL_TAG
1017 void get_board_serial(struct tag_serialnr *serialnr)
1018 {
1019         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
1020         struct fuse_bank0_regs *fuse = (void *)iim->bank[0].fuse_regs;
1021
1022         serialnr->low = readl(&fuse->cfg0);
1023         serialnr->high = readl(&fuse->cfg1);
1024 }
1025 #endif
1026
1027 #if defined(CONFIG_OF_BOARD_SETUP)
1028 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1029 #include <jffs2/jffs2.h>
1030 #include <mtd_node.h>
1031 struct node_info nodes[] = {
1032         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1033 };
1034
1035 #else
1036 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1037 #endif
1038
1039 static void tx6q_fixup_flexcan(void *blob)
1040 {
1041         const char *baseboard = getenv("baseboard");
1042
1043         if (baseboard && strcmp(baseboard, "stk5-v5") == 0)
1044                 return;
1045
1046         karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x02090000, "transceiver-switch");
1047         karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x02094000, "transceiver-switch");
1048 }
1049
1050 void ft_board_setup(void *blob, bd_t *bd)
1051 {
1052         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1053         fdt_fixup_ethernet(blob);
1054
1055         karo_fdt_fixup_touchpanel(blob);
1056         karo_fdt_fixup_usb_otg(blob, "", 0);
1057         tx6q_fixup_flexcan(blob);
1058 }
1059 #endif