2 * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <fdt_support.h>
32 #include <fsl_esdhc.h>
40 #include <asm/arch/iomux-mx6.h>
41 #include <asm/arch/clock.h>
42 #include <asm/arch/imx-regs.h>
43 #include <asm/arch/crm_regs.h>
44 #include <asm/arch/sys_proto.h>
46 #include "../common/karo.h"
48 #define TX6Q_FEC_RST_GPIO IMX_GPIO_NR(7, 6)
49 #define TX6Q_FEC_PWR_GPIO IMX_GPIO_NR(3, 20)
50 #define TX6Q_FEC_INT_GPIO IMX_GPIO_NR(2, 4)
51 #define TX6Q_LED_GPIO IMX_GPIO_NR(2, 20)
53 #define TX6Q_LCD_PWR_GPIO IMX_GPIO_NR(2, 31)
54 #define TX6Q_LCD_RST_GPIO IMX_GPIO_NR(3, 29)
55 #define TX6Q_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
57 #define TX6Q_RESET_OUT_GPIO IMX_GPIO_NR(7, 12)
59 #define TEMPERATURE_MIN -40
60 #define TEMPERATURE_HOT 80
61 #define TEMPERATURE_MAX 125
63 DECLARE_GLOBAL_DATA_PTR;
65 #define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
67 static const iomux_v3_cfg_t tx6q_pads[] = {
69 MX6Q_PAD_NANDF_CLE__RAWNAND_CLE,
70 MX6Q_PAD_NANDF_ALE__RAWNAND_ALE,
71 MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN,
72 MX6Q_PAD_NANDF_RB0__RAWNAND_READY0,
73 MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N,
74 MX6Q_PAD_SD4_CMD__RAWNAND_RDN,
75 MX6Q_PAD_SD4_CLK__RAWNAND_WRN,
76 MX6Q_PAD_NANDF_D0__RAWNAND_D0,
77 MX6Q_PAD_NANDF_D1__RAWNAND_D1,
78 MX6Q_PAD_NANDF_D2__RAWNAND_D2,
79 MX6Q_PAD_NANDF_D3__RAWNAND_D3,
80 MX6Q_PAD_NANDF_D4__RAWNAND_D4,
81 MX6Q_PAD_NANDF_D5__RAWNAND_D5,
82 MX6Q_PAD_NANDF_D6__RAWNAND_D6,
83 MX6Q_PAD_NANDF_D7__RAWNAND_D7,
86 MX6Q_PAD_GPIO_17__GPIO_7_12,
89 #if CONFIG_MXC_UART_BASE == UART1_BASE
90 MX6Q_PAD_SD3_DAT7__UART1_TXD,
91 MX6Q_PAD_SD3_DAT6__UART1_RXD,
92 MX6Q_PAD_SD3_DAT1__UART1_RTS,
93 MX6Q_PAD_SD3_DAT0__UART1_CTS,
95 #if CONFIG_MXC_UART_BASE == UART2_BASE
96 MX6Q_PAD_SD4_DAT4__UART2_RXD,
97 MX6Q_PAD_SD4_DAT7__UART2_TXD,
98 MX6Q_PAD_SD4_DAT5__UART2_RTS,
99 MX6Q_PAD_SD4_DAT6__UART2_CTS,
101 #if CONFIG_MXC_UART_BASE == UART3_BASE
102 MX6Q_PAD_EIM_D24__UART3_TXD,
103 MX6Q_PAD_EIM_D25__UART3_RXD,
104 MX6Q_PAD_SD3_RST__UART3_RTS,
105 MX6Q_PAD_SD3_DAT3__UART3_CTS,
108 MX6Q_PAD_EIM_D28__I2C1_SDA,
109 MX6Q_PAD_EIM_D21__I2C1_SCL,
111 /* FEC PHY GPIO functions */
112 MX6Q_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */
113 MX6Q_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */
114 MX6Q_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */
117 static const iomux_v3_cfg_t tx6q_fec_pads[] = {
119 MX6Q_PAD_ENET_MDC__ENET_MDC,
120 MX6Q_PAD_ENET_MDIO__ENET_MDIO,
121 MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
122 MX6Q_PAD_ENET_RX_ER__ENET_RX_ER,
123 MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN,
124 MX6Q_PAD_ENET_RXD1__ENET_RDATA_1,
125 MX6Q_PAD_ENET_RXD0__ENET_RDATA_0,
126 MX6Q_PAD_ENET_TX_EN__ENET_TX_EN,
127 MX6Q_PAD_ENET_TXD1__ENET_TDATA_1,
128 MX6Q_PAD_ENET_TXD0__ENET_TDATA_0,
131 static const struct gpio tx6q_gpios[] = {
132 { TX6Q_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
133 { TX6Q_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
134 { TX6Q_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
135 { TX6Q_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
141 /* placed in section '.data' to prevent overwriting relocation info
144 static u32 wrsr __attribute__((section(".data")));
146 #define WRSR_POR (1 << 4)
147 #define WRSR_TOUT (1 << 1)
148 #define WRSR_SFTW (1 << 0)
150 static void print_reset_cause(void)
152 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
153 void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
157 printf("Reset cause: ");
159 srsr = readl(&src_regs->srsr);
160 wrsr = readw(wdt_base + 4);
162 if (wrsr & WRSR_POR) {
163 printf("%sPOR", dlm);
166 if (srsr & 0x00004) {
167 printf("%sCSU", dlm);
170 if (srsr & 0x00008) {
171 printf("%sIPP USER", dlm);
174 if (srsr & 0x00010) {
175 if (wrsr & WRSR_SFTW) {
176 printf("%sSOFT", dlm);
179 if (wrsr & WRSR_TOUT) {
180 printf("%sWDOG", dlm);
184 if (srsr & 0x00020) {
185 printf("%sJTAG HIGH-Z", dlm);
188 if (srsr & 0x00040) {
189 printf("%sJTAG SW", dlm);
192 if (srsr & 0x10000) {
193 printf("%sWARM BOOT", dlm);
202 int read_cpu_temperature(void);
203 int check_cpu_temperature(int boot);
205 static void print_cpuinfo(void)
209 cpurev = get_cpu_rev();
211 printf("CPU: Freescale i.MX6Q rev%d.%d at %d MHz\n",
212 (cpurev & 0x000F0) >> 4,
213 (cpurev & 0x0000F) >> 0,
214 mxc_get_clock(MXC_ARM_CLK) / 1000000);
217 check_cpu_temperature(1);
220 #define LTC3676_DVB2A 0x0C
221 #define LTC3676_DVB2B 0x0D
222 #define LTC3676_DVB4A 0x10
223 #define LTC3676_DVB4B 0x11
225 #define VDD_SOC_mV (1375 + 50)
226 #define VDD_CORE_mV (1375 + 50)
228 #define mV_to_regval(mV) (((mV) * 360 / 330 - 825 + 1) / 25)
229 #define regval_to_mV(v) (((v) * 25 + 825) * 330 / 360)
231 static int setup_pmic_voltages(void)
236 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
238 ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
240 printf("Failed to initialize I2C\n");
244 ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
246 printf("%s: i2c_read error: %d\n", __func__, ret);
250 /* VDDCORE/VDDSOC default 1.375V is not enough, considering
251 pfuze tolerance and IR drop and ripple, need increase
252 to 1.425V for SabreSD */
254 value = 0x39; /* VB default value & PGOOD not forced when slewing */
255 ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB2B, 1, &value, 1);
257 printf("%s: failed to write PMIC DVB2B register: %d\n",
261 ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB4B, 1, &value, 1);
263 printf("%s: failed to write PMIC DVB4B register: %d\n",
268 value = mV_to_regval(VDD_SOC_mV);
269 ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB2A, 1, &value, 1);
271 printf("%s: failed to write PMIC DVB2A register: %d\n",
275 printf("VDDSOC set to %dmV\n", regval_to_mV(value));
277 value = mV_to_regval(VDD_CORE_mV);
278 ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB4A, 1, &value, 1);
280 printf("%s: failed to write PMIC DVB4A register: %d\n",
284 printf("VDDCORE set to %dmV\n", regval_to_mV(value));
288 int board_early_init_f(void)
291 writel(0xffffffff, 0x020c4068); /* CCGR0 */
292 writel(0xffffffff, 0x020c406c); /* CCGR1 */
293 writel(0xffffffff, 0x020c4070); /* CCGR2 */
294 writel(0xffffffff, 0x020c4074); /* CCGR3 */
295 writel(0xffffffff, 0x020c4078); /* CCGR4 */
296 writel(0xffffffff, 0x020c407c); /* CCGR5 */
297 writel(0xffffffff, 0x020c4080); /* CCGR6 */
298 writel(0xffffffff, 0x020c4084); /* CCGR7 */
301 writel(0x00000000, 0x020e02d4); /* NANDF_CLE: NANDF_CLE */
302 writel(0x00000000, 0x020e02d8); /* NANDF_ALE: NANDF_ALE */
303 writel(0x00000000, 0x020e02dc); /* NANDF_WP_B: NANDF_WPn */
304 writel(0x00000000, 0x020e02e0); /* NANDF_RB0: NANDF_READY0 */
305 writel(0x00000000, 0x020e02e4); /* NANDF_CS0: NANDF_CS0 */
306 writel(0x00000001, 0x020e02f4); /* SD4_CMD: NANDF_RDn */
307 writel(0x00000001, 0x020e02f8); /* SD4_CLK: NANDF_WRn */
309 writel(0x00000000, 0x020e02fc); /* NANDF_D0: NANDF_D0 */
310 writel(0x00000000, 0x020e0300); /* NANDF_D1: NANDF_D1 */
311 writel(0x00000000, 0x020e0304); /* NANDF_D2: NANDF_D2 */
312 writel(0x00000000, 0x020e0308); /* NANDF_D3: NANDF_D3 */
313 writel(0x00000000, 0x020e030c); /* NANDF_D4: NANDF_D4 */
314 writel(0x00000000, 0x020e0310); /* NANDF_D5: NANDF_D5 */
315 writel(0x00000000, 0x020e0314); /* NANDF_D6: NANDF_D6 */
316 writel(0x00000000, 0x020e0318); /* NANDF_D7: NANDF_D7 */
318 gpio_request_array(tx6q_gpios, ARRAY_SIZE(tx6q_gpios));
319 imx_iomux_v3_setup_multiple_pads(tx6q_pads, ARRAY_SIZE(tx6q_pads));
323 ret = setup_pmic_voltages();
325 printf("Failed to setup PMIC voltages\n");
336 /* Address of boot parameters */
337 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
339 gd->bd->bi_arch_number = 4429;
341 ret = setup_pmic_voltages();
343 printf("Failed to setup PMIC voltages\n");
351 /* dram_init must store complete ramsize in gd->ram_size */
352 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
357 void dram_init_banksize(void)
359 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
360 gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
362 #if CONFIG_NR_DRAM_BANKS > 1
363 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
364 gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
369 #ifdef CONFIG_CMD_MMC
370 static const iomux_v3_cfg_t mmc0_pads[] = {
371 MX6Q_PAD_SD1_CMD__USDHC1_CMD,
372 MX6Q_PAD_SD1_CLK__USDHC1_CLK,
373 MX6Q_PAD_SD1_DAT0__USDHC1_DAT0,
374 MX6Q_PAD_SD1_DAT1__USDHC1_DAT1,
375 MX6Q_PAD_SD1_DAT2__USDHC1_DAT2,
376 MX6Q_PAD_SD1_DAT3__USDHC1_DAT3,
378 MX6Q_PAD_SD3_CMD__GPIO_7_2,
381 static const iomux_v3_cfg_t mmc1_pads[] = {
382 MX6Q_PAD_SD2_CMD__USDHC2_CMD,
383 MX6Q_PAD_SD2_CLK__USDHC2_CLK,
384 MX6Q_PAD_SD2_DAT0__USDHC2_DAT0,
385 MX6Q_PAD_SD2_DAT1__USDHC2_DAT1,
386 MX6Q_PAD_SD2_DAT2__USDHC2_DAT2,
387 MX6Q_PAD_SD2_DAT3__USDHC2_DAT3,
389 MX6Q_PAD_SD3_CLK__GPIO_7_3,
392 static struct tx6q_esdhc_cfg {
393 const iomux_v3_cfg_t *pads;
395 enum mxc_clock clkid;
396 struct fsl_esdhc_cfg cfg;
397 } tx6q_esdhc_cfg[] = {
400 .num_pads = ARRAY_SIZE(mmc0_pads),
401 .clkid = MXC_ESDHC_CLK,
403 .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
404 .cd_gpio = IMX_GPIO_NR(7, 2),
410 .num_pads = ARRAY_SIZE(mmc1_pads),
411 .clkid = MXC_ESDHC2_CLK,
413 .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
414 .cd_gpio = IMX_GPIO_NR(7, 3),
420 static inline struct tx6q_esdhc_cfg *to_tx6q_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
424 return p - offsetof(struct tx6q_esdhc_cfg, cfg);
427 int board_mmc_getcd(struct mmc *mmc)
429 struct fsl_esdhc_cfg *cfg = mmc->priv;
431 if (cfg->cd_gpio < 0)
434 debug("SD card %d is %spresent\n",
435 to_tx6q_esdhc_cfg(cfg) - tx6q_esdhc_cfg, gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
436 return !gpio_get_value(cfg->cd_gpio);
439 int board_mmc_init(bd_t *bis)
443 for (i = 0; i < ARRAY_SIZE(tx6q_esdhc_cfg); i++) {
445 struct fsl_esdhc_cfg *cfg = &tx6q_esdhc_cfg[i].cfg;
447 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
450 cfg->sdhc_clk = mxc_get_clock(tx6q_esdhc_cfg[i].clkid);
451 imx_iomux_v3_setup_multiple_pads(tx6q_esdhc_cfg[i].pads,
452 tx6q_esdhc_cfg[i].num_pads);
454 debug("%s: Initializing MMC slot %d\n", __func__, i);
455 fsl_esdhc_initialize(bis, cfg);
457 mmc = find_mmc_device(i);
460 if (board_mmc_getcd(mmc) > 0)
465 #endif /* CONFIG_CMD_MMC */
467 #ifdef CONFIG_FEC_MXC
469 #define FEC_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
471 #define FEC_PAD_CTL2 (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
472 #define GPIO_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
478 int board_eth_init(bd_t *bis)
482 unsigned char mac[ETH_ALEN];
483 char mac_str[ETH_ALEN * 3] = "";
485 /* delay at least 21ms for the PHY internal POR signal to deassert */
488 imx_iomux_v3_setup_multiple_pads(tx6q_fec_pads, ARRAY_SIZE(tx6q_fec_pads));
490 printf("RXD0(MODE0)=%d\n", gpio_get_value(IMX_GPIO_NR(1, 27)));
491 printf("RXD1(MODE1)=%d\n", gpio_get_value(IMX_GPIO_NR(1, 26)));
492 printf("CRS_DV(MODE2)=%d\n", gpio_get_value(IMX_GPIO_NR(1, 25)));
494 printf("RX_ER(PHYAD0)=%d\n", gpio_get_value(IMX_GPIO_NR(1, 24)));
496 printf("GPIO7[6](FEC RESET)=%d\n", gpio_get_value(IMX_GPIO_NR(7, 6)));
497 printf("GPIO3[20](FEC PWR)=%d\n", gpio_get_value(IMX_GPIO_NR(3, 20)));
500 /* Deassert RESET to the external phy */
501 gpio_set_value(TX6Q_FEC_RST_GPIO, 1);
503 ret = cpu_eth_init(bis);
505 printf("cpu_eth_init() failed: %d\n", ret);
509 imx_get_mac_from_fuse(-1, mac);
510 snprintf(mac_str, sizeof(mac_str), "%02x:%02x:%02x:%02x:%02x:%02x",
511 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
512 setenv("ethaddr", mac_str);
516 #endif /* CONFIG_FEC_MXC */
524 static inline int calc_blink_rate(int tmp)
526 return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
527 (tmp - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
528 (TEMPERATURE_HOT - TEMPERATURE_MIN);
531 void show_activity(int arg)
533 static int led_state = LED_STATE_INIT;
534 static int blink_rate;
537 if (led_state == LED_STATE_INIT) {
539 gpio_set_value(TX6Q_LED_GPIO, 1);
540 led_state = LED_STATE_ON;
541 blink_rate = calc_blink_rate(check_cpu_temperature(0));
543 if (get_timer(last) > blink_rate) {
544 blink_rate = calc_blink_rate(check_cpu_temperature(0));
545 last = get_timer_masked();
546 if (led_state == LED_STATE_ON) {
547 gpio_set_value(TX6Q_LED_GPIO, 0);
549 gpio_set_value(TX6Q_LED_GPIO, 1);
551 led_state = 1 - led_state;
556 static const iomux_v3_cfg_t stk5_pads[] = {
557 /* SW controlled LED on STK5 baseboard */
558 MX6Q_PAD_EIM_A18__GPIO_2_20,
561 MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
562 MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
563 MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
564 MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
565 MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
566 MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
567 MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
568 MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
569 MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
570 MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
571 MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
572 MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
573 MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
574 MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
575 MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
576 MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
577 MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
578 MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
579 MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
580 MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
581 MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
582 MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
583 MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
584 MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
585 MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */
586 MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */
587 MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
588 MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
590 /* I2C bus on DIMM pins 40/41 */
591 MX6Q_PAD_GPIO_6__I2C3_SDA,
592 MX6Q_PAD_GPIO_3__I2C3_SCL,
594 /* TSC200x PEN IRQ */
595 MX6Q_PAD_EIM_D26__GPIO_3_26,
597 /* EDT-FT5x06 Polytouch panel */
598 MX6Q_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */
599 MX6Q_PAD_EIM_A16__GPIO_2_22, /* RESET */
600 MX6Q_PAD_EIM_A17__GPIO_2_21, /* WAKE */
603 MX6Q_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */
604 MX6Q_PAD_EIM_D30__GPIO_3_30, /* OC */
606 MX6Q_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */
607 MX6Q_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */
608 MX6Q_PAD_GPIO_8__GPIO_1_8, /* OC */
611 MX6Q_PAD_GPIO_0__CCM_CLKO,
612 MX6Q_PAD_NANDF_CS2__CCM_CLKO2,
615 static const struct gpio stk5_gpios[] = {
616 { TX6Q_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
618 { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", },
619 { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
620 { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
621 { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
622 { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
626 vidinfo_t panel_info = {
627 /* set to max. size supported by SoC */
631 .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
634 static struct fb_videomode tx6q_fb_mode = {
635 /* Standard VGA timing */
640 .pixclock = KHZ2PICOS(25175),
647 .sync = FB_SYNC_CLK_LAT_FALL,
648 .vmode = FB_VMODE_NONINTERLACED,
651 static int lcd_enabled = 1;
653 void lcd_enable(void)
656 * global variable from common/lcd.c
657 * Set to 0 here to prevent messages from going to LCD
658 * rather than serial console
662 karo_load_splashimage(1);
664 debug("Switching LCD on\n");
665 gpio_set_value(TX6Q_LCD_PWR_GPIO, 1);
667 gpio_set_value(TX6Q_LCD_RST_GPIO, 1);
669 gpio_set_value(TX6Q_LCD_BACKLIGHT_GPIO, 0);
673 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
675 MX6Q_PAD_EIM_D29__GPIO_3_29,
676 /* LCD POWER_ENABLE */
677 MX6Q_PAD_EIM_EB3__GPIO_2_31,
678 /* LCD Backlight (PWM) */
679 MX6Q_PAD_GPIO_1__GPIO_1_1,
682 MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
683 MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15,
684 MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2,
685 MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3,
686 MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
687 MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
688 MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
689 MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
690 MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
691 MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
692 MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
693 MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
694 MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
695 MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
696 MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
697 MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
698 MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
699 MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
700 MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
701 MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
702 MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
703 MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
704 MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
705 MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
706 MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
707 MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
708 MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
709 MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
712 MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
713 MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
714 MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
715 MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
716 MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
717 MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
718 MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
719 MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
720 MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
721 MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
724 static const struct gpio stk5_lcd_gpios[] = {
725 { TX6Q_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
726 { TX6Q_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
727 { TX6Q_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
730 void lcd_ctrl_init(void *lcdbase)
732 int color_depth = 24;
736 struct fb_videomode *p = &tx6q_fb_mode;
737 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
739 ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
740 unsigned long di_clk_rate = 65000000;
743 debug("LCD disabled\n");
747 if (tstc() || (wrsr & WRSR_TOUT)) {
748 debug("Disabling LCD\n");
753 vm = getenv("video_mode");
755 debug("Disabling LCD\n");
759 while (*vm != '\0') {
760 if (*vm >= '0' && *vm <= '9') {
763 val = simple_strtoul(vm, &end, 0);
766 if (val > panel_info.vl_col)
767 val = panel_info.vl_col;
769 panel_info.vl_col = val;
771 } else if (!yres_set) {
772 if (val > panel_info.vl_row)
773 val = panel_info.vl_row;
775 panel_info.vl_row = val;
777 } else if (!bpp_set) {
780 if (pix_fmt == IPU_PIX_FMT_LVDS666)
781 pix_fmt = IPU_PIX_FMT_LVDS888;
789 if (pix_fmt == IPU_PIX_FMT_LVDS666) {
795 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
796 end - vm, vm, color_depth);
799 } else if (!refresh_set) {
825 if (strncmp(vm, "LVDS", 4) == 0) {
826 pix_fmt = IPU_PIX_FMT_LVDS666;
827 di_clk_parent = DI_PCLK_LDB;
829 pix_fmt = IPU_PIX_FMT_RGB24;
831 tmp = strchr(vm, ':');
839 switch (color_depth) {
841 panel_info.vl_bpix = 3;
845 panel_info.vl_bpix = 4;
850 panel_info.vl_bpix = 5;
853 p->pixclock = KHZ2PICOS(refresh *
854 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
855 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
857 debug("Pixel clock set to %lu.%03lu MHz\n",
858 PICOS2KHZ(p->pixclock) / 1000,
859 PICOS2KHZ(p->pixclock) % 1000);
861 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
862 imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
863 ARRAY_SIZE(stk5_lcd_pads));
865 debug("Initializing FB driver\n");
867 pix_fmt = IPU_PIX_FMT_RGB24;
868 else if (pix_fmt == IPU_PIX_FMT_LVDS666) {
869 writel(0x01, IOMUXC_BASE_ADDR + 8);
870 } else if (pix_fmt == IPU_PIX_FMT_LVDS888) {
871 writel(0x21, IOMUXC_BASE_ADDR + 8);
873 if (pix_fmt != IPU_PIX_FMT_RGB24) {
874 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
875 /* enable LDB & DI0 clock */
876 writel(readl(&ccm_regs->CCGR3) | (3 << 12) | (3 << 2),
880 if (karo_load_splashimage(0) == 0) {
881 debug("Initializing LCD controller\n");
882 ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
884 debug("Skipping initialization of LCD controller\n");
888 #define lcd_enabled 0
889 #endif /* CONFIG_LCD */
891 static void stk5_board_init(void)
893 gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
894 imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
897 static void stk5v3_board_init(void)
902 static void stk5v5_board_init(void)
906 gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
907 "Flexcan Transceiver");
908 imx_iomux_v3_setup_pad(MX6Q_PAD_DISP0_DAT0__GPIO_4_21);
911 static void tx6q_set_cpu_clock(void)
913 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
915 if (tstc() || (wrsr & WRSR_TOUT))
918 if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
921 mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK);
923 printf("CPU clock set to %u.%03u MHz\n",
924 mxc_get_clock(MXC_ARM_CLK) / 1000000,
925 mxc_get_clock(MXC_ARM_CLK) / 1000 % 1000);
928 static void tx6_init_mac(void)
931 char mac_str[ETH_ALEN * 3] = "";
933 imx_get_mac_from_fuse(-1, mac);
934 if (!is_valid_ether_addr(mac)) {
935 printf("No valid MAC address programmed\n");
939 snprintf(mac_str, sizeof(mac_str), "%02x:%02x:%02x:%02x:%02x:%02x",
940 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
941 setenv("ethaddr", mac_str);
942 printf("MAC addr from fuse: %02x:%02x:%02x:%02x:%02x:%02x\n",
943 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
946 int board_late_init(void)
949 const char *baseboard;
951 tx6q_set_cpu_clock();
954 baseboard = getenv("baseboard");
958 printf("Baseboard: %s\n", baseboard);
960 if (strncmp(baseboard, "stk5", 4) == 0) {
961 if ((strlen(baseboard) == 4) ||
962 strcmp(baseboard, "stk5-v3") == 0) {
964 } else if (strcmp(baseboard, "stk5-v5") == 0) {
967 printf("WARNING: Unsupported STK5 board rev.: %s\n",
971 printf("WARNING: Unsupported baseboard: '%s'\n",
979 gpio_set_value(TX6Q_RESET_OUT_GPIO, 1);
983 #define iomux_field(v,f) (((iomux_v3_cfg_t)(v) << f##_SHIFT) & f##_MASK)
985 #define chk_iomux_field(f1,f2) ({ \
986 iomux_v3_cfg_t __c = iomux_field(~0, f1); \
987 if (__c & f2##_MASK) { \
988 printf("%18s[%016llx] overlaps with:\n%18s[%016llx]\n", \
992 (__c & f2##_MASK) != 0; \
995 #define chk_iomux_bit(f1,f2) ({ \
996 iomux_v3_cfg_t __c = iomux_field(~0, f1); \
998 printf("%18s[%016llx] overlaps with:\n%18s[%016llx]\n", \
1000 #f2, (iomux_v3_cfg_t)f2); \
1005 int checkboard(void)
1009 printf("Board: Ka-Ro TX6Q\n");
1014 unsigned int control;
1015 unsigned int prescaler;
1016 unsigned int status;
1017 unsigned int nouse[6];
1018 unsigned int counter;
1020 const int us_delay = 10;
1021 unsigned long start = get_timer(0);
1022 unsigned long last = gd->arch.tbl;
1023 unsigned long loop = 0;
1024 unsigned long cnt = 0;
1025 static struct mxc_gpt *timer_base = (struct mxc_gpt *)GPT1_BASE_ADDR;
1027 printf("GPT prescaler=%u\n", readl(&timer_base->prescaler) + 1);
1028 printf("clock tick rate: %lu.%03lukHz\n",
1029 gd->arch.timer_rate_hz / 1000, gd->arch.timer_rate_hz % 1000);
1030 printf("ticks/us=%lu\n", gd->arch.timer_rate_hz / CONFIG_SYS_HZ / 1000);
1033 unsigned long elapsed = get_timer(start);
1034 unsigned long diff = gd->arch.tbl - last;
1037 last = gd->arch.tbl;
1039 printf("loop %4lu: t=%08lx diff=%08lx steps=%6lu elapsed time: %4lu",
1040 loop, gd->arch.tbl, diff, cnt, elapsed / CONFIG_SYS_HZ);
1042 while (get_timer(elapsed + start) < CONFIG_SYS_HZ) {
1046 printf(" counter=%08x udelay(%u)=%lu.%03luus\n",
1047 readl(&timer_base->counter), us_delay,
1048 1000000000 / cnt / 1000, 1000000000 / cnt % 1000);
1055 #if defined(CONFIG_OF_BOARD_SETUP)
1056 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1057 #include <jffs2/jffs2.h>
1058 #include <mtd_node.h>
1059 struct node_info nodes[] = {
1060 { "fsl,imx53-nand", MTD_DEV_TYPE_NAND, },
1064 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1067 static void tx6q_fixup_flexcan(void *blob)
1069 const char *baseboard = getenv("baseboard");
1071 if (baseboard && strcmp(baseboard, "stk5-v5") == 0)
1074 karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x02090000, "transceiver-switch");
1075 karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x02094000, "transceiver-switch");
1078 void tx6q_fixup_rtc(void *blob)
1080 karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupt-parent");
1081 karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupts");
1084 void ft_board_setup(void *blob, bd_t *bd)
1086 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1087 fdt_fixup_ethernet(blob);
1089 karo_fdt_fixup_touchpanel(blob);
1090 karo_fdt_fixup_usb_otg(blob, "", 0);
1091 tx6q_fixup_flexcan(blob);
1092 tx6q_fixup_rtc(blob);