board/kosagi/novena/novena_spl.c

   1 /*
   2  * Novena SPL
   3  *
   4  * Copyright (C) 2014 Marek Vasut <marex@denx.de>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/mx6-ddr.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/gpio.h>
  17 #include <asm/imx-common/boot_mode.h>
  18 #include <asm/imx-common/iomux-v3.h>
  19 #include <asm/imx-common/mxc_i2c.h>
  20 #include <i2c.h>
  21 #include <mmc.h>
  22 #include <fsl_esdhc.h>
  23 #include <spl.h>
  24
  25 #include <asm/arch/mx6-ddr.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #define UART_PAD_CTRL                                           \
  30         (PAD_CTL_PKE | PAD_CTL_PUE |                            \
  31         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  32         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  33
  34 #define USDHC_PAD_CTRL                                          \
  35         (PAD_CTL_PKE | PAD_CTL_PUE |                            \
  36         PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
  37         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  38
  39 #define ENET_PAD_CTRL                                           \
  40         (PAD_CTL_PKE | PAD_CTL_PUE |                            \
  41         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  42         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  43
  44 #define ENET_PHY_CFG_PAD_CTRL                                   \
  45         (PAD_CTL_PKE | PAD_CTL_PUE |                            \
  46         PAD_CTL_PUS_22K_UP | PAD_CTL_HYS)
  47
  48 #define RGMII_PAD_CTRL                                          \
  49         (PAD_CTL_PKE | PAD_CTL_PUE |                            \
  50         PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  51
  52 #define SPI_PAD_CTRL                                            \
  53         (PAD_CTL_HYS |                                          \
  54         PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |             \
  55         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  56
  57 #define I2C_PAD_CTRL                                            \
  58         (PAD_CTL_PKE | PAD_CTL_PUE |                            \
  59         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW |               \
  60         PAD_CTL_DSE_240ohm  | PAD_CTL_HYS |                     \
  61         PAD_CTL_ODE)
  62
  63 #define BUTTON_PAD_CTRL                                         \
  64         (PAD_CTL_PKE | PAD_CTL_PUE |                            \
  65         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  66         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  67
  68 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  69
  70 #define NOVENA_AUDIO_PWRON              IMX_GPIO_NR(5, 17)
  71 #define NOVENA_FPGA_RESET_N_GPIO        IMX_GPIO_NR(5, 7)
  72 #define NOVENA_HDMI_GHOST_HPD           IMX_GPIO_NR(5, 4)
  73 #define NOVENA_PCIE_RESET_GPIO          IMX_GPIO_NR(3, 29)
  74 #define NOVENA_PCIE_POWER_ON_GPIO       IMX_GPIO_NR(7, 12)
  75 #define NOVENA_PCIE_WAKE_UP_GPIO        IMX_GPIO_NR(3, 22)
  76 #define NOVENA_PCIE_DISABLE_GPIO        IMX_GPIO_NR(2, 16)
  77
  78 /*
  79  * Audio
  80  */
  81 static iomux_v3_cfg_t audio_pads[] = {
  82         /* AUD_PWRON */
  83         MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
  84 };
  85
  86 static void novena_spl_setup_iomux_audio(void)
  87 {
  88         imx_iomux_v3_setup_multiple_pads(audio_pads, ARRAY_SIZE(audio_pads));
  89         gpio_direction_output(NOVENA_AUDIO_PWRON, 1);
  90 }
  91
  92 /*
  93  * ENET
  94  */
  95 static iomux_v3_cfg_t enet_pads1[] = {
  96         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  97         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
  98         MX6_PAD_RGMII_TXC__RGMII_TXC            | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  99         MX6_PAD_RGMII_TD0__RGMII_TD0            | MUX_PAD_CTRL(RGMII_PAD_CTRL),
 100         MX6_PAD_RGMII_TD1__RGMII_TD1            | MUX_PAD_CTRL(RGMII_PAD_CTRL),
 101         MX6_PAD_RGMII_TD2__RGMII_TD2            | MUX_PAD_CTRL(RGMII_PAD_CTRL),
 102         MX6_PAD_RGMII_TD3__RGMII_TD3            | MUX_PAD_CTRL(RGMII_PAD_CTRL),
 103         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(RGMII_PAD_CTRL),
 104         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 105
 106         /* pin 35, PHY_AD2 */
 107         MX6_PAD_RGMII_RXC__GPIO6_IO30   | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
 108         /* pin 32, MODE0 */
 109         MX6_PAD_RGMII_RD0__GPIO6_IO25   | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
 110         /* pin 31, MODE1 */
 111         MX6_PAD_RGMII_RD1__GPIO6_IO27   | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
 112         /* pin 28, MODE2 */
 113         MX6_PAD_RGMII_RD2__GPIO6_IO28   | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
 114         /* pin 27, MODE3 */
 115         MX6_PAD_RGMII_RD3__GPIO6_IO29   | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
 116         /* pin 33, CLK125_EN */
 117         MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
 118
 119         /* pin 42 PHY nRST */
 120         MX6_PAD_EIM_D23__GPIO3_IO23             | MUX_PAD_CTRL(NO_PAD_CTRL),
 121 };
 122
 123 static iomux_v3_cfg_t enet_pads2[] = {
 124         MX6_PAD_RGMII_RXC__RGMII_RXC            | MUX_PAD_CTRL(RGMII_PAD_CTRL),
 125         MX6_PAD_RGMII_RD0__RGMII_RD0            | MUX_PAD_CTRL(RGMII_PAD_CTRL),
 126         MX6_PAD_RGMII_RD1__RGMII_RD1            | MUX_PAD_CTRL(RGMII_PAD_CTRL),
 127         MX6_PAD_RGMII_RD2__RGMII_RD2            | MUX_PAD_CTRL(RGMII_PAD_CTRL),
 128         MX6_PAD_RGMII_RD3__RGMII_RD3            | MUX_PAD_CTRL(RGMII_PAD_CTRL),
 129         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(RGMII_PAD_CTRL),
 130 };
 131
 132 static void novena_spl_setup_iomux_enet(void)
 133 {
 134         imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
 135
 136         /* Assert Ethernet PHY nRST */
 137         gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
 138
 139         /*
 140          * Use imx6 internal pull-ups to drive PHY mode pins during PHY reset
 141          * de-assertion. The intention is to use weak signal drivers (pull-ups)
 142          * to prevent the conflict between PHY pins becoming outputs after
 143          * reset and imx6 still driving the pins. The issue is described in PHY
 144          * datasheet, p.14
 145          */
 146         gpio_direction_input(IMX_GPIO_NR(6, 30)); /* PHY_AD2 = 1 */
 147         gpio_direction_input(IMX_GPIO_NR(6, 25)); /* MODE0 = 1 */
 148         gpio_direction_input(IMX_GPIO_NR(6, 27)); /* MODE1 = 1 */
 149         gpio_direction_input(IMX_GPIO_NR(6, 28)); /* MODE2 = 1 */
 150         gpio_direction_input(IMX_GPIO_NR(6, 29)); /* MODE3 = 1 */
 151         gpio_direction_input(IMX_GPIO_NR(6, 24)); /* CLK125_EN = 1 */
 152
 153         /* Following reset timing (p.53, fig.8 from the PHY datasheet) */
 154         mdelay(10);
 155
 156         /* De-assert Ethernet PHY nRST */
 157         gpio_set_value(IMX_GPIO_NR(3, 23), 1);
 158
 159         /* PHY is now configured, connect FEC to the pads */
 160         imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
 161
 162         /*
 163          * PHY datasheet recommends on p.53 to wait at least 100us after reset
 164          * before using MII, so we enforce the delay here
 165          */
 166         udelay(100);
 167 }
 168
 169 /*
 170  * FPGA
 171  */
 172 static iomux_v3_cfg_t fpga_pads[] = {
 173         /* FPGA_RESET_N */
 174         MX6_PAD_DISP0_DAT13__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
 175 };
 176
 177 static void novena_spl_setup_iomux_fpga(void)
 178 {
 179         imx_iomux_v3_setup_multiple_pads(fpga_pads, ARRAY_SIZE(fpga_pads));
 180         gpio_direction_output(NOVENA_FPGA_RESET_N_GPIO, 0);
 181 }
 182
 183 /*
 184  * GPIO Button
 185  */
 186 static iomux_v3_cfg_t button_pads[] = {
 187         /* Debug */
 188         MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 189 };
 190
 191 static void novena_spl_setup_iomux_buttons(void)
 192 {
 193         imx_iomux_v3_setup_multiple_pads(button_pads, ARRAY_SIZE(button_pads));
 194 }
 195
 196 /*
 197  * I2C
 198  */
 199 /*
 200  * I2C1:
 201  *  0x1d ... MMA7455L
 202  *  0x30 ... SO-DIMM temp sensor
 203  *  0x44 ... STMPE610
 204  *  0x50 ... SO-DIMM ID
 205  */
 206 struct i2c_pads_info i2c_pad_info0 = {
 207         .scl = {
 208                 .i2c_mode       = MX6_PAD_EIM_D21__I2C1_SCL | PC,
 209                 .gpio_mode      = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
 210                 .gp             = IMX_GPIO_NR(3, 21)
 211         },
 212         .sda = {
 213                 .i2c_mode       = MX6_PAD_EIM_D28__I2C1_SDA | PC,
 214                 .gpio_mode      = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
 215                 .gp             = IMX_GPIO_NR(3, 28)
 216         }
 217 };
 218
 219 /*
 220  * I2C2:
 221  *  0x08 ... PMIC
 222  *  0x3a ... HDMI DCC
 223  *  0x50 ... HDMI DCC
 224  */
 225 static struct i2c_pads_info i2c_pad_info1 = {
 226         .scl = {
 227                 .i2c_mode       = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
 228                 .gpio_mode      = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
 229                 .gp             = IMX_GPIO_NR(2, 30)
 230         },
 231         .sda = {
 232                 .i2c_mode       = MX6_PAD_EIM_D16__I2C2_SDA | PC,
 233                 .gpio_mode      = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
 234                 .gp             = IMX_GPIO_NR(3, 16)
 235         }
 236 };
 237
 238 /*
 239  * I2C3:
 240  *  0x11 ... ES8283
 241  *  0x50 ... LCD EDID
 242  *  0x56 ... EEPROM
 243  */
 244 static struct i2c_pads_info i2c_pad_info2 = {
 245         .scl = {
 246                 .i2c_mode       = MX6_PAD_EIM_D17__I2C3_SCL | PC,
 247                 .gpio_mode      = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
 248                 .gp             = IMX_GPIO_NR(3, 17)
 249         },
 250         .sda = {
 251                 .i2c_mode       = MX6_PAD_EIM_D18__I2C3_SDA | PC,
 252                 .gpio_mode      = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
 253                 .gp             = IMX_GPIO_NR(3, 18)
 254         }
 255 };
 256
 257 static void novena_spl_setup_iomux_i2c(void)
 258 {
 259         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
 260         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 261         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 262 }
 263
 264 /*
 265  * PCI express
 266  */
 267 #ifdef CONFIG_CMD_PCI
 268 static iomux_v3_cfg_t pcie_pads[] = {
 269         /* "Reset" pin */
 270         MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 271         /* "Power on" pin */
 272         MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 273         /* "Wake up" pin (input) */
 274         MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 275         /* "Disable endpoint" (rfkill) pin */
 276         MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),
 277 };
 278
 279 static void novena_spl_setup_iomux_pcie(void)
 280 {
 281         imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
 282
 283         /* Ensure PCIe is powered down */
 284         gpio_direction_output(NOVENA_PCIE_POWER_ON_GPIO, 0);
 285
 286         /* Put the card into reset */
 287         gpio_direction_output(NOVENA_PCIE_RESET_GPIO, 0);
 288
 289         /* Input signal to wake system from mPCIe card */
 290         gpio_direction_input(NOVENA_PCIE_WAKE_UP_GPIO);
 291
 292         /* Drive RFKILL high, to ensure the radio is turned on */
 293         gpio_direction_output(NOVENA_PCIE_DISABLE_GPIO, 1);
 294 }
 295 #else
 296 static inline void novena_spl_setup_iomux_pcie(void) {}
 297 #endif
 298
 299 /*
 300  * SDHC
 301  */
 302 static iomux_v3_cfg_t usdhc2_pads[] = {
 303         MX6_PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 304         MX6_PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 305         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 306         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 307         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 308         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 309         MX6_PAD_GPIO_2__GPIO1_IO02  | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
 310         MX6_PAD_GPIO_4__GPIO1_IO04  | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 311 };
 312
 313 static iomux_v3_cfg_t usdhc3_pads[] = {
 314         MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 315         MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 316         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 317         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 318         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 319         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 320 };
 321
 322 static void novena_spl_setup_iomux_sdhc(void)
 323 {
 324         imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 325         imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 326
 327         /* Big SD write-protect and card-detect */
 328         gpio_direction_input(IMX_GPIO_NR(1, 2));
 329         gpio_direction_input(IMX_GPIO_NR(1, 4));
 330 }
 331
 332 /*
 333  * SPI
 334  */
 335 #ifdef CONFIG_MXC_SPI
 336 static iomux_v3_cfg_t ecspi3_pads[] = {
 337         /* SS1 */
 338         MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 339         MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 340         MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 341         MX6_PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(SPI_PAD_CTRL),
 342         MX6_PAD_DISP0_DAT4__GPIO4_IO25 | MUX_PAD_CTRL(SPI_PAD_CTRL),
 343         MX6_PAD_DISP0_DAT5__GPIO4_IO26 | MUX_PAD_CTRL(SPI_PAD_CTRL),
 344         MX6_PAD_DISP0_DAT7__ECSPI3_RDY | MUX_PAD_CTRL(SPI_PAD_CTRL),
 345 };
 346
 347 static void novena_spl_setup_iomux_spi(void)
 348 {
 349         imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads));
 350         /* De-assert the nCS */
 351         gpio_direction_output(MX6_PAD_DISP0_DAT3__GPIO4_IO24, 1);
 352         gpio_direction_output(MX6_PAD_DISP0_DAT4__GPIO4_IO25, 1);
 353         gpio_direction_output(MX6_PAD_DISP0_DAT5__GPIO4_IO26, 1);
 354 }
 355 #else
 356 static void novena_spl_setup_iomux_spi(void) {}
 357 #endif
 358
 359 /*
 360  * UART
 361  */
 362 static iomux_v3_cfg_t const uart2_pads[] = {
 363         MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 364         MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 365 };
 366
 367 static iomux_v3_cfg_t const uart3_pads[] = {
 368         MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 369         MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 370 };
 371
 372 static iomux_v3_cfg_t const uart4_pads[] = {
 373         MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 374         MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 375         MX6_PAD_CSI0_DAT16__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
 376         MX6_PAD_CSI0_DAT17__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
 377
 378 };
 379
 380 static void novena_spl_setup_iomux_uart(void)
 381 {
 382         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 383         imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
 384         imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 385 }
 386
 387 /*
 388  * Video
 389  */
 390 #ifdef CONFIG_VIDEO
 391 static iomux_v3_cfg_t hdmi_pads[] = {
 392         /* "Ghost HPD" pin */
 393         MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
 394 };
 395
 396 static void novena_spl_setup_iomux_video(void)
 397 {
 398         imx_iomux_v3_setup_multiple_pads(hdmi_pads, ARRAY_SIZE(hdmi_pads));
 399         gpio_direction_input(NOVENA_HDMI_GHOST_HPD);
 400 }
 401 #else
 402 static inline void novena_spl_setup_iomux_video(void) {}
 403 #endif
 404
 405 /*
 406  * SPL boots from uSDHC card
 407  */
 408 #ifdef CONFIG_FSL_ESDHC
 409 static struct fsl_esdhc_cfg usdhc_cfg = {
 410         USDHC3_BASE_ADDR, 0, 4
 411 };
 412
 413 int board_mmc_getcd(struct mmc *mmc)
 414 {
 415         /* There is no CD for a microSD card, assume always present. */
 416         return 1;
 417 }
 418
 419 int board_mmc_init(bd_t *bis)
 420 {
 421         usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 422         return fsl_esdhc_initialize(bis, &usdhc_cfg);
 423 }
 424 #endif
 425
 426 /* Configure MX6Q/DUAL mmdc DDR io registers */
 427 static struct mx6dq_iomux_ddr_regs novena_ddr_ioregs = {
 428         /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
 429         .dram_sdclk_0           = 0x00020038,
 430         .dram_sdclk_1           = 0x00020038,
 431         .dram_cas               = 0x00000038,
 432         .dram_ras               = 0x00000038,
 433         .dram_reset             = 0x00000038,
 434         /* SDCKE[0:1]: 100k pull-up */
 435         .dram_sdcke0            = 0x00003000,
 436         .dram_sdcke1            = 0x00003000,
 437         /* SDBA2: pull-up disabled */
 438         .dram_sdba2             = 0x00000000,
 439         /* SDODT[0:1]: 100k pull-up, 40 ohm */
 440         .dram_sdodt0            = 0x00000038,
 441         .dram_sdodt1            = 0x00000038,
 442         /* SDQS[0:7]: Differential input, 40 ohm */
 443         .dram_sdqs0             = 0x00000038,
 444         .dram_sdqs1             = 0x00000038,
 445         .dram_sdqs2             = 0x00000038,
 446         .dram_sdqs3             = 0x00000038,
 447         .dram_sdqs4             = 0x00000038,
 448         .dram_sdqs5             = 0x00000038,
 449         .dram_sdqs6             = 0x00000038,
 450         .dram_sdqs7             = 0x00000038,
 451
 452         /* DQM[0:7]: Differential input, 40 ohm */
 453         .dram_dqm0              = 0x00000038,
 454         .dram_dqm1              = 0x00000038,
 455         .dram_dqm2              = 0x00000038,
 456         .dram_dqm3              = 0x00000038,
 457         .dram_dqm4              = 0x00000038,
 458         .dram_dqm5              = 0x00000038,
 459         .dram_dqm6              = 0x00000038,
 460         .dram_dqm7              = 0x00000038,
 461 };
 462
 463 /* Configure MX6Q/DUAL mmdc GRP io registers */
 464 static struct mx6dq_iomux_grp_regs novena_grp_ioregs = {
 465         /* DDR3 */
 466         .grp_ddr_type           = 0x000c0000,
 467         .grp_ddrmode_ctl        = 0x00020000,
 468         /* Disable DDR pullups */
 469         .grp_ddrpke             = 0x00000000,
 470         /* ADDR[00:16], SDBA[0:1]: 40 ohm */
 471         .grp_addds              = 0x00000038,
 472         /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
 473         .grp_ctlds              = 0x00000038,
 474         /* DATA[00:63]: Differential input, 40 ohm */
 475         .grp_ddrmode            = 0x00020000,
 476         .grp_b0ds               = 0x00000038,
 477         .grp_b1ds               = 0x00000038,
 478         .grp_b2ds               = 0x00000038,
 479         .grp_b3ds               = 0x00000038,
 480         .grp_b4ds               = 0x00000038,
 481         .grp_b5ds               = 0x00000038,
 482         .grp_b6ds               = 0x00000038,
 483         .grp_b7ds               = 0x00000038,
 484 };
 485
 486 static struct mx6_mmdc_calibration novena_mmdc_calib = {
 487         /* write leveling calibration determine */
 488         .p0_mpwldectrl0         = 0x00420048,
 489         .p0_mpwldectrl1         = 0x006f0059,
 490         .p1_mpwldectrl0         = 0x005a0104,
 491         .p1_mpwldectrl1         = 0x01070113,
 492         /* Read DQS Gating calibration */
 493         .p0_mpdgctrl0           = 0x437c040b,
 494         .p0_mpdgctrl1           = 0x0413040e,
 495         .p1_mpdgctrl0           = 0x444f0446,
 496         .p1_mpdgctrl1           = 0x044d0422,
 497         /* Read Calibration: DQS delay relative to DQ read access */
 498         .p0_mprddlctl           = 0x4c424249,
 499         .p1_mprddlctl           = 0x4e48414f,
 500         /* Write Calibration: DQ/DM delay relative to DQS write access */
 501         .p0_mpwrdlctl           = 0x42414641,
 502         .p1_mpwrdlctl           = 0x46374b43,
 503 };
 504
 505 static struct mx6_ddr_sysinfo novena_ddr_info = {
 506         /* Width of data bus: 0=16, 1=32, 2=64 */
 507         .dsize          = 2,
 508         /* Config for full 4GB range so that get_mem_size() works */
 509         .cs_density     = 32,   /* 32Gb per CS */
 510         /* Single chip select */
 511         .ncs            = 1,
 512         .cs1_mirror     = 0,
 513         .rtt_wr         = 1,    /* RTT_Wr = RZQ/4 */
 514         .rtt_nom        = 2,    /* RTT_Nom = RZQ/2 */
 515         .walat          = 3,    /* Write additional latency */
 516         .ralat          = 7,    /* Read additional latency */
 517         .mif3_mode      = 3,    /* Command prediction working mode */
 518         .bi_on          = 1,    /* Bank interleaving enabled */
 519         .sde_to_rst     = 0x10, /* 14 cycles, 200us (JEDEC default) */
 520         .rst_to_cke     = 0x23, /* 33 cycles, 500us (JEDEC default) */
 521 };
 522
 523 static struct mx6_ddr3_cfg elpida_4gib_1600 = {
 524         .mem_speed      = 1600,
 525         .density        = 4,
 526         .width          = 64,
 527         .banks          = 8,
 528         .rowaddr        = 16,
 529         .coladdr        = 10,
 530         .pagesz         = 2,
 531         .trcd           = 1300,
 532         .trcmin         = 4900,
 533         .trasmin        = 3590,
 534 };
 535
 536 /*
 537  * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
 538  * - we have a stack and a place to store GD, both in SRAM
 539  * - no variable global data is available
 540  */
 541 void board_init_f(ulong dummy)
 542 {
 543         /* setup AIPS and disable watchdog */
 544         arch_cpu_init();
 545
 546         /* setup GP timer */
 547         timer_init();
 548
 549 #ifdef CONFIG_BOARD_POSTCLK_INIT
 550         board_postclk_init();
 551 #endif
 552 #ifdef CONFIG_FSL_ESDHC
 553         get_clocks();
 554 #endif
 555
 556         /* Setup IOMUX and configure basics. */
 557         novena_spl_setup_iomux_audio();
 558         novena_spl_setup_iomux_buttons();
 559         novena_spl_setup_iomux_enet();
 560         novena_spl_setup_iomux_fpga();
 561         novena_spl_setup_iomux_i2c();
 562         novena_spl_setup_iomux_pcie();
 563         novena_spl_setup_iomux_sdhc();
 564         novena_spl_setup_iomux_spi();
 565         novena_spl_setup_iomux_uart();
 566         novena_spl_setup_iomux_video();
 567
 568         /* UART clocks enabled and gd valid - init serial console */
 569         preloader_console_init();
 570
 571         /* Start the DDR DRAM */
 572         mx6dq_dram_iocfg(64, &novena_ddr_ioregs, &novena_grp_ioregs);
 573         mx6_dram_cfg(&novena_ddr_info, &novena_mmdc_calib, &elpida_4gib_1600);
 574
 575         /* Clear the BSS. */
 576         memset(__bss_start, 0, __bss_end - __bss_start);
 577
 578         /* load/boot image from boot device */
 579         board_init_r(NULL, 0);
 580 }
 581
 582 void reset_cpu(ulong addr)
 583 {
 584 }