board/mini-box/picosam9g45/picosam9g45.c

   1 /*
   2  * Board functions for mini-box PICOSAM9G45 (AT91SAM9G45) based board
   3  * (C) Copyright 2015 Inter Act B.V.
   4  *
   5  * Based on:
   6  * U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
   7  * (C) Copyright 2007-2008
   8  * Stelian Pop <stelian@popies.net>
   9  * Lead Tech Design <www.leadtechdesign.com>
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 #include <common.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/clk.h>
  17 #include <asm/arch/at91sam9g45_matrix.h>
  18 #include <asm/arch/at91sam9_smc.h>
  19 #include <asm/arch/at91_common.h>
  20 #include <asm/arch/at91_pmc.h>
  21 #include <asm/arch/gpio.h>
  22 #include <asm/arch/clk.h>
  23 #include <lcd.h>
  24 #include <linux/mtd/nand.h>
  25 #include <atmel_lcdc.h>
  26 #include <atmel_mci.h>
  27 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  28 #include <net.h>
  29 #endif
  30 #include <netdev.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 /* ------------------------------------------------------------------------- */
  35 /*
  36  * Miscelaneous platform dependent initialisations
  37  */
  38
  39 #if defined(CONFIG_SPL_BUILD)
  40 #include <spl.h>
  41
  42 void at91_spl_board_init(void)
  43 {
  44 #ifdef CONFIG_SYS_USE_MMC
  45         at91_mci_hw_init();
  46 #endif
  47 }
  48
  49 #include <asm/arch/atmel_mpddrc.h>
  50 static void ddr2_conf(struct atmel_mpddr *ddr2)
  51 {
  52         ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
  53
  54         ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
  55                     ATMEL_MPDDRC_CR_NR_ROW_14 |
  56                     ATMEL_MPDDRC_CR_DQMS_SHARED |
  57                     ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
  58
  59         ddr2->rtr = 0x24b;
  60
  61         ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
  62                       2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
  63                       2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
  64                       8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */
  65                       2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
  66                       1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
  67                       1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
  68                       2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
  69
  70         ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
  71                       200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
  72                       16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
  73                       14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
  74
  75         ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
  76                       0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
  77                       7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
  78                       2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
  79 }
  80
  81 void mem_init(void)
  82 {
  83         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  84         struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  85         struct atmel_mpddr ddr2;
  86         unsigned long csa;
  87
  88         ddr2_conf(&ddr2);
  89
  90         /* enable DDR2 clock */
  91         writel(AT91_PMC_DDR, &pmc->scer);
  92
  93         /* Chip select 1 is for DDR2/SDRAM */
  94         csa = readl(&mat->ebicsa);
  95         csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
  96         csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
  97         writel(csa, &mat->ebicsa);
  98
  99         /* DDRAM2 Controller initialize */
 100         ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
 101         ddr2_init(ATMEL_BASE_DDRSDRC1, ATMEL_BASE_CS1, &ddr2);
 102 }
 103 #endif
 104
 105 #ifdef CONFIG_CMD_USB
 106 static void picosam9g45_usb_hw_init(void)
 107 {
 108         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 109
 110         writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
 111
 112         at91_set_gpio_output(AT91_PIN_PD1, 0);
 113         at91_set_gpio_output(AT91_PIN_PD3, 0);
 114 }
 115 #endif
 116
 117 #ifdef CONFIG_MACB
 118 static void picosam9g45_macb_hw_init(void)
 119 {
 120         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 121         struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
 122
 123         /* Enable clock */
 124         writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
 125
 126         /*
 127          * Disable pull-up on:
 128          *      RXDV (PA15) => PHY normal mode (not Test mode)
 129          *      ERX0 (PA12) => PHY ADDR0
 130          *      ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
 131          *
 132          * PHY has internal pull-down
 133          */
 134         writel(pin_to_mask(AT91_PIN_PA15) |
 135                pin_to_mask(AT91_PIN_PA12) |
 136                pin_to_mask(AT91_PIN_PA13),
 137                &pioa->pudr);
 138
 139         at91_phy_reset();
 140
 141         /* Re-enable pull-up */
 142         writel(pin_to_mask(AT91_PIN_PA15) |
 143                pin_to_mask(AT91_PIN_PA12) |
 144                pin_to_mask(AT91_PIN_PA13),
 145                &pioa->puer);
 146
 147         /* And the pins. */
 148         at91_macb_hw_init();
 149 }
 150 #endif
 151
 152 #ifdef CONFIG_LCD
 153
 154 vidinfo_t panel_info = {
 155         .vl_col =               480,
 156         .vl_row =               272,
 157         .vl_clk =               9000000,
 158         .vl_sync =              ATMEL_LCDC_INVLINE_NORMAL |
 159                                 ATMEL_LCDC_INVFRAME_NORMAL,
 160         .vl_bpix =              3,
 161         .vl_tft =               1,
 162         .vl_hsync_len =         45,
 163         .vl_left_margin =       1,
 164         .vl_right_margin =      1,
 165         .vl_vsync_len =         1,
 166         .vl_upper_margin =      40,
 167         .vl_lower_margin =      1,
 168         .mmio =                 ATMEL_BASE_LCDC,
 169 };
 170
 171
 172 void lcd_enable(void)
 173 {
 174         at91_set_A_periph(AT91_PIN_PE6, 1);     /* power up */
 175 }
 176
 177 void lcd_disable(void)
 178 {
 179         at91_set_A_periph(AT91_PIN_PE6, 0);     /* power down */
 180 }
 181
 182 static void picosam9g45_lcd_hw_init(void)
 183 {
 184         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 185
 186         at91_set_A_periph(AT91_PIN_PE0, 0);     /* LCDDPWR */
 187         at91_set_A_periph(AT91_PIN_PE2, 0);     /* LCDCC */
 188         at91_set_A_periph(AT91_PIN_PE3, 0);     /* LCDVSYNC */
 189         at91_set_A_periph(AT91_PIN_PE4, 0);     /* LCDHSYNC */
 190         at91_set_A_periph(AT91_PIN_PE5, 0);     /* LCDDOTCK */
 191
 192         at91_set_A_periph(AT91_PIN_PE7, 0);     /* LCDD0 */
 193         at91_set_A_periph(AT91_PIN_PE8, 0);     /* LCDD1 */
 194         at91_set_A_periph(AT91_PIN_PE9, 0);     /* LCDD2 */
 195         at91_set_A_periph(AT91_PIN_PE10, 0);    /* LCDD3 */
 196         at91_set_A_periph(AT91_PIN_PE11, 0);    /* LCDD4 */
 197         at91_set_A_periph(AT91_PIN_PE12, 0);    /* LCDD5 */
 198         at91_set_A_periph(AT91_PIN_PE13, 0);    /* LCDD6 */
 199         at91_set_A_periph(AT91_PIN_PE14, 0);    /* LCDD7 */
 200         at91_set_A_periph(AT91_PIN_PE15, 0);    /* LCDD8 */
 201         at91_set_A_periph(AT91_PIN_PE16, 0);    /* LCDD9 */
 202         at91_set_A_periph(AT91_PIN_PE17, 0);    /* LCDD10 */
 203         at91_set_A_periph(AT91_PIN_PE18, 0);    /* LCDD11 */
 204         at91_set_A_periph(AT91_PIN_PE19, 0);    /* LCDD12 */
 205         at91_set_B_periph(AT91_PIN_PE20, 0);    /* LCDD13 */
 206         at91_set_A_periph(AT91_PIN_PE21, 0);    /* LCDD14 */
 207         at91_set_A_periph(AT91_PIN_PE22, 0);    /* LCDD15 */
 208         at91_set_A_periph(AT91_PIN_PE23, 0);    /* LCDD16 */
 209         at91_set_A_periph(AT91_PIN_PE24, 0);    /* LCDD17 */
 210         at91_set_A_periph(AT91_PIN_PE25, 0);    /* LCDD18 */
 211         at91_set_A_periph(AT91_PIN_PE26, 0);    /* LCDD19 */
 212         at91_set_A_periph(AT91_PIN_PE27, 0);    /* LCDD20 */
 213         at91_set_B_periph(AT91_PIN_PE28, 0);    /* LCDD21 */
 214         at91_set_A_periph(AT91_PIN_PE29, 0);    /* LCDD22 */
 215         at91_set_A_periph(AT91_PIN_PE30, 0);    /* LCDD23 */
 216
 217         writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
 218
 219         gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
 220 }
 221
 222 #ifdef CONFIG_LCD_INFO
 223 #include <nand.h>
 224 #include <version.h>
 225
 226 void lcd_show_board_info(void)
 227 {
 228         ulong dram_size;
 229         int i;
 230         char temp[32];
 231
 232         lcd_printf("%s\n", U_BOOT_VERSION);
 233         lcd_printf("(C) 2015 Inter Act B.V.\n");
 234         lcd_printf("support@interact.nl\n");
 235         lcd_printf("%s CPU at %s MHz\n",
 236                    ATMEL_CPU_NAME,
 237                    strmhz(temp, get_cpu_clk_rate()));
 238
 239         dram_size = 0;
 240         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 241                 dram_size += gd->bd->bi_dram[i].size;
 242         lcd_printf("  %ld MB SDRAM\n", dram_size >> 20);
 243 }
 244 #endif /* CONFIG_LCD_INFO */
 245 #endif
 246
 247 #ifdef CONFIG_GENERIC_ATMEL_MCI
 248 int board_mmc_init(bd_t *bis)
 249 {
 250         at91_mci_hw_init();
 251
 252         return atmel_mci_init((void *)ATMEL_BASE_MCI0);
 253 }
 254 #endif
 255
 256 int board_early_init_f(void)
 257 {
 258         at91_seriald_hw_init();
 259         return 0;
 260 }
 261
 262 int board_init(void)
 263 {
 264         gd->bd->bi_arch_number = MACH_TYPE_PICOSAM9G45;
 265
 266         /* adress of boot parameters */
 267         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 268
 269 #ifdef CONFIG_CMD_USB
 270         picosam9g45_usb_hw_init();
 271 #endif
 272 #ifdef CONFIG_HAS_DATAFLASH
 273         at91_spi0_hw_init(1 << 0);
 274 #endif
 275 #ifdef CONFIG_ATMEL_SPI
 276         at91_spi0_hw_init(1 << 4);
 277 #endif
 278 #ifdef CONFIG_MACB
 279         picosam9g45_macb_hw_init();
 280 #endif
 281 #ifdef CONFIG_LCD
 282         picosam9g45_lcd_hw_init();
 283 #endif
 284         return 0;
 285 }
 286
 287 int dram_init(void)
 288 {
 289         gd->ram_size    = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
 290                         + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
 291
 292         return 0;
 293 }
 294
 295 void dram_init_banksize(void)
 296 {
 297         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 298         gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
 299                                                         PHYS_SDRAM_1_SIZE);
 300         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 301         gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
 302                                                         PHYS_SDRAM_2_SIZE);
 303 }
 304
 305 #ifdef CONFIG_RESET_PHY_R
 306 void reset_phy(void)
 307 {
 308 }
 309 #endif
 310
 311 int board_eth_init(bd_t *bis)
 312 {
 313         int rc = 0;
 314 #ifdef CONFIG_MACB
 315         rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
 316 #endif
 317         return rc;
 318 }
 319
 320 /* SPI chip select control */
 321 #ifdef CONFIG_ATMEL_SPI
 322 #include <spi.h>
 323
 324 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 325 {
 326         return bus == 0 && cs < 2;
 327 }
 328
 329 void spi_cs_activate(struct spi_slave *slave)
 330 {
 331         switch (slave->cs) {
 332         case 1:
 333                 at91_set_gpio_output(AT91_PIN_PB18, 0);
 334                 break;
 335         case 0:
 336         default:
 337                 at91_set_gpio_output(AT91_PIN_PB3, 0);
 338                 break;
 339         }
 340 }
 341
 342 void spi_cs_deactivate(struct spi_slave *slave)
 343 {
 344         switch (slave->cs) {
 345         case 1:
 346                 at91_set_gpio_output(AT91_PIN_PB18, 1);
 347                 break;
 348         case 0:
 349         default:
 350                 at91_set_gpio_output(AT91_PIN_PB3, 1);
 351         break;
 352         }
 353 }
 354 #endif /* CONFIG_ATMEL_SPI */