board/sacsng/clkinit.c

   1 /*
   2  * (C) Copyright 2002
   3  * Custom IDEAS, Inc. <www.cideas.com>
   4  * Jon Diekema <diekema@cideas.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <ioports.h>
  27 #include <mpc8260.h>
  28 #include <asm/cpm_8260.h>
  29 #include <configs/sacsng.h>
  30
  31 #include "clkinit.h"
  32
  33 int Daq64xSampling = 0;
  34
  35
  36 void Daq_BRG_Reset(uint brg)
  37 {
  38      volatile immap_t *immr = (immap_t *)CFG_IMMR;
  39      volatile uint *brg_ptr;
  40
  41      brg_ptr = (uint *)&immr->im_brgc1;
  42
  43      if (brg >= 5) {
  44          brg_ptr = (uint *)&immr->im_brgc5;
  45          brg -= 4;
  46      }
  47      brg_ptr += brg;
  48      *brg_ptr |=  CPM_BRG_RST;
  49      *brg_ptr &= ~CPM_BRG_RST;
  50 }
  51
  52 void Daq_BRG_Disable(uint brg)
  53 {
  54      volatile immap_t *immr = (immap_t *)CFG_IMMR;
  55      volatile uint *brg_ptr;
  56
  57      brg_ptr = (uint *)&immr->im_brgc1;
  58
  59      if (brg >= 5) {
  60          brg_ptr = (uint *)&immr->im_brgc5;
  61          brg -= 4;
  62      }
  63      brg_ptr += brg;
  64      *brg_ptr &= ~CPM_BRG_EN;
  65 }
  66
  67 void Daq_BRG_Enable(uint brg)
  68 {
  69      volatile immap_t *immr = (immap_t *)CFG_IMMR;
  70      volatile uint *brg_ptr;
  71
  72      brg_ptr = (uint *)&immr->im_brgc1;
  73      if (brg >= 5) {
  74          brg_ptr = (uint *)&immr->im_brgc5;
  75          brg -= 4;
  76      }
  77      brg_ptr += brg;
  78      *brg_ptr |= CPM_BRG_EN;
  79 }
  80
  81 uint Daq_BRG_Get_Div16(uint brg)
  82 {
  83      volatile immap_t *immr = (immap_t *)CFG_IMMR;
  84      uint *brg_ptr;
  85
  86      brg_ptr = (uint *)&immr->im_brgc1;
  87      if (brg >= 5) {
  88          brg_ptr = (uint *)&immr->im_brgc5;
  89          brg -= 4;
  90      }
  91      brg_ptr += brg;
  92
  93      if (*brg_ptr & CPM_BRG_DIV16) {
  94          /* DIV16 active */
  95          return (TRUE);
  96      }
  97      else {
  98          /* DIV16 inactive */
  99          return (FALSE);
 100      }
 101 }
 102
 103 void Daq_BRG_Set_Div16(uint brg, uint div16)
 104 {
 105      volatile immap_t *immr = (immap_t *)CFG_IMMR;
 106      uint *brg_ptr;
 107
 108      brg_ptr = (uint *)&immr->im_brgc1;
 109      if (brg >= 5) {
 110          brg_ptr = (uint *)&immr->im_brgc5;
 111          brg -= 4;
 112      }
 113      brg_ptr += brg;
 114
 115      if (div16) {
 116          /* DIV16 active */
 117          *brg_ptr |=  CPM_BRG_DIV16;
 118      }
 119      else {
 120          /* DIV16 inactive */
 121          *brg_ptr &= ~CPM_BRG_DIV16;
 122      }
 123 }
 124
 125 uint Daq_BRG_Get_Count(uint brg)
 126 {
 127      volatile immap_t *immr = (immap_t *)CFG_IMMR;
 128      uint *brg_ptr;
 129      uint brg_cnt;
 130
 131      brg_ptr = (uint *)&immr->im_brgc1;
 132      if (brg >= 5) {
 133          brg_ptr = (uint *)&immr->im_brgc5;
 134          brg -= 4;
 135      }
 136      brg_ptr += brg;
 137
 138      /* Get the clock divider
 139       *
 140       * Note: A clock divider of 0 means divide by 1,
 141       *       therefore we need to add 1 to the count.
 142       */
 143      brg_cnt = (*brg_ptr & CPM_BRG_CD_MASK) >> CPM_BRG_DIV16_SHIFT;
 144      brg_cnt++;
 145      if (*brg_ptr & CPM_BRG_DIV16) {
 146          brg_cnt *= 16;
 147      }
 148
 149     return (brg_cnt);
 150 }
 151
 152 void Daq_BRG_Set_Count(uint brg, uint brg_cnt)
 153 {
 154      volatile immap_t *immr = (immap_t *)CFG_IMMR;
 155      uint *brg_ptr;
 156
 157      brg_ptr = (uint *)&immr->im_brgc1;
 158      if (brg >= 5) {
 159          brg_ptr = (uint *)&immr->im_brgc5;
 160          brg -= 4;
 161      }
 162      brg_ptr += brg;
 163
 164      /*
 165       * Note: A clock divider of 0 means divide by 1,
 166       *  therefore we need to subtract 1 from the count.
 167       */
 168      if (brg_cnt > 4096) {
 169          /* Prescale = Divide by 16 */
 170          *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK)   |
 171              (((brg_cnt / 16) - 1) << CPM_BRG_DIV16_SHIFT);
 172          *brg_ptr |= CPM_BRG_DIV16;
 173      }
 174      else {
 175          /* Prescale = Divide by 1 */
 176          *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) |
 177              ((brg_cnt - 1) << CPM_BRG_DIV16_SHIFT);
 178          *brg_ptr &= ~CPM_BRG_DIV16;
 179      }
 180 }
 181
 182 uint Daq_BRG_Get_ExtClk(uint brg)
 183 {
 184      volatile immap_t *immr = (immap_t *)CFG_IMMR;
 185      uint *brg_ptr;
 186
 187      brg_ptr = (uint *)&immr->im_brgc1;
 188      if (brg >= 5) {
 189          brg_ptr = (uint *)&immr->im_brgc5;
 190          brg -= 4;
 191      }
 192      brg_ptr += brg;
 193
 194      return ((*brg_ptr & CPM_BRG_EXTC_MASK) >> CPM_BRG_EXTC_SHIFT);
 195 }
 196
 197 char* Daq_BRG_Get_ExtClk_Description(uint brg)
 198 {
 199      uint extc;
 200
 201      extc = Daq_BRG_Get_ExtClk(brg);
 202
 203      switch (brg + 1) {
 204          case 1:
 205          case 2:
 206          case 5:
 207          case 6: {
 208              switch (extc) {
 209                  case 0: {
 210                      return ("BRG_INT");
 211                  }
 212                  case 1: {
 213                      return ("CLK3");
 214                  }
 215                  case 2: {
 216                      return ("CLK5");
 217                  }
 218              }
 219              return ("??1245??");
 220          }
 221          case 3:
 222          case 4:
 223          case 7:
 224          case 8: {
 225              switch (extc) {
 226                  case 0: {
 227                      return ("BRG_INT");
 228                  }
 229                  case 1: {
 230                      return ("CLK9");
 231                  }
 232                  case 2: {
 233                      return ("CLK15");
 234                  }
 235              }
 236              return ("??3478??");
 237          }
 238      }
 239      return ("??9876??");
 240 }
 241
 242 void Daq_BRG_Set_ExtClk(uint brg, uint extc)
 243 {
 244      volatile immap_t *immr = (immap_t *)CFG_IMMR;
 245      uint *brg_ptr;
 246
 247      brg_ptr = (uint *)&immr->im_brgc1;
 248      if (brg >= 5) {
 249          brg_ptr = (uint *)&immr->im_brgc5;
 250          brg -= 4;
 251      }
 252      brg_ptr += brg;
 253
 254      *brg_ptr = (*brg_ptr & ~CPM_BRG_EXTC_MASK) |
 255                 ((extc << CPM_BRG_EXTC_SHIFT) & CPM_BRG_EXTC_MASK);
 256 }
 257
 258 uint Daq_BRG_Rate(uint brg)
 259 {
 260      DECLARE_GLOBAL_DATA_PTR;
 261      volatile immap_t *immr = (immap_t *)CFG_IMMR;
 262      uint *brg_ptr;
 263      uint brg_cnt;
 264      uint brg_freq = 0;
 265
 266      brg_ptr = (uint *)&immr->im_brgc1;
 267      brg_ptr += brg;
 268      if (brg >= 5) {
 269          brg_ptr = (uint *)&immr->im_brgc5;
 270          brg_ptr += (brg - 4);
 271      }
 272
 273     brg_cnt = Daq_BRG_Get_Count(brg);
 274
 275     switch (Daq_BRG_Get_ExtClk(brg)) {
 276         case CPM_BRG_EXTC_CLK3:
 277         case CPM_BRG_EXTC_CLK5: {
 278             brg_freq = brg_cnt;
 279             break;
 280         }
 281         default: {
 282             brg_freq = (uint)BRG_INT_CLK / brg_cnt;
 283         }
 284     }
 285     return (brg_freq);
 286 }
 287
 288 uint Daq_Get_SampleRate(void)
 289
 290 {
 291      /*
 292       * Read the BRG's to return the actual sample rate.
 293       */
 294      return (Daq_BRG_Rate(MCLK_BRG) / (MCLK_DIVISOR * SCLK_DIVISOR));
 295 }
 296
 297 uint Daq_Set_SampleRate(uint rate, uint force)
 298
 299 {
 300     DECLARE_GLOBAL_DATA_PTR;
 301     uint mclk_divisor; /* MCLK divisor */
 302     uint rate_curr;    /* Current sample rate */
 303
 304     /*
 305      * Limit the sample rate to some sensible values.
 306      */
 307     if (Daq64xSampling) {
 308       if (rate > MAX_64x_SAMPLE_RATE) {
 309           rate = MAX_64x_SAMPLE_RATE;
 310       }
 311     }
 312     else {
 313       if (rate > MAX_128x_SAMPLE_RATE) {
 314           rate = MAX_128x_SAMPLE_RATE;
 315       }
 316     }
 317     if (rate < MIN_SAMPLE_RATE) {
 318         rate = MIN_SAMPLE_RATE;
 319     }
 320
 321     /* Check to see if we are really changing rates */
 322     rate_curr = Daq_Get_SampleRate();
 323     if ((rate != rate_curr) || force) {
 324         /*
 325          * Dynamically adjust MCLK based on the new sample rate.
 326          */
 327
 328         /* Compute the divisors */
 329         mclk_divisor = BRG_INT_CLK / (rate * MCLK_DIVISOR * SCLK_DIVISOR);
 330
 331         /* Setup MCLK */
 332         Daq_BRG_Set_Count(MCLK_BRG, mclk_divisor);
 333
 334         /* Setup SCLK */
 335 #       ifdef RUN_SCLK_ON_BRG_INT
 336            Daq_BRG_Set_Count(SCLK_BRG, mclk_divisor * MCLK_DIVISOR);
 337 #       else
 338            Daq_BRG_Set_Count(SCLK_BRG, MCLK_DIVISOR);
 339 #       endif
 340
 341 #       ifdef RUN_LRCLK_ON_BRG_INT
 342             Daq_BRG_Set_Count(LRCLK_BRG,
 343                               mclk_divisor * MCLK_DIVISOR * SCLK_DIVISOR);
 344 #       else
 345             Daq_BRG_Set_Count(LRCLK_BRG, SCLK_DIVISOR);
 346 #       endif
 347
 348         /* Read the BRG's to return the actual sample rate. */
 349         rate_curr = Daq_Get_SampleRate();
 350     }
 351
 352     return (rate_curr);
 353 }
 354
 355 void Daq_Init_Clocks(int sample_rate, int sample_64x)
 356
 357 {
 358     volatile ioport_t *iopa = ioport_addr((immap_t *)CFG_IMMR, 0 /* port A */);
 359
 360     /* Save off the clocking data */
 361     Daq64xSampling = sample_64x;
 362
 363     /*
 364      * Limit the sample rate to some sensible values.
 365      */
 366     if (Daq64xSampling) {
 367       if (sample_rate > MAX_64x_SAMPLE_RATE) {
 368           sample_rate = MAX_64x_SAMPLE_RATE;
 369       }
 370     }
 371     else {
 372       if (sample_rate > MAX_128x_SAMPLE_RATE) {
 373           sample_rate = MAX_128x_SAMPLE_RATE;
 374       }
 375     }
 376     if (sample_rate < MIN_SAMPLE_RATE) {
 377         sample_rate = MIN_SAMPLE_RATE;
 378     }
 379
 380     /*
 381      * Initialize the MCLK/SCLK/LRCLK baud rate generators.
 382      */
 383
 384     /* Setup MCLK */
 385     Daq_BRG_Set_ExtClk(MCLK_BRG, CPM_BRG_EXTC_BRGCLK);
 386
 387     /* Setup SCLK */
 388 #   ifdef RUN_SCLK_ON_BRG_INT
 389         Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_BRGCLK);
 390 #   else
 391         Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_CLK9);
 392 #   endif
 393
 394     /* Setup LRCLK */
 395 #   ifdef RUN_LRCLK_ON_BRG_INT
 396         Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_BRGCLK);
 397 #   else
 398         Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_CLK5);
 399 #   endif
 400
 401     /* Setup the BRG rates */
 402     Daq_Set_SampleRate(sample_rate, TRUE);
 403
 404     /* Enable the clock drivers */
 405     iopa->pdat &= ~SLRCLK_EN_MASK;
 406 }
 407
 408 void Daq_Stop_Clocks(void)
 409
 410 {
 411 #ifdef TIGHTEN_UP_BRG_TIMING
 412     volatile immap_t *immr = (immap_t *)CFG_IMMR;
 413 #endif
 414
 415 #   ifdef TIGHTEN_UP_BRG_TIMING
 416         /*
 417          * Reset MCLK BRG
 418          */
 419 #       if (MCLK_BRG == 0)
 420             immr->im_brgc1 |=  CPM_BRG_RST;
 421             immr->im_brgc1 &= ~CPM_BRG_RST;
 422 #       endif
 423 #       if (MCLK_BRG == 1)
 424             immr->im_brgc2 |=  CPM_BRG_RST;
 425             immr->im_brgc2 &= ~CPM_BRG_RST;
 426 #       endif
 427 #       if (MCLK_BRG == 2)
 428             immr->im_brgc3 |=  CPM_BRG_RST;
 429             immr->im_brgc3 &= ~CPM_BRG_RST;
 430 #       endif
 431 #       if (MCLK_BRG == 3)
 432             immr->im_brgc4 |=  CPM_BRG_RST;
 433             immr->im_brgc4 &= ~CPM_BRG_RST;
 434 #       endif
 435 #       if (MCLK_BRG == 4)
 436             immr->im_brgc5 |=  CPM_BRG_RST;
 437             immr->im_brgc5 &= ~CPM_BRG_RST;
 438 #       endif
 439 #       if (MCLK_BRG == 5)
 440             immr->im_brgc6 |=  CPM_BRG_RST;
 441             immr->im_brgc6 &= ~CPM_BRG_RST;
 442 #       endif
 443 #       if (MCLK_BRG == 6)
 444             immr->im_brgc7 |=  CPM_BRG_RST;
 445             immr->im_brgc7 &= ~CPM_BRG_RST;
 446 #       endif
 447 #       if (MCLK_BRG == 7)
 448             immr->im_brgc8 |=  CPM_BRG_RST;
 449             immr->im_brgc8 &= ~CPM_BRG_RST;
 450 #       endif
 451
 452         /*
 453          * Reset SCLK BRG
 454          */
 455 #       if (SCLK_BRG == 0)
 456             immr->im_brgc1 |=  CPM_BRG_RST;
 457             immr->im_brgc1 &= ~CPM_BRG_RST;
 458 #       endif
 459 #       if (SCLK_BRG == 1)
 460             immr->im_brgc2 |=  CPM_BRG_RST;
 461             immr->im_brgc2 &= ~CPM_BRG_RST;
 462 #       endif
 463 #       if (SCLK_BRG == 2)
 464             immr->im_brgc3 |=  CPM_BRG_RST;
 465             immr->im_brgc3 &= ~CPM_BRG_RST;
 466 #       endif
 467 #       if (SCLK_BRG == 3)
 468             immr->im_brgc4 |=  CPM_BRG_RST;
 469             immr->im_brgc4 &= ~CPM_BRG_RST;
 470 #       endif
 471 #       if (SCLK_BRG == 4)
 472             immr->im_brgc5 |=  CPM_BRG_RST;
 473             immr->im_brgc5 &= ~CPM_BRG_RST;
 474 #       endif
 475 #       if (SCLK_BRG == 5)
 476             immr->im_brgc6 |=  CPM_BRG_RST;
 477             immr->im_brgc6 &= ~CPM_BRG_RST;
 478 #       endif
 479 #       if (SCLK_BRG == 6)
 480             immr->im_brgc7 |=  CPM_BRG_RST;
 481             immr->im_brgc7 &= ~CPM_BRG_RST;
 482 #       endif
 483 #       if (SCLK_BRG == 7)
 484             immr->im_brgc8 |=  CPM_BRG_RST;
 485             immr->im_brgc8 &= ~CPM_BRG_RST;
 486 #       endif
 487
 488         /*
 489          * Reset LRCLK BRG
 490          */
 491 #       if (LRCLK_BRG == 0)
 492             immr->im_brgc1 |=  CPM_BRG_RST;
 493             immr->im_brgc1 &= ~CPM_BRG_RST;
 494 #       endif
 495 #       if (LRCLK_BRG == 1)
 496             immr->im_brgc2 |=  CPM_BRG_RST;
 497             immr->im_brgc2 &= ~CPM_BRG_RST;
 498 #       endif
 499 #       if (LRCLK_BRG == 2)
 500             immr->im_brgc3 |=  CPM_BRG_RST;
 501             immr->im_brgc3 &= ~CPM_BRG_RST;
 502 #       endif
 503 #       if (LRCLK_BRG == 3)
 504             immr->im_brgc4 |=  CPM_BRG_RST;
 505             immr->im_brgc4 &= ~CPM_BRG_RST;
 506 #       endif
 507 #       if (LRCLK_BRG == 4)
 508             immr->im_brgc5 |=  CPM_BRG_RST;
 509             immr->im_brgc5 &= ~CPM_BRG_RST;
 510 #       endif
 511 #       if (LRCLK_BRG == 5)
 512             immr->im_brgc6 |=  CPM_BRG_RST;
 513             immr->im_brgc6 &= ~CPM_BRG_RST;
 514 #       endif
 515 #       if (LRCLK_BRG == 6)
 516             immr->im_brgc7 |=  CPM_BRG_RST;
 517             immr->im_brgc7 &= ~CPM_BRG_RST;
 518 #       endif
 519 #       if (LRCLK_BRG == 7)
 520             immr->im_brgc8 |=  CPM_BRG_RST;
 521             immr->im_brgc8 &= ~CPM_BRG_RST;
 522 #       endif
 523 #   else
 524         /*
 525          * Reset the clocks
 526          */
 527         Daq_BRG_Reset(MCLK_BRG);
 528         Daq_BRG_Reset(SCLK_BRG);
 529         Daq_BRG_Reset(LRCLK_BRG);
 530 #   endif
 531 }
 532
 533 void Daq_Start_Clocks(int sample_rate)
 534
 535 {
 536 #ifdef TIGHTEN_UP_BRG_TIMING
 537     volatile immap_t *immr = (immap_t *)CFG_IMMR;
 538
 539     uint          mclk_brg;       /* MCLK  BRG value */
 540     uint          sclk_brg;       /* SCLK  BRG value */
 541     uint          lrclk_brg;      /* LRCLK BRG value */
 542     uint          temp_lrclk_brg; /* Temporary LRCLK BRG value */
 543     uint          real_lrclk_brg; /* Permanent LRCLK BRG value */
 544     unsigned long flags;          /* Interrupt flags */
 545     uint          sclk_cnt;       /* SCLK count */
 546     uint          delay_cnt;      /* Delay count */
 547 #endif
 548
 549 #   ifdef TIGHTEN_UP_BRG_TIMING
 550         /*
 551          * Obtain the enabled MCLK BRG value
 552          */
 553 #       if (MCLK_BRG == 0)
 554             mclk_brg = (immr->im_brgc1 & ~CPM_BRG_RST) | CPM_BRG_EN;
 555 #       endif
 556 #       if (MCLK_BRG == 1)
 557             mclk_brg = (immr->im_brgc2 & ~CPM_BRG_RST) | CPM_BRG_EN;
 558 #       endif
 559 #       if (MCLK_BRG == 2)
 560             mclk_brg = (immr->im_brgc3 & ~CPM_BRG_RST) | CPM_BRG_EN;
 561 #       endif
 562 #       if (MCLK_BRG == 3)
 563             mclk_brg = (immr->im_brgc4 & ~CPM_BRG_RST) | CPM_BRG_EN;
 564 #       endif
 565 #       if (MCLK_BRG == 4)
 566             mclk_brg = (immr->im_brgc5 & ~CPM_BRG_RST) | CPM_BRG_EN;
 567 #       endif
 568 #       if (MCLK_BRG == 5)
 569             mclk_brg = (immr->im_brgc6 & ~CPM_BRG_RST) | CPM_BRG_EN;
 570 #       endif
 571 #       if (MCLK_BRG == 6)
 572             mclk_brg = (immr->im_brgc7 & ~CPM_BRG_RST) | CPM_BRG_EN;
 573 #       endif
 574 #       if (MCLK_BRG == 7)
 575             mclk_brg = (immr->im_brgc8 & ~CPM_BRG_RST) | CPM_BRG_EN;
 576 #       endif
 577
 578         /*
 579          * Obtain the enabled SCLK BRG value
 580          */
 581 #       if (SCLK_BRG == 0)
 582             sclk_brg = (immr->im_brgc1 & ~CPM_BRG_RST) | CPM_BRG_EN;
 583 #       endif
 584 #       if (SCLK_BRG == 1)
 585             sclk_brg = (immr->im_brgc2 & ~CPM_BRG_RST) | CPM_BRG_EN;
 586 #       endif
 587 #       if (SCLK_BRG == 2)
 588             sclk_brg = (immr->im_brgc3 & ~CPM_BRG_RST) | CPM_BRG_EN;
 589 #       endif
 590 #       if (SCLK_BRG == 3)
 591             sclk_brg = (immr->im_brgc4 & ~CPM_BRG_RST) | CPM_BRG_EN;
 592 #       endif
 593 #       if (SCLK_BRG == 4)
 594             sclk_brg = (immr->im_brgc5 & ~CPM_BRG_RST) | CPM_BRG_EN;
 595 #       endif
 596 #       if (SCLK_BRG == 5)
 597             sclk_brg = (immr->im_brgc6 & ~CPM_BRG_RST) | CPM_BRG_EN;
 598 #       endif
 599 #       if (SCLK_BRG == 6)
 600             sclk_brg = (immr->im_brgc7 & ~CPM_BRG_RST) | CPM_BRG_EN;
 601 #       endif
 602 #       if (SCLK_BRG == 7)
 603             sclk_brg = (immr->im_brgc8 & ~CPM_BRG_RST) | CPM_BRG_EN;
 604 #       endif
 605
 606         /*
 607          * Obtain the enabled LRCLK BRG value
 608          */
 609 #       if (LRCLK_BRG == 0)
 610             lrclk_brg = (immr->im_brgc1 & ~CPM_BRG_RST) | CPM_BRG_EN;
 611 #       endif
 612 #       if (LRCLK_BRG == 1)
 613             lrclk_brg = (immr->im_brgc2 & ~CPM_BRG_RST) | CPM_BRG_EN;
 614 #       endif
 615 #       if (LRCLK_BRG == 2)
 616             lrclk_brg = (immr->im_brgc3 & ~CPM_BRG_RST) | CPM_BRG_EN;
 617 #       endif
 618 #       if (LRCLK_BRG == 3)
 619             lrclk_brg = (immr->im_brgc4 & ~CPM_BRG_RST) | CPM_BRG_EN;
 620 #       endif
 621 #       if (LRCLK_BRG == 4)
 622             lrclk_brg = (immr->im_brgc5 & ~CPM_BRG_RST) | CPM_BRG_EN;
 623 #       endif
 624 #       if (LRCLK_BRG == 5)
 625             lrclk_brg = (immr->im_brgc6 & ~CPM_BRG_RST) | CPM_BRG_EN;
 626 #       endif
 627 #       if (LRCLK_BRG == 6)
 628             lrclk_brg = (immr->im_brgc7 & ~CPM_BRG_RST) | CPM_BRG_EN;
 629 #       endif
 630 #       if (LRCLK_BRG == 7)
 631             lrclk_brg = (immr->im_brgc8 & ~CPM_BRG_RST) | CPM_BRG_EN;
 632 #       endif
 633
 634         /* Save off the real LRCLK value */
 635         real_lrclk_brg = lrclk_brg;
 636
 637         /* Obtain the current SCLK count */
 638         sclk_cnt  = ((sclk_brg & 0x00001FFE) >> 1) + 1;
 639
 640         /* Compute the delay as a function of SCLK count */
 641         delay_cnt = ((sclk_cnt / 4) - 2) * 10 + 6;
 642         if (sample_rate == 43402) {
 643           delay_cnt++;
 644         }
 645
 646         /* Clear out the count */
 647         temp_lrclk_brg = sclk_brg & ~0x00001FFE;
 648
 649         /* Insert the count */
 650         temp_lrclk_brg |= ((delay_cnt + (sclk_cnt / 2) - 1) << 1) &  0x00001FFE;
 651
 652         /*
 653          * Enable MCLK BRG
 654          */
 655 #       if (MCLK_BRG == 0)
 656             immr->im_brgc1 = mclk_brg;
 657 #       endif
 658 #       if (MCLK_BRG == 1)
 659             immr->im_brgc2 = mclk_brg;
 660 #       endif
 661 #       if (MCLK_BRG == 2)
 662             immr->im_brgc3 = mclk_brg;
 663 #       endif
 664 #       if (MCLK_BRG == 3)
 665             immr->im_brgc4 = mclk_brg;
 666 #       endif
 667 #       if (MCLK_BRG == 4)
 668             immr->im_brgc5 = mclk_brg;
 669 #       endif
 670 #       if (MCLK_BRG == 5)
 671             immr->im_brgc6 = mclk_brg;
 672 #       endif
 673 #       if (MCLK_BRG == 6)
 674             immr->im_brgc7 = mclk_brg;
 675 #       endif
 676 #       if (MCLK_BRG == 7)
 677             immr->im_brgc8 = mclk_brg;
 678 #       endif
 679
 680         /*
 681          * Enable SCLK BRG
 682          */
 683 #       if (SCLK_BRG == 0)
 684             immr->im_brgc1 = sclk_brg;
 685 #       endif
 686 #       if (SCLK_BRG == 1)
 687             immr->im_brgc2 = sclk_brg;
 688 #       endif
 689 #       if (SCLK_BRG == 2)
 690             immr->im_brgc3 = sclk_brg;
 691 #       endif
 692 #       if (SCLK_BRG == 3)
 693             immr->im_brgc4 = sclk_brg;
 694 #       endif
 695 #       if (SCLK_BRG == 4)
 696             immr->im_brgc5 = sclk_brg;
 697 #       endif
 698 #       if (SCLK_BRG == 5)
 699             immr->im_brgc6 = sclk_brg;
 700 #       endif
 701 #       if (SCLK_BRG == 6)
 702             immr->im_brgc7 = sclk_brg;
 703 #       endif
 704 #       if (SCLK_BRG == 7)
 705             immr->im_brgc8 = sclk_brg;
 706 #       endif
 707
 708         /*
 709          * Enable LRCLK BRG (1st time - temporary)
 710          */
 711 #       if (LRCLK_BRG == 0)
 712              immr->im_brgc1 = temp_lrclk_brg;
 713 #       endif
 714 #       if (LRCLK_BRG == 1)
 715              immr->im_brgc2 = temp_lrclk_brg;
 716 #       endif
 717 #       if (LRCLK_BRG == 2)
 718              immr->im_brgc3 = temp_lrclk_brg;
 719 #       endif
 720 #       if (LRCLK_BRG == 3)
 721              immr->im_brgc4 = temp_lrclk_brg;
 722 #       endif
 723 #       if (LRCLK_BRG == 4)
 724              immr->im_brgc5 = temp_lrclk_brg;
 725 #       endif
 726 #       if (LRCLK_BRG == 5)
 727              immr->im_brgc6 = temp_lrclk_brg;
 728 #       endif
 729 #       if (LRCLK_BRG == 6)
 730              immr->im_brgc7 = temp_lrclk_brg;
 731 #       endif
 732 #       if (LRCLK_BRG == 7)
 733              immr->im_brgc8 = temp_lrclk_brg;
 734 #       endif
 735
 736         /*
 737          * Enable LRCLK BRG (2nd time - permanent)
 738          */
 739 #       if (LRCLK_BRG == 0)
 740              immr->im_brgc1 = real_lrclk_brg;
 741 #       endif
 742 #       if (LRCLK_BRG == 1)
 743              immr->im_brgc2 = real_lrclk_brg;
 744 #       endif
 745 #       if (LRCLK_BRG == 2)
 746              immr->im_brgc3 = real_lrclk_brg;
 747 #       endif
 748 #       if (LRCLK_BRG == 3)
 749              immr->im_brgc4 = real_lrclk_brg;
 750 #       endif
 751 #       if (LRCLK_BRG == 4)
 752              immr->im_brgc5 = real_lrclk_brg;
 753 #       endif
 754 #       if (LRCLK_BRG == 5)
 755              immr->im_brgc6 = real_lrclk_brg;
 756 #       endif
 757 #       if (LRCLK_BRG == 6)
 758              immr->im_brgc7 = real_lrclk_brg;
 759 #       endif
 760 #       if (LRCLK_BRG == 7)
 761              immr->im_brgc8 = real_lrclk_brg;
 762 #       endif
 763 #   else
 764         /*
 765          * Enable the clocks
 766          */
 767         Daq_BRG_Enable(LRCLK_BRG);
 768         Daq_BRG_Enable(SCLK_BRG);
 769         Daq_BRG_Enable(MCLK_BRG);
 770 #   endif
 771 }
 772
 773 void Daq_Display_Clocks(void)
 774
 775 {
 776     volatile immap_t *immr = (immap_t *)CFG_IMMR;
 777     uint mclk_divisor; /* Detected MCLK divisor */
 778     uint sclk_divisor; /* Detected SCLK divisor */
 779
 780     printf("\nBRG:\n");
 781     if (immr->im_brgc4 != 0) {
 782         printf("\tbrgc4\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  MCLK\n",
 783                immr->im_brgc4,
 784                (uint)&(immr->im_brgc4),
 785                Daq_BRG_Get_Count(3),
 786                Daq_BRG_Get_ExtClk(3),
 787                Daq_BRG_Get_ExtClk_Description(3));
 788     }
 789     if (immr->im_brgc8 != 0) {
 790         printf("\tbrgc8\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  SCLK\n",
 791                immr->im_brgc8,
 792                (uint)&(immr->im_brgc8),
 793                Daq_BRG_Get_Count(7),
 794                Daq_BRG_Get_ExtClk(7),
 795                Daq_BRG_Get_ExtClk_Description(7));
 796     }
 797     if (immr->im_brgc6 != 0) {
 798         printf("\tbrgc6\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  LRCLK\n",
 799                immr->im_brgc6,
 800                (uint)&(immr->im_brgc6),
 801                Daq_BRG_Get_Count(5),
 802                Daq_BRG_Get_ExtClk(5),
 803                Daq_BRG_Get_ExtClk_Description(5));
 804     }
 805     if (immr->im_brgc1 != 0) {
 806         printf("\tbrgc1\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  SMC1\n",
 807                immr->im_brgc1,
 808                (uint)&(immr->im_brgc1),
 809                Daq_BRG_Get_Count(0),
 810                Daq_BRG_Get_ExtClk(0),
 811                Daq_BRG_Get_ExtClk_Description(0));
 812     }
 813     if (immr->im_brgc2 != 0) {
 814         printf("\tbrgc2\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  SMC2\n",
 815                immr->im_brgc2,
 816                (uint)&(immr->im_brgc2),
 817                Daq_BRG_Get_Count(1),
 818                Daq_BRG_Get_ExtClk(1),
 819                Daq_BRG_Get_ExtClk_Description(1));
 820     }
 821     if (immr->im_brgc3 != 0) {
 822         printf("\tbrgc3\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  SCC1\n",
 823                immr->im_brgc3,
 824                (uint)&(immr->im_brgc3),
 825                Daq_BRG_Get_Count(2),
 826                Daq_BRG_Get_ExtClk(2),
 827                Daq_BRG_Get_ExtClk_Description(2));
 828     }
 829     if (immr->im_brgc5 != 0) {
 830         printf("\tbrgc5\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n",
 831                immr->im_brgc5,
 832                (uint)&(immr->im_brgc5),
 833                Daq_BRG_Get_Count(4),
 834                Daq_BRG_Get_ExtClk(4),
 835                Daq_BRG_Get_ExtClk_Description(4));
 836     }
 837     if (immr->im_brgc7 != 0) {
 838         printf("\tbrgc7\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n",
 839                immr->im_brgc7,
 840                (uint)&(immr->im_brgc7),
 841                Daq_BRG_Get_Count(6),
 842                Daq_BRG_Get_ExtClk(6),
 843                Daq_BRG_Get_ExtClk_Description(6));
 844     }
 845
 846 #   ifdef RUN_SCLK_ON_BRG_INT
 847         mclk_divisor = Daq_BRG_Rate(MCLK_BRG) / Daq_BRG_Rate(SCLK_BRG);
 848 #   else
 849         mclk_divisor = Daq_BRG_Get_Count(SCLK_BRG);
 850 #   endif
 851 #   ifdef RUN_LRCLK_ON_BRG_INT
 852         sclk_divisor = Daq_BRG_Rate(SCLK_BRG) / Daq_BRG_Rate(LRCLK_BRG);
 853 #   else
 854         sclk_divisor = Daq_BRG_Get_Count(LRCLK_BRG);
 855 #   endif
 856
 857     printf("\nADC/DAC Clocking (%d/%d):\n", sclk_divisor, mclk_divisor);
 858     printf("\tMCLK  %8d Hz, or %3dx SCLK, or %3dx LRCLK\n",
 859            Daq_BRG_Rate(MCLK_BRG),
 860            mclk_divisor,
 861            mclk_divisor * sclk_divisor);
 862 #   ifdef RUN_SCLK_ON_BRG_INT
 863         printf("\tSCLK  %8d Hz, or %3dx LRCLK\n",
 864                Daq_BRG_Rate(SCLK_BRG),
 865                sclk_divisor);
 866 #   else
 867         printf("\tSCLK  %8d Hz, or %3dx LRCLK\n",
 868                Daq_BRG_Rate(MCLK_BRG) / mclk_divisor,
 869                sclk_divisor);
 870 #   endif
 871 #   ifdef RUN_LRCLK_ON_BRG_INT
 872         printf("\tLRCLK %8d Hz\n",
 873                Daq_BRG_Rate(LRCLK_BRG));
 874 #   else
 875 #       ifdef RUN_SCLK_ON_BRG_INT
 876             printf("\tLRCLK %8d Hz\n",
 877                    Daq_BRG_Rate(SCLK_BRG) / sclk_divisor);
 878 #       else
 879             printf("\tLRCLK %8d Hz\n",
 880                    Daq_BRG_Rate(MCLK_BRG) / (mclk_divisor * sclk_divisor));
 881 #       endif
 882 #   endif
 883     printf("\n");
 884 }