board/samsung/smdk5250/smdk5250.c

   1 /*
   2  * Copyright (C) 2012 Samsung Electronics
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <fdtdec.h>
  25 #include <asm/io.h>
  26 #include <errno.h>
  27 #include <i2c.h>
  28 #include <lcd.h>
  29 #include <netdev.h>
  30 #include <spi.h>
  31 #include <asm/arch/cpu.h>
  32 #include <asm/arch/dwmmc.h>
  33 #include <asm/arch/gpio.h>
  34 #include <asm/arch/mmc.h>
  35 #include <asm/arch/pinmux.h>
  36 #include <asm/arch/power.h>
  37 #include <asm/arch/sromc.h>
  38 #include <asm/arch/dp_info.h>
  39 #include <power/pmic.h>
  40 #include <power/max77686_pmic.h>
  41
  42 DECLARE_GLOBAL_DATA_PTR;
  43
  44 #ifdef CONFIG_USB_EHCI_EXYNOS
  45 int board_usb_vbus_init(void)
  46 {
  47         struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
  48                                                 samsung_get_base_gpio_part1();
  49
  50         /* Enable VBUS power switch */
  51         s5p_gpio_direction_output(&gpio1->x2, 6, 1);
  52
  53         /* VBUS turn ON time */
  54         mdelay(3);
  55
  56         return 0;
  57 }
  58 #endif
  59
  60 #ifdef CONFIG_SOUND_MAX98095
  61 static void  board_enable_audio_codec(void)
  62 {
  63         struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
  64                                                 samsung_get_base_gpio_part1();
  65
  66         /* Enable MAX98095 Codec */
  67         s5p_gpio_direction_output(&gpio1->x1, 7, 1);
  68         s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
  69 }
  70 #endif
  71
  72 int board_init(void)
  73 {
  74         gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
  75
  76 #ifdef CONFIG_EXYNOS_SPI
  77         spi_init();
  78 #endif
  79 #ifdef CONFIG_USB_EHCI_EXYNOS
  80         board_usb_vbus_init();
  81 #endif
  82 #ifdef CONFIG_SOUND_MAX98095
  83         board_enable_audio_codec();
  84 #endif
  85         return 0;
  86 }
  87
  88 int dram_init(void)
  89 {
  90         int i;
  91         u32 addr;
  92
  93         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  94                 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
  95                 gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
  96         }
  97         return 0;
  98 }
  99
 100 #if defined(CONFIG_POWER)
 101 static int pmic_reg_update(struct pmic *p, int reg, uint regval)
 102 {
 103         u32 val;
 104         int ret = 0;
 105
 106         ret = pmic_reg_read(p, reg, &val);
 107         if (ret) {
 108                 debug("%s: PMIC %d register read failed\n", __func__, reg);
 109                 return -1;
 110         }
 111         val |= regval;
 112         ret = pmic_reg_write(p, reg, val);
 113         if (ret) {
 114                 debug("%s: PMIC %d register write failed\n", __func__, reg);
 115                 return -1;
 116         }
 117         return 0;
 118 }
 119
 120 int power_init_board(void)
 121 {
 122         struct pmic *p;
 123
 124         set_ps_hold_ctrl();
 125
 126         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 127
 128         if (pmic_init(I2C_PMIC))
 129                 return -1;
 130
 131         p = pmic_get("MAX77686_PMIC");
 132         if (!p)
 133                 return -ENODEV;
 134
 135         if (pmic_probe(p))
 136                 return -1;
 137
 138         if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
 139                 return -1;
 140
 141         if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
 142                                 MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
 143                 return -1;
 144
 145         /* VDD_MIF */
 146         if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
 147                                                 MAX77686_BUCK1OUT_1V)) {
 148                 debug("%s: PMIC %d register write failed\n", __func__,
 149                                                 MAX77686_REG_PMIC_BUCK1OUT);
 150                 return -1;
 151         }
 152
 153         if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
 154                                                 MAX77686_BUCK1CTRL_EN))
 155                 return -1;
 156
 157         /* VDD_ARM */
 158         if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
 159                                         MAX77686_BUCK2DVS1_1_3V)) {
 160                 debug("%s: PMIC %d register write failed\n", __func__,
 161                                                 MAX77686_REG_PMIC_BUCK2DVS1);
 162                 return -1;
 163         }
 164
 165         if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
 166                                         MAX77686_BUCK2CTRL_ON))
 167                 return -1;
 168
 169         /* VDD_INT */
 170         if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
 171                                         MAX77686_BUCK3DVS1_1_0125V)) {
 172                 debug("%s: PMIC %d register write failed\n", __func__,
 173                                                 MAX77686_REG_PMIC_BUCK3DVS1);
 174                 return -1;
 175         }
 176
 177         if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
 178                                         MAX77686_BUCK3CTRL_ON))
 179                 return -1;
 180
 181         /* VDD_G3D */
 182         if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
 183                                         MAX77686_BUCK4DVS1_1_2V)) {
 184                 debug("%s: PMIC %d register write failed\n", __func__,
 185                                                 MAX77686_REG_PMIC_BUCK4DVS1);
 186                 return -1;
 187         }
 188
 189         if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
 190                                         MAX77686_BUCK3CTRL_ON))
 191                 return -1;
 192
 193         /* VDD_LDO2 */
 194         if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
 195                                 MAX77686_LD02CTRL1_1_5V | EN_LDO))
 196                 return -1;
 197
 198         /* VDD_LDO3 */
 199         if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
 200                                 MAX77686_LD03CTRL1_1_8V | EN_LDO))
 201                 return -1;
 202
 203         /* VDD_LDO5 */
 204         if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
 205                                 MAX77686_LD05CTRL1_1_8V | EN_LDO))
 206                 return -1;
 207
 208         /* VDD_LDO10 */
 209         if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
 210                                 MAX77686_LD10CTRL1_1_8V | EN_LDO))
 211                 return -1;
 212
 213         return 0;
 214 }
 215 #endif
 216
 217 void dram_init_banksize(void)
 218 {
 219         int i;
 220         u32 addr, size;
 221         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 222                 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
 223                 size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
 224                 gd->bd->bi_dram[i].start = addr;
 225                 gd->bd->bi_dram[i].size = size;
 226         }
 227 }
 228
 229 int board_eth_init(bd_t *bis)
 230 {
 231 #ifdef CONFIG_SMC911X
 232         u32 smc_bw_conf, smc_bc_conf;
 233         struct fdt_sromc config;
 234         fdt_addr_t base_addr;
 235
 236         /* Non-FDT configuration - bank number and timing parameters*/
 237         config.bank = CONFIG_ENV_SROM_BANK;
 238         config.width = 2;
 239
 240         config.timing[FDT_SROM_TACS] = 0x01;
 241         config.timing[FDT_SROM_TCOS] = 0x01;
 242         config.timing[FDT_SROM_TACC] = 0x06;
 243         config.timing[FDT_SROM_TCOH] = 0x01;
 244         config.timing[FDT_SROM_TAH] = 0x0C;
 245         config.timing[FDT_SROM_TACP] = 0x09;
 246         config.timing[FDT_SROM_PMC] = 0x01;
 247         base_addr = CONFIG_SMC911X_BASE;
 248
 249         /* Ethernet needs data bus width of 16 bits */
 250         if (config.width != 2) {
 251                 debug("%s: Unsupported bus width %d\n", __func__,
 252                         config.width);
 253                 return -1;
 254         }
 255         smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
 256                         | SROMC_BYTE_ENABLE(config.bank);
 257
 258         smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS])   |\
 259                         SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |\
 260                         SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |\
 261                         SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |\
 262                         SROMC_BC_TAH(config.timing[FDT_SROM_TAH])   |\
 263                         SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |\
 264                         SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
 265
 266         /* Select and configure the SROMC bank */
 267         exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
 268         s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
 269         return smc911x_initialize(0, base_addr);
 270 #endif
 271         return 0;
 272 }
 273
 274 #ifdef CONFIG_DISPLAY_BOARDINFO
 275 int checkboard(void)
 276 {
 277         printf("\nBoard: SMDK5250\n");
 278         return 0;
 279 }
 280 #endif
 281
 282 #ifdef CONFIG_GENERIC_MMC
 283 int board_mmc_init(bd_t *bis)
 284 {
 285         int err, ret = 0, index, bus_width;
 286         u32 base;
 287
 288         err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
 289         if (err)
 290                 debug("SDMMC0 not configured\n");
 291         ret |= err;
 292
 293         /*EMMC: dwmmc Channel-0 with 8 bit bus width */
 294         index = 0;
 295         base =  samsung_get_base_mmc() + (0x10000 * index);
 296         bus_width = 8;
 297         err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL);
 298         if (err)
 299                 debug("dwmmc Channel-0 init failed\n");
 300         ret |= err;
 301
 302         err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
 303         if (err)
 304                 debug("SDMMC2 not configured\n");
 305         ret |= err;
 306
 307         /*SD: dwmmc Channel-2 with 4 bit bus width */
 308         index = 2;
 309         base = samsung_get_base_mmc() + (0x10000 * index);
 310         bus_width = 4;
 311         err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL);
 312         if (err)
 313                 debug("dwmmc Channel-2 init failed\n");
 314         ret |= err;
 315
 316         return ret;
 317 }
 318 #endif
 319
 320 static int board_uart_init(void)
 321 {
 322         int err, uart_id, ret = 0;
 323
 324         for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
 325                 err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
 326                 if (err) {
 327                         debug("UART%d not configured\n",
 328                               (uart_id - PERIPH_ID_UART0));
 329                         ret |= err;
 330                 }
 331         }
 332         return ret;
 333 }
 334
 335 #ifdef CONFIG_BOARD_EARLY_INIT_F
 336 int board_early_init_f(void)
 337 {
 338         int err;
 339         err = board_uart_init();
 340         if (err) {
 341                 debug("UART init failed\n");
 342                 return err;
 343         }
 344 #ifdef CONFIG_SYS_I2C_INIT_BOARD
 345         board_i2c_init(NULL);
 346 #endif
 347         return err;
 348 }
 349 #endif
 350
 351 #ifdef CONFIG_LCD
 352 void exynos_cfg_lcd_gpio(void)
 353 {
 354         struct exynos5_gpio_part1 *gpio1 =
 355                 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
 356
 357         /* For Backlight */
 358         s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
 359         s5p_gpio_set_value(&gpio1->b2, 0, 1);
 360
 361         /* LCD power on */
 362         s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
 363         s5p_gpio_set_value(&gpio1->x1, 5, 1);
 364
 365         /* Set Hotplug detect for DP */
 366         s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
 367 }
 368
 369 void exynos_set_dp_phy(unsigned int onoff)
 370 {
 371         set_dp_phy_ctrl(onoff);
 372 }
 373
 374 vidinfo_t panel_info = {
 375         .vl_freq        = 60,
 376         .vl_col         = 2560,
 377         .vl_row         = 1600,
 378         .vl_width       = 2560,
 379         .vl_height      = 1600,
 380         .vl_clkp        = CONFIG_SYS_LOW,
 381         .vl_hsp         = CONFIG_SYS_LOW,
 382         .vl_vsp         = CONFIG_SYS_LOW,
 383         .vl_dp          = CONFIG_SYS_LOW,
 384         .vl_bpix        = 4,    /* LCD_BPP = 2^4, for output conosle on LCD */
 385
 386         /* wDP panel timing infomation */
 387         .vl_hspw        = 32,
 388         .vl_hbpd        = 80,
 389         .vl_hfpd        = 48,
 390
 391         .vl_vspw        = 6,
 392         .vl_vbpd        = 37,
 393         .vl_vfpd        = 3,
 394         .vl_cmd_allow_len = 0xf,
 395
 396         .win_id         = 3,
 397         .dual_lcd_enabled = 0,
 398
 399         .init_delay     = 0,
 400         .power_on_delay = 0,
 401         .reset_delay    = 0,
 402         .interface_mode = FIMD_RGB_INTERFACE,
 403         .dp_enabled     = 1,
 404 };
 405
 406 static struct edp_device_info edp_info = {
 407         .disp_info = {
 408                 .h_res = 2560,
 409                 .h_sync_width = 32,
 410                 .h_back_porch = 80,
 411                 .h_front_porch = 48,
 412                 .v_res = 1600,
 413                 .v_sync_width  = 6,
 414                 .v_back_porch = 37,
 415                 .v_front_porch = 3,
 416                 .v_sync_rate = 60,
 417         },
 418         .lt_info = {
 419                 .lt_status = DP_LT_NONE,
 420         },
 421         .video_info = {
 422                 .master_mode = 0,
 423                 .bist_mode = DP_DISABLE,
 424                 .bist_pattern = NO_PATTERN,
 425                 .h_sync_polarity = 0,
 426                 .v_sync_polarity = 0,
 427                 .interlaced = 0,
 428                 .color_space = COLOR_RGB,
 429                 .dynamic_range = VESA,
 430                 .ycbcr_coeff = COLOR_YCBCR601,
 431                 .color_depth = COLOR_8,
 432         },
 433 };
 434
 435 static struct exynos_dp_platform_data dp_platform_data = {
 436         .edp_dev_info   = &edp_info,
 437 };
 438
 439 void init_panel_info(vidinfo_t *vid)
 440 {
 441         vid->rgb_mode   = MODE_RGB_P;
 442         exynos_set_dp_platform_data(&dp_platform_data);
 443 }
 444 #endif