arm: pxa: config option for PXA270 turbo mode
[karo-tx-uboot.git] / board / samsung / smdk5250 / smdk5250.c
1 /*
2  * Copyright (C) 2012 Samsung Electronics
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22
23 #include <common.h>
24 #include <fdtdec.h>
25 #include <asm/io.h>
26 #include <errno.h>
27 #include <i2c.h>
28 #include <lcd.h>
29 #include <netdev.h>
30 #include <spi.h>
31 #include <asm/arch/cpu.h>
32 #include <asm/arch/gpio.h>
33 #include <asm/arch/mmc.h>
34 #include <asm/arch/pinmux.h>
35 #include <asm/arch/power.h>
36 #include <asm/arch/sromc.h>
37 #include <asm/arch/dp_info.h>
38 #include <power/pmic.h>
39 #include <power/max77686_pmic.h>
40 #include <tmu.h>
41
42 DECLARE_GLOBAL_DATA_PTR;
43
44 #if defined CONFIG_EXYNOS_TMU
45 /*
46  * Boot Time Thermal Analysis for SoC temperature threshold breach
47  */
48 static void boot_temp_check(void)
49 {
50         int temp;
51
52         switch (tmu_monitor(&temp)) {
53         /* Status TRIPPED ans WARNING means corresponding threshold breach */
54         case TMU_STATUS_TRIPPED:
55                 puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n");
56                 set_ps_hold_ctrl();
57                 hang();
58                 break;
59         case TMU_STATUS_WARNING:
60                 puts("EXYNOS_TMU: WARNING! Temperature very high\n");
61                 break;
62         /*
63          * TMU_STATUS_INIT means something is wrong with temperature sensing
64          * and TMU status was changed back from NORMAL to INIT.
65          */
66         case TMU_STATUS_INIT:
67         default:
68                 debug("EXYNOS_TMU: Unknown TMU state\n");
69         }
70 }
71 #endif
72
73 #ifdef CONFIG_USB_EHCI_EXYNOS
74 int board_usb_vbus_init(void)
75 {
76         struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
77                                                 samsung_get_base_gpio_part1();
78
79         /* Enable VBUS power switch */
80         s5p_gpio_direction_output(&gpio1->x2, 6, 1);
81
82         /* VBUS turn ON time */
83         mdelay(3);
84
85         return 0;
86 }
87 #endif
88
89 #ifdef CONFIG_SOUND_MAX98095
90 static void  board_enable_audio_codec(void)
91 {
92         struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
93                                                 samsung_get_base_gpio_part1();
94
95         /* Enable MAX98095 Codec */
96         s5p_gpio_direction_output(&gpio1->x1, 7, 1);
97         s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
98 }
99 #endif
100
101 int board_init(void)
102 {
103         gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
104
105 #if defined CONFIG_EXYNOS_TMU
106         if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) {
107                 debug("%s: Failed to init TMU\n", __func__);
108                 return -1;
109         }
110         boot_temp_check();
111 #endif
112
113 #ifdef CONFIG_EXYNOS_SPI
114         spi_init();
115 #endif
116 #ifdef CONFIG_USB_EHCI_EXYNOS
117         board_usb_vbus_init();
118 #endif
119 #ifdef CONFIG_SOUND_MAX98095
120         board_enable_audio_codec();
121 #endif
122         return 0;
123 }
124
125 int dram_init(void)
126 {
127         gd->ram_size    = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
128                         + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
129                         + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
130                         + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)
131                         + get_ram_size((long *)PHYS_SDRAM_5, PHYS_SDRAM_7_SIZE)
132                         + get_ram_size((long *)PHYS_SDRAM_6, PHYS_SDRAM_7_SIZE)
133                         + get_ram_size((long *)PHYS_SDRAM_7, PHYS_SDRAM_7_SIZE)
134                         + get_ram_size((long *)PHYS_SDRAM_8, PHYS_SDRAM_8_SIZE);
135         return 0;
136 }
137
138 #if defined(CONFIG_POWER)
139 static int pmic_reg_update(struct pmic *p, int reg, uint regval)
140 {
141         u32 val;
142         int ret = 0;
143
144         ret = pmic_reg_read(p, reg, &val);
145         if (ret) {
146                 debug("%s: PMIC %d register read failed\n", __func__, reg);
147                 return -1;
148         }
149         val |= regval;
150         ret = pmic_reg_write(p, reg, val);
151         if (ret) {
152                 debug("%s: PMIC %d register write failed\n", __func__, reg);
153                 return -1;
154         }
155         return 0;
156 }
157
158 int power_init_board(void)
159 {
160         struct pmic *p;
161
162         set_ps_hold_ctrl();
163
164         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
165
166         if (pmic_init(I2C_PMIC))
167                 return -1;
168
169         p = pmic_get("MAX77686_PMIC");
170         if (!p)
171                 return -ENODEV;
172
173         if (pmic_probe(p))
174                 return -1;
175
176         if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
177                 return -1;
178
179         if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
180                                 MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
181                 return -1;
182
183         /* VDD_MIF */
184         if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
185                                                 MAX77686_BUCK1OUT_1V)) {
186                 debug("%s: PMIC %d register write failed\n", __func__,
187                                                 MAX77686_REG_PMIC_BUCK1OUT);
188                 return -1;
189         }
190
191         if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
192                                                 MAX77686_BUCK1CTRL_EN))
193                 return -1;
194
195         /* VDD_ARM */
196         if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
197                                         MAX77686_BUCK2DVS1_1_3V)) {
198                 debug("%s: PMIC %d register write failed\n", __func__,
199                                                 MAX77686_REG_PMIC_BUCK2DVS1);
200                 return -1;
201         }
202
203         if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
204                                         MAX77686_BUCK2CTRL_ON))
205                 return -1;
206
207         /* VDD_INT */
208         if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
209                                         MAX77686_BUCK3DVS1_1_0125V)) {
210                 debug("%s: PMIC %d register write failed\n", __func__,
211                                                 MAX77686_REG_PMIC_BUCK3DVS1);
212                 return -1;
213         }
214
215         if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
216                                         MAX77686_BUCK3CTRL_ON))
217                 return -1;
218
219         /* VDD_G3D */
220         if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
221                                         MAX77686_BUCK4DVS1_1_2V)) {
222                 debug("%s: PMIC %d register write failed\n", __func__,
223                                                 MAX77686_REG_PMIC_BUCK4DVS1);
224                 return -1;
225         }
226
227         if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
228                                         MAX77686_BUCK3CTRL_ON))
229                 return -1;
230
231         /* VDD_LDO2 */
232         if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
233                                 MAX77686_LD02CTRL1_1_5V | EN_LDO))
234                 return -1;
235
236         /* VDD_LDO3 */
237         if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
238                                 MAX77686_LD03CTRL1_1_8V | EN_LDO))
239                 return -1;
240
241         /* VDD_LDO5 */
242         if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
243                                 MAX77686_LD05CTRL1_1_8V | EN_LDO))
244                 return -1;
245
246         /* VDD_LDO10 */
247         if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
248                                 MAX77686_LD10CTRL1_1_8V | EN_LDO))
249                 return -1;
250
251         return 0;
252 }
253 #endif
254
255 void dram_init_banksize(void)
256 {
257         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
258         gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
259                                                         PHYS_SDRAM_1_SIZE);
260         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
261         gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
262                                                         PHYS_SDRAM_2_SIZE);
263         gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
264         gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3,
265                                                         PHYS_SDRAM_3_SIZE);
266         gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
267         gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,
268                                                         PHYS_SDRAM_4_SIZE);
269         gd->bd->bi_dram[4].start = PHYS_SDRAM_5;
270         gd->bd->bi_dram[4].size = get_ram_size((long *)PHYS_SDRAM_5,
271                                                         PHYS_SDRAM_5_SIZE);
272         gd->bd->bi_dram[5].start = PHYS_SDRAM_6;
273         gd->bd->bi_dram[5].size = get_ram_size((long *)PHYS_SDRAM_6,
274                                                         PHYS_SDRAM_6_SIZE);
275         gd->bd->bi_dram[6].start = PHYS_SDRAM_7;
276         gd->bd->bi_dram[6].size = get_ram_size((long *)PHYS_SDRAM_7,
277                                                         PHYS_SDRAM_7_SIZE);
278         gd->bd->bi_dram[7].start = PHYS_SDRAM_8;
279         gd->bd->bi_dram[7].size = get_ram_size((long *)PHYS_SDRAM_8,
280                                                         PHYS_SDRAM_8_SIZE);
281 }
282
283 #ifdef CONFIG_OF_CONTROL
284 static int decode_sromc(const void *blob, struct fdt_sromc *config)
285 {
286         int err;
287         int node;
288
289         node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
290         if (node < 0) {
291                 debug("Could not find SROMC node\n");
292                 return node;
293         }
294
295         config->bank = fdtdec_get_int(blob, node, "bank", 0);
296         config->width = fdtdec_get_int(blob, node, "width", 2);
297
298         err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
299                         FDT_SROM_TIMING_COUNT);
300         if (err < 0) {
301                 debug("Could not decode SROMC configuration\n");
302                 return -FDT_ERR_NOTFOUND;
303         }
304
305         return 0;
306 }
307 #endif
308
309 int board_eth_init(bd_t *bis)
310 {
311 #ifdef CONFIG_SMC911X
312         u32 smc_bw_conf, smc_bc_conf;
313         struct fdt_sromc config;
314         fdt_addr_t base_addr;
315
316 #ifdef CONFIG_OF_CONTROL
317         int node;
318
319         node = decode_sromc(gd->fdt_blob, &config);
320         if (node < 0) {
321                 debug("%s: Could not find sromc configuration\n", __func__);
322                 return 0;
323         }
324         node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
325         if (node < 0) {
326                 debug("%s: Could not find lan9215 configuration\n", __func__);
327                 return 0;
328         }
329
330         /* We now have a node, so any problems from now on are errors */
331         base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
332         if (base_addr == FDT_ADDR_T_NONE) {
333                 debug("%s: Could not find lan9215 address\n", __func__);
334                 return -1;
335         }
336 #else
337         /* Non-FDT configuration - bank number and timing parameters*/
338         config.bank = CONFIG_ENV_SROM_BANK;
339         config.width = 2;
340
341         config.timing[FDT_SROM_TACS] = 0x01;
342         config.timing[FDT_SROM_TCOS] = 0x01;
343         config.timing[FDT_SROM_TACC] = 0x06;
344         config.timing[FDT_SROM_TCOH] = 0x01;
345         config.timing[FDT_SROM_TAH] = 0x0C;
346         config.timing[FDT_SROM_TACP] = 0x09;
347         config.timing[FDT_SROM_PMC] = 0x01;
348         base_addr = CONFIG_SMC911X_BASE;
349 #endif
350
351         /* Ethernet needs data bus width of 16 bits */
352         if (config.width != 2) {
353                 debug("%s: Unsupported bus width %d\n", __func__,
354                         config.width);
355                 return -1;
356         }
357         smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
358                         | SROMC_BYTE_ENABLE(config.bank);
359
360         smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS])   |\
361                         SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |\
362                         SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |\
363                         SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |\
364                         SROMC_BC_TAH(config.timing[FDT_SROM_TAH])   |\
365                         SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |\
366                         SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
367
368         /* Select and configure the SROMC bank */
369         exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
370         s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
371         return smc911x_initialize(0, base_addr);
372 #endif
373         return 0;
374 }
375
376 #ifdef CONFIG_DISPLAY_BOARDINFO
377 int checkboard(void)
378 {
379 #ifdef CONFIG_OF_CONTROL
380         const char *board_name;
381
382         board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
383         if (board_name == NULL)
384                 printf("\nUnknown Board\n");
385         else
386                 printf("\nBoard: %s\n", board_name);
387 #else
388         printf("\nBoard: SMDK5250\n");
389 #endif
390         return 0;
391 }
392 #endif
393
394 #ifdef CONFIG_GENERIC_MMC
395 int board_mmc_init(bd_t *bis)
396 {
397         int err;
398
399         err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
400         if (err) {
401                 debug("SDMMC0 not configured\n");
402                 return err;
403         }
404
405         err = s5p_mmc_init(0, 8);
406         return err;
407 }
408 #endif
409
410 static int board_uart_init(void)
411 {
412         int err;
413
414         err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
415         if (err) {
416                 debug("UART0 not configured\n");
417                 return err;
418         }
419
420         err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE);
421         if (err) {
422                 debug("UART1 not configured\n");
423                 return err;
424         }
425
426         err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
427         if (err) {
428                 debug("UART2 not configured\n");
429                 return err;
430         }
431
432         err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
433         if (err) {
434                 debug("UART3 not configured\n");
435                 return err;
436         }
437
438         return 0;
439 }
440
441 #ifdef CONFIG_BOARD_EARLY_INIT_F
442 int board_early_init_f(void)
443 {
444         int err;
445         err = board_uart_init();
446         if (err) {
447                 debug("UART init failed\n");
448                 return err;
449         }
450 #ifdef CONFIG_SYS_I2C_INIT_BOARD
451         board_i2c_init(gd->fdt_blob);
452 #endif
453         return err;
454 }
455 #endif
456
457 #ifdef CONFIG_LCD
458 void exynos_cfg_lcd_gpio(void)
459 {
460         struct exynos5_gpio_part1 *gpio1 =
461                 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
462
463         /* For Backlight */
464         s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
465         s5p_gpio_set_value(&gpio1->b2, 0, 1);
466
467         /* LCD power on */
468         s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
469         s5p_gpio_set_value(&gpio1->x1, 5, 1);
470
471         /* Set Hotplug detect for DP */
472         s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
473 }
474
475 void exynos_set_dp_phy(unsigned int onoff)
476 {
477         set_dp_phy_ctrl(onoff);
478 }
479
480 #ifndef CONFIG_OF_CONTROL
481 vidinfo_t panel_info = {
482         .vl_freq        = 60,
483         .vl_col         = 2560,
484         .vl_row         = 1600,
485         .vl_width       = 2560,
486         .vl_height      = 1600,
487         .vl_clkp        = CONFIG_SYS_LOW,
488         .vl_hsp         = CONFIG_SYS_LOW,
489         .vl_vsp         = CONFIG_SYS_LOW,
490         .vl_dp          = CONFIG_SYS_LOW,
491         .vl_bpix        = 4,    /* LCD_BPP = 2^4, for output conosle on LCD */
492
493         /* wDP panel timing infomation */
494         .vl_hspw        = 32,
495         .vl_hbpd        = 80,
496         .vl_hfpd        = 48,
497
498         .vl_vspw        = 6,
499         .vl_vbpd        = 37,
500         .vl_vfpd        = 3,
501         .vl_cmd_allow_len = 0xf,
502
503         .win_id         = 3,
504         .dual_lcd_enabled = 0,
505
506         .init_delay     = 0,
507         .power_on_delay = 0,
508         .reset_delay    = 0,
509         .interface_mode = FIMD_RGB_INTERFACE,
510         .dp_enabled     = 1,
511 };
512
513 static struct edp_device_info edp_info = {
514         .disp_info = {
515                 .h_res = 2560,
516                 .h_sync_width = 32,
517                 .h_back_porch = 80,
518                 .h_front_porch = 48,
519                 .v_res = 1600,
520                 .v_sync_width  = 6,
521                 .v_back_porch = 37,
522                 .v_front_porch = 3,
523                 .v_sync_rate = 60,
524         },
525         .lt_info = {
526                 .lt_status = DP_LT_NONE,
527         },
528         .video_info = {
529                 .master_mode = 0,
530                 .bist_mode = DP_DISABLE,
531                 .bist_pattern = NO_PATTERN,
532                 .h_sync_polarity = 0,
533                 .v_sync_polarity = 0,
534                 .interlaced = 0,
535                 .color_space = COLOR_RGB,
536                 .dynamic_range = VESA,
537                 .ycbcr_coeff = COLOR_YCBCR601,
538                 .color_depth = COLOR_8,
539         },
540 };
541
542 static struct exynos_dp_platform_data dp_platform_data = {
543         .edp_dev_info   = &edp_info,
544 };
545
546 #endif
547 void init_panel_info(vidinfo_t *vid)
548 {
549 #ifndef CONFIG_OF_CONTROL
550         vid->rgb_mode   = MODE_RGB_P,
551
552         exynos_set_dp_platform_data(&dp_platform_data);
553 #endif
554 }
555 #endif