board/samsung/smdk5250/smdk5250.c

   1 /*
   2  * Copyright (C) 2012 Samsung Electronics
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <cros_ec.h>
   9 #include <fdtdec.h>
  10 #include <asm/io.h>
  11 #include <errno.h>
  12 #include <i2c.h>
  13 #include <lcd.h>
  14 #include <netdev.h>
  15 #include <spi.h>
  16 #include <asm/arch/cpu.h>
  17 #include <asm/arch/dwmmc.h>
  18 #include <asm/arch/gpio.h>
  19 #include <asm/arch/mmc.h>
  20 #include <asm/arch/pinmux.h>
  21 #include <asm/arch/power.h>
  22 #include <asm/arch/sromc.h>
  23 #include <asm/arch/dp_info.h>
  24 #include <power/pmic.h>
  25 #include <power/max77686_pmic.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #ifdef CONFIG_SOUND_MAX98095
  30 static void  board_enable_audio_codec(void)
  31 {
  32         struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
  33                                                 samsung_get_base_gpio_part1();
  34
  35         /* Enable MAX98095 Codec */
  36         s5p_gpio_direction_output(&gpio1->x1, 7, 1);
  37         s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
  38 }
  39 #endif
  40
  41 int exynos_init(void)
  42 {
  43 #ifdef CONFIG_SOUND_MAX98095
  44         board_enable_audio_codec();
  45 #endif
  46         return 0;
  47 }
  48
  49 int board_eth_init(bd_t *bis)
  50 {
  51 #ifdef CONFIG_SMC911X
  52         u32 smc_bw_conf, smc_bc_conf;
  53         struct fdt_sromc config;
  54         fdt_addr_t base_addr;
  55
  56         /* Non-FDT configuration - bank number and timing parameters*/
  57         config.bank = CONFIG_ENV_SROM_BANK;
  58         config.width = 2;
  59
  60         config.timing[FDT_SROM_TACS] = 0x01;
  61         config.timing[FDT_SROM_TCOS] = 0x01;
  62         config.timing[FDT_SROM_TACC] = 0x06;
  63         config.timing[FDT_SROM_TCOH] = 0x01;
  64         config.timing[FDT_SROM_TAH] = 0x0C;
  65         config.timing[FDT_SROM_TACP] = 0x09;
  66         config.timing[FDT_SROM_PMC] = 0x01;
  67         base_addr = CONFIG_SMC911X_BASE;
  68
  69         /* Ethernet needs data bus width of 16 bits */
  70         if (config.width != 2) {
  71                 debug("%s: Unsupported bus width %d\n", __func__,
  72                         config.width);
  73                 return -1;
  74         }
  75         smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
  76                         | SROMC_BYTE_ENABLE(config.bank);
  77
  78         smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS])   |\
  79                         SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |\
  80                         SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |\
  81                         SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |\
  82                         SROMC_BC_TAH(config.timing[FDT_SROM_TAH])   |\
  83                         SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |\
  84                         SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
  85
  86         /* Select and configure the SROMC bank */
  87         exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
  88         s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
  89         return smc911x_initialize(0, base_addr);
  90 #endif
  91         return 0;
  92 }
  93
  94 #ifdef CONFIG_DISPLAY_BOARDINFO
  95 int checkboard(void)
  96 {
  97         printf("\nBoard: SMDK5250\n");
  98         return 0;
  99 }
 100 #endif
 101
 102 #ifdef CONFIG_GENERIC_MMC
 103 int board_mmc_init(bd_t *bis)
 104 {
 105         int err, ret = 0, index, bus_width;
 106         u32 base;
 107
 108         err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
 109         if (err)
 110                 debug("SDMMC0 not configured\n");
 111         ret |= err;
 112
 113         /*EMMC: dwmmc Channel-0 with 8 bit bus width */
 114         index = 0;
 115         base =  samsung_get_base_mmc() + (0x10000 * index);
 116         bus_width = 8;
 117         err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL);
 118         if (err)
 119                 debug("dwmmc Channel-0 init failed\n");
 120         ret |= err;
 121
 122         err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
 123         if (err)
 124                 debug("SDMMC2 not configured\n");
 125         ret |= err;
 126
 127         /*SD: dwmmc Channel-2 with 4 bit bus width */
 128         index = 2;
 129         base = samsung_get_base_mmc() + (0x10000 * index);
 130         bus_width = 4;
 131         err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL);
 132         if (err)
 133                 debug("dwmmc Channel-2 init failed\n");
 134         ret |= err;
 135
 136         return ret;
 137 }
 138 #endif
 139
 140 void board_i2c_init(const void *blob)
 141 {
 142         int i;
 143
 144         for (i = 0; i < CONFIG_MAX_I2C_NUM; i++) {
 145                 exynos_pinmux_config((PERIPH_ID_I2C0 + i),
 146                                      PINMUX_FLAG_NONE);
 147         }
 148 }
 149
 150 #ifdef CONFIG_LCD
 151 void exynos_cfg_lcd_gpio(void)
 152 {
 153         struct exynos5_gpio_part1 *gpio1 =
 154                 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
 155
 156         /* For Backlight */
 157         s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
 158         s5p_gpio_set_value(&gpio1->b2, 0, 1);
 159
 160         /* LCD power on */
 161         s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
 162         s5p_gpio_set_value(&gpio1->x1, 5, 1);
 163
 164         /* Set Hotplug detect for DP */
 165         s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
 166 }
 167
 168 void exynos_set_dp_phy(unsigned int onoff)
 169 {
 170         set_dp_phy_ctrl(onoff);
 171 }
 172
 173 vidinfo_t panel_info = {
 174         .vl_freq        = 60,
 175         .vl_col         = 2560,
 176         .vl_row         = 1600,
 177         .vl_width       = 2560,
 178         .vl_height      = 1600,
 179         .vl_clkp        = CONFIG_SYS_LOW,
 180         .vl_hsp         = CONFIG_SYS_LOW,
 181         .vl_vsp         = CONFIG_SYS_LOW,
 182         .vl_dp          = CONFIG_SYS_LOW,
 183         .vl_bpix        = 4,    /* LCD_BPP = 2^4, for output conosle on LCD */
 184
 185         /* wDP panel timing infomation */
 186         .vl_hspw        = 32,
 187         .vl_hbpd        = 80,
 188         .vl_hfpd        = 48,
 189
 190         .vl_vspw        = 6,
 191         .vl_vbpd        = 37,
 192         .vl_vfpd        = 3,
 193         .vl_cmd_allow_len = 0xf,
 194
 195         .win_id         = 3,
 196         .dual_lcd_enabled = 0,
 197
 198         .init_delay     = 0,
 199         .power_on_delay = 0,
 200         .reset_delay    = 0,
 201         .interface_mode = FIMD_RGB_INTERFACE,
 202         .dp_enabled     = 1,
 203 };
 204
 205 static struct edp_device_info edp_info = {
 206         .disp_info = {
 207                 .h_res = 2560,
 208                 .h_sync_width = 32,
 209                 .h_back_porch = 80,
 210                 .h_front_porch = 48,
 211                 .v_res = 1600,
 212                 .v_sync_width  = 6,
 213                 .v_back_porch = 37,
 214                 .v_front_porch = 3,
 215                 .v_sync_rate = 60,
 216         },
 217         .lt_info = {
 218                 .lt_status = DP_LT_NONE,
 219         },
 220         .video_info = {
 221                 .master_mode = 0,
 222                 .bist_mode = DP_DISABLE,
 223                 .bist_pattern = NO_PATTERN,
 224                 .h_sync_polarity = 0,
 225                 .v_sync_polarity = 0,
 226                 .interlaced = 0,
 227                 .color_space = COLOR_RGB,
 228                 .dynamic_range = VESA,
 229                 .ycbcr_coeff = COLOR_YCBCR601,
 230                 .color_depth = COLOR_8,
 231         },
 232 };
 233
 234 static struct exynos_dp_platform_data dp_platform_data = {
 235         .edp_dev_info   = &edp_info,
 236 };
 237
 238 void init_panel_info(vidinfo_t *vid)
 239 {
 240         vid->rgb_mode   = MODE_RGB_P;
 241         exynos_set_dp_platform_data(&dp_platform_data);
 242 }
 243 #endif