board/samsung/smdkv310/lowlevel_init.S

   1 /*
   2  * Lowlevel setup for SMDKV310 board based on EXYNOS4210
   3  *
   4  * Copyright (C) 2011 Samsung Electronics
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <version.h>
  27 #include <asm/arch/cpu.h>
  28
  29 /*
  30  * Register usages:
  31  *
  32  * r5 has zero always
  33  * r7 has GPIO part1 base 0x11400000
  34  * r6 has GPIO part2 base 0x11000000
  35  */
  36
  37 #define MEM_DLLl_ON
  38
  39 _TEXT_BASE:
  40         .word   CONFIG_SYS_TEXT_BASE
  41
  42         .globl lowlevel_init
  43 lowlevel_init:
  44         push    {lr}
  45
  46         /* r5 has always zero */
  47         mov     r5, #0
  48         ldr     r7, =EXYNOS4_GPIO_PART1_BASE
  49         ldr     r6, =EXYNOS4_GPIO_PART2_BASE
  50
  51         /* check reset status  */
  52         ldr     r0, =(EXYNOS4_POWER_BASE + 0x81C)       @ INFORM7
  53         ldr     r1, [r0]
  54
  55         /* AFTR wakeup reset */
  56         ldr     r2, =S5P_CHECK_DIDLE
  57         cmp     r1, r2
  58         beq     exit_wakeup
  59
  60         /* Sleep wakeup reset */
  61         ldr     r2, =S5P_CHECK_SLEEP
  62         cmp     r1, r2
  63         beq     wakeup_reset
  64
  65         /*
  66          * If U-boot is already running in ram, no need to relocate U-Boot.
  67          * Memory controller must be configured before relocating U-Boot
  68          * in ram.
  69          */
  70         ldr     r0, =0x00ffffff         /* r0 <- Mask Bits*/
  71         bic     r1, pc, r0              /* pc <- current addr of code */
  72                                         /* r1 <- unmasked bits of pc */
  73
  74         ldr     r2, _TEXT_BASE          /* r2 <- original base addr in ram */
  75         bic     r2, r2, r0              /* r2 <- unmasked bits of r2*/
  76         cmp     r1, r2                  /* compare r1, r2 */
  77         beq     1f                      /* r0 == r1 then skip sdram init */
  78
  79         /* init system clock */
  80         bl system_clock_init
  81
  82         /* Memory initialize */
  83         bl mem_ctrl_asm_init
  84
  85 1:
  86         /* for UART */
  87         bl uart_asm_init
  88         bl arch_cpu_init
  89         bl tzpc_init
  90         pop     {pc}
  91
  92 wakeup_reset:
  93         bl system_clock_init
  94         bl mem_ctrl_asm_init
  95         bl arch_cpu_init
  96         bl tzpc_init
  97
  98 exit_wakeup:
  99         /* Load return address and jump to kernel */
 100         ldr     r0, =(EXYNOS4_POWER_BASE + 0x800)       @ INFORM0
 101
 102         /* r1 = physical address of exynos4210_cpu_resume function */
 103         ldr     r1, [r0]
 104
 105         /* Jump to kernel*/
 106         mov     pc, r1
 107         nop
 108         nop
 109
 110 /*
 111  * system_clock_init: Initialize core clock and bus clock.
 112  * void system_clock_init(void)
 113  */
 114 system_clock_init:
 115         push    {lr}
 116         ldr     r0, =EXYNOS4_CLOCK_BASE
 117
 118         /* APLL(1), MPLL(1), CORE(0), HPM(0) */
 119         ldr     r1, =0x0101
 120         ldr     r2, =0x14200                    @CLK_SRC_CPU
 121         str     r1, [r0, r2]
 122
 123         /* wait ?us */
 124         mov     r1, #0x10000
 125 2:      subs    r1, r1, #1
 126         bne     2b
 127
 128         ldr     r1, =0x00
 129         ldr     r2, =0x0C210                    @CLK_SRC_TOP0
 130         str     r1, [r0, r2]
 131
 132         ldr     r1, =0x00
 133         ldr     r2, =0x0C214                    @CLK_SRC_TOP1_OFFSET
 134         str     r1, [r0, r2]
 135
 136         /* DMC */
 137         ldr     r1, =0x00
 138         ldr     r2, =0x10200                    @CLK_SRC_DMC_OFFSET
 139         str     r1, [r0, r2]
 140
 141         /*CLK_SRC_LEFTBUS */
 142         ldr     r1, =0x00
 143         ldr     r2, =0x04200                    @CLK_SRC_LEFTBUS_OFFSET
 144         str     r1, [r0, r2]
 145
 146         /*CLK_SRC_RIGHTBUS */
 147         ldr     r1, =0x00
 148         ldr     r2, =0x08200                    @CLK_SRC_RIGHTBUS_OFFSET
 149         str     r1, [r0, r2]
 150
 151         /* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
 152         ldr     r1, =0x066666
 153         ldr     r2, =0x0C240                    @ CLK_SRC_FSYS
 154         str     r1, [r0, r2]
 155
 156         /* UART[0:4], PWM: SCLKMPLL(6) */
 157         ldr     r1, =0x06666666
 158         ldr     r2, =0x0C250                    @CLK_SRC_PERIL0_OFFSET
 159         str     r1, [r0, r2]
 160
 161         /* wait ?us */
 162         mov     r1, #0x10000
 163 3:      subs    r1, r1, #1
 164         bne     3b
 165
 166         /*
 167          * CLK_DIV_CPU0:
 168          *
 169          * PCLK_DBG_RATIO[20]   0x1
 170          * ATB_RATIO[16]        0x3
 171          * PERIPH_RATIO[12]     0x3
 172          * COREM1_RATIO[8]      0x7
 173          * COREM0_RATIO[4]      0x3
 174          */
 175         ldr     r1, =0x0133730
 176         ldr     r2, =0x14500                    @CLK_DIV_CPU0_OFFSET
 177         str     r1, [r0, r2]
 178
 179         /* CLK_DIV_CPU1: COPY_RATIO [0] 0x3 */
 180         ldr     r1, =0x03
 181         ldr     r2, =0x14504                    @CLK_DIV_CPU1_OFFSET
 182         str     r1, [r0, r2]
 183
 184         /*
 185          * CLK_DIV_DMC0:
 186          *
 187          * CORE_TIMERS_RATIO[28]        0x1
 188          * COPY2_RATIO[24]      0x3
 189          * DMCP_RATIO[20]       0x1
 190          * DMCD_RATIO[16]       0x1
 191          * DMC_RATIO[12]        0x1
 192          * DPHY_RATIO[8]        0x1
 193          * ACP_PCLK_RATIO[4]    0x1
 194          * ACP_RATIO[0]         0x3
 195          */
 196         ldr     r1, =0x13111113
 197         ldr     r2, =0x010500                   @CLK_DIV_DMC0_OFFSET
 198         str     r1, [r0, r2]
 199
 200         /*
 201          * CLK_DIV_DMC1:
 202          *
 203          * DPM_RATIO[24]        0x1
 204          * DVSEM_RATIO[16]      0x1
 205          * PWI_RATIO[8]         0x1
 206          */
 207         ldr     r1, =0x01010100
 208         ldr     r2, =0x010504                   @CLK_DIV_DMC1_OFFSET
 209         str     r1, [r0, r2]
 210
 211         /*
 212          * CLK_DIV_LEFRBUS:
 213          *
 214          * GPL_RATIO[4]         0x1
 215          * GDL_RATIO[0]         0x3
 216          */
 217         ldr     r1, =0x013
 218         ldr     r2, =0x04500                    @CLK_DIV_LEFTBUS_OFFSET
 219         str     r1, [r0, r2]
 220
 221         /*
 222          * CLK_DIV_RIGHTBUS:
 223          *
 224          * GPR_RATIO[4]         0x1
 225          * GDR_RATIO[0]         0x3
 226          */
 227         ldr     r1, =0x013
 228         ldr     r2, =0x08500                    @CLK_DIV_RIGHTBUS_OFFSET
 229         str     r1, [r0, r2]
 230
 231         /*
 232          * CLK_DIV_TOP:
 233          *
 234          * ONENAND_RATIO[16]    0x0
 235          * ACLK_133_RATIO[12]   0x5
 236          * ACLK_160_RATIO[8]    0x4
 237          * ACLK_100_RATIO[4]    0x7
 238          * ACLK_200_RATIO[0]    0x3
 239          */
 240         ldr     r1, =0x05473
 241         ldr     r2, =0x0C510                    @CLK_DIV_TOP_OFFSET
 242         str     r1, [r0, r2]
 243
 244         /* MMC[0:1] */
 245         ldr     r1, =0x000f000f                 /* 800(MPLL) / (15 + 1) */
 246         ldr     r2, =0x0C544                    @ CLK_DIV_FSYS1
 247         str     r1, [r0, r2]
 248
 249         /* MMC[2:3] */
 250         ldr     r1, =0x000f000f                 /* 800(MPLL) / (15 + 1) */
 251         ldr     r2, =0x0C548                    @ CLK_DIV_FSYS2
 252         str     r1, [r0, r2]
 253
 254         /* MMC4 */
 255         ldr     r1, =0x000f                     /* 800(MPLL) / (15 + 1) */
 256         ldr     r2, =0x0C54C                    @ CLK_DIV_FSYS3
 257         str     r1, [r0, r2]
 258
 259         /* wait ?us */
 260         mov     r1, #0x10000
 261 4:      subs    r1, r1, #1
 262         bne     4b
 263
 264         /*
 265          * CLK_DIV_PERIL0:
 266          *
 267          * UART5_RATIO[20]      8
 268          * UART4_RATIO[16]      8
 269          * UART3_RATIO[12]      8
 270          * UART2_RATIO[8]       8
 271          * UART1_RATIO[4]       8
 272          * UART0_RATIO[0]       8
 273          */
 274         ldr     r1, =0x774777
 275         ldr     r2, =0x0C550                    @CLK_DIV_PERIL0_OFFSET
 276         str     r1, [r0, r2]
 277
 278         /* SLIMBUS: ???, PWM */
 279         ldr     r1, =0x8
 280         ldr     r2, =0x0C55C                    @ CLK_DIV_PERIL3
 281         str     r1, [r0, r2]
 282
 283         /* Set PLL locktime */
 284         ldr     r1, =0x01C20
 285         ldr     r2, =0x014000                   @APLL_LOCK_OFFSET
 286         str     r1, [r0, r2]
 287         ldr     r1, =0x01C20
 288         ldr     r2, =0x014008                   @MPLL_LOCK_OFFSET
 289         str     r1, [r0, r2]
 290         ldr     r1, =0x01C20
 291         ldr     r2, =0x0C010                    @EPLL_LOCK_OFFSET
 292         str     r1, [r0, r2]
 293         ldr     r1, =0x01C20
 294         ldr     r2, =0x0C020                    @VPLL_LOCK_OFFSET
 295         str     r1, [r0, r2]
 296
 297         /*
 298          * APLL_CON1:
 299          *
 300          * APLL_AFC_ENB[31]     0x1
 301          * APLL_AFC[0]          0xC
 302          */
 303         ldr     r1, =0x8000000C
 304         ldr     r2, =0x014104                   @APLL_CON1_OFFSET
 305         str     r1, [r0, r2]
 306
 307         /*
 308          * APLL_CON0:
 309          *
 310          * APLL_MDIV[16]        0xFA
 311          * APLL_PDIV[8]         0x6
 312          * APLL_SDIV[0]         0x1
 313          */
 314         ldr     r1, =0x80FA0601
 315         ldr     r2, =0x014100                   @APLL_CON0_OFFSET
 316         str     r1, [r0, r2]
 317
 318         /*
 319          * MPLL_CON1:
 320          *
 321          * MPLL_AFC_ENB[31]     0x1
 322          * MPLL_AFC[0]          0x1C
 323          */
 324         ldr     r1, =0x0000001C
 325         ldr     r2, =0x01410C                   @MPLL_CON1_OFFSET
 326         str     r1, [r0, r2]
 327
 328         /*
 329          * MPLL_CON0:
 330          *
 331          * MPLL_MDIV[16]        0xC8
 332          * MPLL_PDIV[8]         0x6
 333          * MPLL_SDIV[0]         0x1
 334          */
 335         ldr     r1, =0x80C80601
 336         ldr     r2, =0x014108                   @MPLL_CON0_OFFSET
 337         str     r1, [r0, r2]
 338
 339         /* EPLL */
 340         ldr     r1, =0x0
 341         ldr     r2, =0x0C114                    @EPLL_CON1_OFFSET
 342         str     r1, [r0, r2]
 343
 344         /*
 345          * EPLL_CON0:
 346          *
 347          * EPLL_MDIV[16]        0x30
 348          * EPLL_PDIV[8]         0x3
 349          * EPLL_SDIV[0]         0x2
 350          */
 351         ldr     r1, =0x80300302
 352         ldr     r2, =0x0C110                    @EPLL_CON0_OFFSET
 353         str     r1, [r0, r2]
 354
 355         /*
 356          * VPLL_CON1:
 357          *
 358          * VPLL_MRR[24]         0x11
 359          * VPLL_MFR[16]         0x0
 360          * VPLL_K[0]            0x400
 361          */
 362         ldr     r1, =0x11000400
 363         ldr     r2, =0x0C124                    @VPLL_CON1_OFFSET
 364         str     r1, [r0, r2]
 365
 366         /*
 367          * VPLL_CON0:
 368          *
 369          * VPLL_MDIV[16]        0x35
 370          * VPLL_PDIV[8]         0x3
 371          * VPLL_SDIV[0]         0x2
 372          */
 373         ldr     r1, =0x80350302
 374         ldr     r2, =0x0C120                    @VPLL_CON0_OFFSET
 375         str     r1, [r0, r2]
 376
 377         /* wait ?us */
 378         mov     r1, #0x30000
 379 3:      subs    r1, r1, #1
 380         bne     3b
 381
 382         pop     {pc}
 383 /*
 384  * uart_asm_init: Initialize UART in asm mode, 115200bps fixed.
 385  * void uart_asm_init(void)
 386  */
 387         .globl uart_asm_init
 388 uart_asm_init:
 389
 390         /* setup UART0-UART3 GPIOs (part1) */
 391         mov     r0, r7
 392         ldr     r1, =0x22222222
 393         str     r1, [r0, #0x00]                 @ EXYNOS4_GPIO_A0_OFFSET
 394         ldr     r1, =0x00222222
 395         str     r1, [r0, #0x20]                 @ EXYNOS4_GPIO_A1_OFFSET
 396
 397         ldr r0, =EXYNOS4_UART_BASE
 398         add r0, r0, #EXYNOS4_DEFAULT_UART_OFFSET
 399
 400         ldr r1, =0x3C5
 401         str     r1, [r0, #0x4]
 402         ldr r1, =0x111
 403         str     r1, [r0, #0x8]
 404         ldr r1, =0x3
 405         str     r1, [r0, #0x0]
 406         ldr r1, =0x35
 407         str     r1, [r0, #0x28]
 408         ldr r1, =0x4
 409         str     r1, [r0, #0x2c]
 410
 411         mov     pc, lr
 412         nop
 413         nop
 414         nop