board/samsung/trats/trats.c

   1 /*
   2  * Copyright (C) 2011 Samsung Electronics
   3  * Heungjun Kim <riverful.kim@samsung.com>
   4  * Kyungmin Park <kyungmin.park@samsung.com>
   5  * Donghwa Lee <dh09.lee@samsung.com>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <lcd.h>
  28 #include <asm/io.h>
  29 #include <asm/arch/cpu.h>
  30 #include <asm/arch/gpio.h>
  31 #include <asm/arch/mmc.h>
  32 #include <asm/arch/clock.h>
  33 #include <asm/arch/clk.h>
  34 #include <asm/arch/mipi_dsim.h>
  35 #include <asm/arch/watchdog.h>
  36 #include <asm/arch/power.h>
  37 #include <pmic.h>
  38 #include <usb/s3c_udc.h>
  39 #include <max8997_pmic.h>
  40
  41 #include "setup.h"
  42
  43 DECLARE_GLOBAL_DATA_PTR;
  44
  45 unsigned int board_rev;
  46
  47 #ifdef CONFIG_REVISION_TAG
  48 u32 get_board_rev(void)
  49 {
  50         return board_rev;
  51 }
  52 #endif
  53
  54 static void check_hw_revision(void);
  55
  56 int board_init(void)
  57 {
  58         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  59
  60         check_hw_revision();
  61         printf("HW Revision:\t0x%x\n", board_rev);
  62
  63 #if defined(CONFIG_PMIC)
  64         pmic_init();
  65 #endif
  66
  67         return 0;
  68 }
  69
  70 int dram_init(void)
  71 {
  72         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
  73                 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
  74
  75         return 0;
  76 }
  77
  78 void dram_init_banksize(void)
  79 {
  80         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  81         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  82         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  83         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  84 }
  85
  86 static unsigned int get_hw_revision(void)
  87 {
  88         struct exynos4_gpio_part1 *gpio =
  89                 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
  90         int hwrev = 0;
  91         int i;
  92
  93         /* hw_rev[3:0] == GPE1[3:0] */
  94         for (i = 0; i < 4; i++) {
  95                 s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT);
  96                 s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE);
  97         }
  98
  99         udelay(1);
 100
 101         for (i = 0; i < 4; i++)
 102                 hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i);
 103
 104         debug("hwrev 0x%x\n", hwrev);
 105
 106         return hwrev;
 107 }
 108
 109 static void check_hw_revision(void)
 110 {
 111         int hwrev;
 112
 113         hwrev = get_hw_revision();
 114
 115         board_rev |= hwrev;
 116 }
 117
 118 #ifdef CONFIG_DISPLAY_BOARDINFO
 119 int checkboard(void)
 120 {
 121         puts("Board:\tTRATS\n");
 122         return 0;
 123 }
 124 #endif
 125
 126 #ifdef CONFIG_GENERIC_MMC
 127 int board_mmc_init(bd_t *bis)
 128 {
 129         struct exynos4_gpio_part2 *gpio =
 130                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 131         int i, err;
 132
 133         /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
 134         s5p_gpio_direction_output(&gpio->k0, 2, 1);
 135         s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
 136
 137         /*
 138          * eMMC GPIO:
 139          * SDR 8-bit@48MHz at MMC0
 140          * GPK0[0]      SD_0_CLK(2)
 141          * GPK0[1]      SD_0_CMD(2)
 142          * GPK0[2]      SD_0_CDn        -> Not used
 143          * GPK0[3:6]    SD_0_DATA[0:3](2)
 144          * GPK1[3:6]    SD_0_DATA[0:3](3)
 145          *
 146          * DDR 4-bit@26MHz at MMC4
 147          * GPK0[0]      SD_4_CLK(3)
 148          * GPK0[1]      SD_4_CMD(3)
 149          * GPK0[2]      SD_4_CDn        -> Not used
 150          * GPK0[3:6]    SD_4_DATA[0:3](3)
 151          * GPK1[3:6]    SD_4_DATA[4:7](4)
 152          */
 153         for (i = 0; i < 7; i++) {
 154                 if (i == 2)
 155                         continue;
 156                 /* GPK0[0:6] special function 2 */
 157                 s5p_gpio_cfg_pin(&gpio->k0, i, 0x2);
 158                 /* GPK0[0:6] pull disable */
 159                 s5p_gpio_set_pull(&gpio->k0, i, GPIO_PULL_NONE);
 160                 /* GPK0[0:6] drv 4x */
 161                 s5p_gpio_set_drv(&gpio->k0, i, GPIO_DRV_4X);
 162         }
 163
 164         for (i = 3; i < 7; i++) {
 165                 /* GPK1[3:6] special function 3 */
 166                 s5p_gpio_cfg_pin(&gpio->k1, i, 0x3);
 167                 /* GPK1[3:6] pull disable */
 168                 s5p_gpio_set_pull(&gpio->k1, i, GPIO_PULL_NONE);
 169                 /* GPK1[3:6] drv 4x */
 170                 s5p_gpio_set_drv(&gpio->k1, i, GPIO_DRV_4X);
 171         }
 172
 173         /*
 174          * MMC device init
 175          * mmc0  : eMMC (8-bit buswidth)
 176          * mmc2  : SD card (4-bit buswidth)
 177          */
 178         err = s5p_mmc_init(0, 8);
 179
 180         /* T-flash detect */
 181         s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
 182         s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP);
 183
 184         /*
 185          * Check the T-flash  detect pin
 186          * GPX3[4] T-flash detect pin
 187          */
 188         if (!s5p_gpio_get_value(&gpio->x3, 4)) {
 189                 /*
 190                  * SD card GPIO:
 191                  * GPK2[0]      SD_2_CLK(2)
 192                  * GPK2[1]      SD_2_CMD(2)
 193                  * GPK2[2]      SD_2_CDn        -> Not used
 194                  * GPK2[3:6]    SD_2_DATA[0:3](2)
 195                  */
 196                 for (i = 0; i < 7; i++) {
 197                         if (i == 2)
 198                                 continue;
 199                         /* GPK2[0:6] special function 2 */
 200                         s5p_gpio_cfg_pin(&gpio->k2, i, 0x2);
 201                         /* GPK2[0:6] pull disable */
 202                         s5p_gpio_set_pull(&gpio->k2, i, GPIO_PULL_NONE);
 203                         /* GPK2[0:6] drv 4x */
 204                         s5p_gpio_set_drv(&gpio->k2, i, GPIO_DRV_4X);
 205                 }
 206                 err = s5p_mmc_init(2, 4);
 207         }
 208
 209         return err;
 210 }
 211 #endif
 212
 213 #ifdef CONFIG_USB_GADGET
 214 static int s5pc210_phy_control(int on)
 215 {
 216         int ret = 0;
 217         struct pmic *p = get_pmic();
 218
 219         if (pmic_probe(p))
 220                 return -1;
 221
 222         if (on) {
 223                 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
 224                                       ENSAFEOUT1, LDO_ON);
 225                 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO);
 226                 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO);
 227         } else {
 228                 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO);
 229                 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO);
 230                 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
 231                                       ENSAFEOUT1, LDO_OFF);
 232         }
 233
 234         if (ret) {
 235                 puts("MAX8997 LDO setting error!\n");
 236                 return -1;
 237         }
 238
 239         return 0;
 240 }
 241
 242 struct s3c_plat_otg_data s5pc210_otg_data = {
 243         .phy_control    = s5pc210_phy_control,
 244         .regs_phy       = EXYNOS4_USBPHY_BASE,
 245         .regs_otg       = EXYNOS4_USBOTG_BASE,
 246         .usb_phy_ctrl   = EXYNOS4_USBPHY_CONTROL,
 247         .usb_flags      = PHY0_SLEEP,
 248 };
 249 #endif
 250
 251 static void pmic_reset(void)
 252 {
 253         struct exynos4_gpio_part2 *gpio =
 254                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 255
 256         s5p_gpio_direction_output(&gpio->x0, 7, 1);
 257         s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE);
 258 }
 259
 260 static void board_clock_init(void)
 261 {
 262         struct exynos4_clock *clk =
 263                 (struct exynos4_clock *)samsung_get_base_clock();
 264
 265         writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
 266         writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
 267         writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
 268         writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
 269
 270         writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
 271         writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
 272         writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
 273         writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
 274         writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
 275         writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
 276         writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
 277         writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
 278         writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
 279         writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
 280         writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
 281         writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
 282
 283         writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
 284         writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
 285         writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
 286         writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
 287         writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
 288         writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
 289         writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
 290         writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
 291         writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
 292         writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
 293         writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
 294         writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
 295
 296         writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
 297         writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
 298         writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
 299         writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
 300         writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
 301         writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
 302         writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
 303         writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
 304         writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
 305         writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
 306         writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
 307         writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
 308 }
 309
 310 static void board_power_init(void)
 311 {
 312         struct exynos4_power *pwr =
 313                 (struct exynos4_power *)samsung_get_base_power();
 314
 315         /* PS HOLD */
 316         writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
 317
 318         /* Set power down */
 319         writel(0, (unsigned int)&pwr->cam_configuration);
 320         writel(0, (unsigned int)&pwr->tv_configuration);
 321         writel(0, (unsigned int)&pwr->mfc_configuration);
 322         writel(0, (unsigned int)&pwr->g3d_configuration);
 323         writel(0, (unsigned int)&pwr->lcd1_configuration);
 324         writel(0, (unsigned int)&pwr->gps_configuration);
 325         writel(0, (unsigned int)&pwr->gps_alive_configuration);
 326 }
 327
 328 static void board_uart_init(void)
 329 {
 330         struct exynos4_gpio_part1 *gpio1 =
 331                 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
 332         struct exynos4_gpio_part2 *gpio2 =
 333                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 334         int i;
 335
 336         /*
 337          * UART2 GPIOs
 338          * GPA1CON[0] = UART_2_RXD(2)
 339          * GPA1CON[1] = UART_2_TXD(2)
 340          * GPA1CON[2] = I2C_3_SDA (3)
 341          * GPA1CON[3] = I2C_3_SCL (3)
 342          */
 343
 344         for (i = 0; i < 4; i++) {
 345                 s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
 346                 s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2));
 347         }
 348
 349         /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
 350         s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP);
 351         s5p_gpio_direction_output(&gpio2->y4, 7, 1);
 352 }
 353
 354 int board_early_init_f(void)
 355 {
 356         wdt_stop();
 357         pmic_reset();
 358         board_clock_init();
 359         board_uart_init();
 360         board_power_init();
 361
 362         return 0;
 363 }
 364
 365 static void lcd_reset(void)
 366 {
 367         struct exynos4_gpio_part2 *gpio2 =
 368                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 369
 370         s5p_gpio_direction_output(&gpio2->y4, 5, 1);
 371         udelay(10000);
 372         s5p_gpio_direction_output(&gpio2->y4, 5, 0);
 373         udelay(10000);
 374         s5p_gpio_direction_output(&gpio2->y4, 5, 1);
 375 }
 376
 377 static int lcd_power(void)
 378 {
 379         int ret = 0;
 380         struct pmic *p = get_pmic();
 381
 382         if (pmic_probe(p))
 383                 return 0;
 384
 385         /* LDO15 voltage: 2.2v */
 386         ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
 387         /* LDO13 voltage: 3.0v */
 388         ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
 389
 390         if (ret) {
 391                 puts("MAX8997 LDO setting error!\n");
 392                 return -1;
 393         }
 394
 395         return 0;
 396 }
 397
 398 static struct mipi_dsim_config dsim_config = {
 399         .e_interface            = DSIM_VIDEO,
 400         .e_virtual_ch           = DSIM_VIRTUAL_CH_0,
 401         .e_pixel_format         = DSIM_24BPP_888,
 402         .e_burst_mode           = DSIM_BURST_SYNC_EVENT,
 403         .e_no_data_lane         = DSIM_DATA_LANE_4,
 404         .e_byte_clk             = DSIM_PLL_OUT_DIV8,
 405         .hfp                    = 1,
 406
 407         .p                      = 3,
 408         .m                      = 120,
 409         .s                      = 1,
 410
 411         /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
 412         .pll_stable_time        = 500,
 413
 414         /* escape clk : 10MHz */
 415         .esc_clk                = 20 * 1000000,
 416
 417         /* stop state holding counter after bta change count 0 ~ 0xfff */
 418         .stop_holding_cnt       = 0x7ff,
 419         /* bta timeout 0 ~ 0xff */
 420         .bta_timeout            = 0xff,
 421         /* lp rx timeout 0 ~ 0xffff */
 422         .rx_timeout             = 0xffff,
 423 };
 424
 425 static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = {
 426         .lcd_panel_info = NULL,
 427         .dsim_config = &dsim_config,
 428 };
 429
 430 static struct mipi_dsim_lcd_device mipi_lcd_device = {
 431         .name   = "s6e8ax0",
 432         .id     = -1,
 433         .bus_id = 0,
 434         .platform_data  = (void *)&s6e8ax0_platform_data,
 435 };
 436
 437 static int mipi_power(void)
 438 {
 439         int ret = 0;
 440         struct pmic *p = get_pmic();
 441
 442         if (pmic_probe(p))
 443                 return 0;
 444
 445         /* LDO3 voltage: 1.1v */
 446         ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
 447         /* LDO4 voltage: 1.8v */
 448         ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
 449
 450         if (ret) {
 451                 puts("MAX8997 LDO setting error!\n");
 452                 return -1;
 453         }
 454
 455         return 0;
 456 }
 457
 458 void init_panel_info(vidinfo_t *vid)
 459 {
 460         vid->vl_freq    = 60;
 461         vid->vl_col     = 720;
 462         vid->vl_row     = 1280;
 463         vid->vl_width   = 720;
 464         vid->vl_height  = 1280;
 465         vid->vl_clkp    = CONFIG_SYS_HIGH;
 466         vid->vl_hsp     = CONFIG_SYS_LOW;
 467         vid->vl_vsp     = CONFIG_SYS_LOW;
 468         vid->vl_dp      = CONFIG_SYS_LOW;
 469
 470         vid->vl_bpix    = 5;
 471         vid->dual_lcd_enabled = 0;
 472
 473         /* s6e8ax0 Panel */
 474         vid->vl_hspw    = 5;
 475         vid->vl_hbpd    = 10;
 476         vid->vl_hfpd    = 10;
 477
 478         vid->vl_vspw    = 2;
 479         vid->vl_vbpd    = 1;
 480         vid->vl_vfpd    = 13;
 481         vid->vl_cmd_allow_len = 0xf;
 482
 483         vid->win_id = 3;
 484         vid->cfg_gpio = NULL;
 485         vid->backlight_on = NULL;
 486         vid->lcd_power_on = NULL;       /* lcd_power_on in mipi dsi driver */
 487         vid->reset_lcd = lcd_reset;
 488
 489         vid->init_delay = 0;
 490         vid->power_on_delay = 0;
 491         vid->reset_delay = 0;
 492         vid->interface_mode = FIMD_RGB_INTERFACE;
 493         vid->mipi_enabled = 1;
 494
 495         strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name);
 496         s6e8ax0_platform_data.lcd_power = lcd_power;
 497         s6e8ax0_platform_data.mipi_power = mipi_power;
 498         s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl;
 499         s6e8ax0_platform_data.lcd_panel_info = (void *)vid;
 500         exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device);
 501         s6e8ax0_init();
 502         exynos_set_dsim_platform_data(&s6e8ax0_platform_data);
 503
 504         setenv("lcdinfo", "lcd=s6e8ax0");
 505 }