board/sandburst/karef/karef.c

   1 /*
   2  *  Copyright (C) 2005 Sandburst Corporation
   3  *  Travis B. Sawyer
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <config.h>
   9 #include <common.h>
  10 #include <command.h>
  11 #include "karef.h"
  12 #include "karef_version.h"
  13 #include <timestamp.h>
  14 #include <asm/processor.h>
  15 #include <asm/io.h>
  16 #include <spd_sdram.h>
  17 #include <i2c.h>
  18 #include "../common/sb_common.h"
  19 #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) || \
  20     defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
  21 #include <net.h>
  22 #endif
  23
  24 void fpga_init (void);
  25
  26 KAREF_BOARD_ID_ST board_id_as[] =
  27 {
  28         {"Undefined"},                       /* Not specified */
  29         {"Kamino Reference Design"},
  30         {"Reserved"},                        /* Reserved for future use */
  31         {"Reserved"},                        /* Reserved for future use */
  32 };
  33
  34 KAREF_BOARD_ID_ST ofem_board_id_as[] =
  35 {
  36         {"Undefined"},
  37         {"1x10 + 10x2"},
  38         {"Reserved"},
  39         {"Reserved"},
  40 };
  41
  42 /*************************************************************************
  43  *  board_early_init_f
  44  *
  45  *  Setup chip selects, initialize the Opto-FPGA, initialize
  46  *  interrupt polarity and triggers.
  47  ************************************************************************/
  48 int board_early_init_f (void)
  49 {
  50         ppc440_gpio_regs_t *gpio_regs;
  51
  52         /* Enable GPIO interrupts */
  53         mtsdr(SDR0_PFC0, 0x00103E00);
  54
  55         /* Setup access for LEDs, and system topology info */
  56         gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
  57         gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
  58         gpio_regs->tri_state  = SBCOMMON_GPIO_DBGLEDS;
  59
  60         /* Turn on all the leds for now */
  61         gpio_regs->out = SBCOMMON_GPIO_LEDS;
  62
  63         /*--------------------------------------------------------------------+
  64           | Initialize EBC CONFIG
  65           +-------------------------------------------------------------------*/
  66         mtebc(EBC0_CFG,
  67               EBC_CFG_LE_UNLOCK    | EBC_CFG_PTD_ENABLE |
  68               EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
  69               EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
  70               EBC_CFG_EMC_DEFAULT  | EBC_CFG_PME_DISABLE |
  71               EBC_CFG_PR_32);
  72
  73         /*--------------------------------------------------------------------+
  74           | 1/2 MB FLASH. Initialize bank 0 with default values.
  75           +-------------------------------------------------------------------*/
  76         mtebc(PB0AP,
  77               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
  78               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
  79               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
  80               EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
  81               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
  82               EBC_BXAP_PEN_DISABLED);
  83
  84         mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
  85               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
  86         /*--------------------------------------------------------------------+
  87           | 8KB NVRAM/RTC. Initialize bank 1 with default values.
  88           +-------------------------------------------------------------------*/
  89         mtebc(PB1AP,
  90               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
  91               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
  92               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
  93               EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
  94               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
  95               EBC_BXAP_PEN_DISABLED);
  96
  97         mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000) |
  98               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
  99
 100         /*--------------------------------------------------------------------+
 101           | Compact Flash, uses 2 Chip Selects (2 & 6)
 102           +-------------------------------------------------------------------*/
 103         mtebc(PB2AP,
 104               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
 105               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
 106               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
 107               EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
 108               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
 109               EBC_BXAP_PEN_DISABLED);
 110
 111         mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0xF0000000) |
 112               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
 113
 114         /*--------------------------------------------------------------------+
 115           | KaRef Scan FPGA. Initialize bank 3 with default values.
 116           +-------------------------------------------------------------------*/
 117         mtebc(PB5AP,
 118               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 119               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 120               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 121               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 122               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 123
 124         mtebc(PB5CR, EBC_BXCR_BAS_ENCODE(0x48200000) |
 125               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 126
 127         /*--------------------------------------------------------------------+
 128           | MAC A & B for Kamino.  OFEM FPGA decodes the addresses
 129           | Initialize bank 4 with default values.
 130           +-------------------------------------------------------------------*/
 131         mtebc(PB4AP,
 132               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 133               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 134               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 135               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 136               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 137
 138         mtebc(PB4CR, EBC_BXCR_BAS_ENCODE(0x48600000) |
 139               EBC_BXCR_BS_2MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 140
 141         /*--------------------------------------------------------------------+
 142           | OFEM FPGA  Initialize bank 5 with default values.
 143           +-------------------------------------------------------------------*/
 144         mtebc(PB3AP,
 145               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 146               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 147               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 148               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 149               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 150
 151
 152         mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48400000) |
 153               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 154
 155
 156         /*--------------------------------------------------------------------+
 157           | Compact Flash, uses 2 Chip Selects (2 & 6)
 158           +-------------------------------------------------------------------*/
 159         mtebc(PB6AP,
 160               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
 161               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
 162               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
 163               EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
 164               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
 165               EBC_BXAP_PEN_DISABLED);
 166
 167         mtebc(PB6CR, EBC_BXCR_BAS_ENCODE(0xF0100000) |
 168               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
 169
 170         /*--------------------------------------------------------------------+
 171           | BME-32. Initialize bank 7 with default values.
 172           +-------------------------------------------------------------------*/
 173         mtebc(PB7AP,
 174               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 175               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 176               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 177               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 178               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 179
 180         mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48500000) |
 181               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 182
 183         /*--------------------------------------------------------------------+
 184          * Setup the interrupt controller polarities, triggers, etc.
 185          +-------------------------------------------------------------------*/
 186         /*
 187          * Because of the interrupt handling rework to handle 440GX interrupts
 188          * with the common code, we needed to change names of the UIC registers.
 189          * Here the new relationship:
 190          *
 191          * U-Boot name  440GX name
 192          * -----------------------
 193          * UIC0         UICB0
 194          * UIC1         UIC0
 195          * UIC2         UIC1
 196          * UIC3         UIC2
 197          */
 198         mtdcr (UIC1SR, 0xffffffff);     /* clear all */
 199         mtdcr (UIC1ER, 0x00000000);     /* disable all */
 200         mtdcr (UIC1CR, 0x00000000);     /* all non- critical */
 201         mtdcr (UIC1PR, 0xfffffe03);     /* polarity */
 202         mtdcr (UIC1TR, 0x01c00000);     /* trigger edge vs level */
 203         mtdcr (UIC1VR, 0x00000001);     /* int31 highest, base=0x000 */
 204         mtdcr (UIC1SR, 0xffffffff);     /* clear all */
 205
 206         mtdcr (UIC2SR, 0xffffffff);     /* clear all */
 207         mtdcr (UIC2ER, 0x00000000);     /* disable all */
 208         mtdcr (UIC2CR, 0x00000000);     /* all non-critical */
 209         mtdcr (UIC2PR, 0xffffc8ff);     /* polarity */
 210         mtdcr (UIC2TR, 0x00ff0000);     /* trigger edge vs level */
 211         mtdcr (UIC2VR, 0x00000001);     /* int31 highest, base=0x000 */
 212         mtdcr (UIC2SR, 0xffffffff);     /* clear all */
 213
 214         mtdcr (UIC3SR, 0xffffffff);     /* clear all */
 215         mtdcr (UIC3ER, 0x00000000);     /* disable all */
 216         mtdcr (UIC3CR, 0x00000000);     /* all non-critical */
 217         mtdcr (UIC3PR, 0xffff83ff);     /* polarity */
 218         mtdcr (UIC3TR, 0x00ff8c0f);     /* trigger edge vs level */
 219         mtdcr (UIC3VR, 0x00000001);     /* int31 highest, base=0x000 */
 220         mtdcr (UIC3SR, 0xffffffff);     /* clear all */
 221
 222         mtdcr (UIC0SR, 0xfc000000);     /* clear all */
 223         mtdcr (UIC0ER, 0x00000000);     /* disable all */
 224         mtdcr (UIC0CR, 0x00000000);     /* all non-critical */
 225         mtdcr (UIC0PR, 0xfc000000);
 226         mtdcr (UIC0TR, 0x00000000);
 227         mtdcr (UIC0VR, 0x00000001);
 228
 229         fpga_init();
 230
 231         return 0;
 232 }
 233
 234
 235 /*************************************************************************
 236  *  checkboard
 237  *
 238  *  Dump pertinent info to the console
 239  ************************************************************************/
 240 int checkboard (void)
 241 {
 242         sys_info_t sysinfo;
 243         unsigned char brd_rev, brd_id;
 244         unsigned short sernum;
 245         unsigned char scan_rev, scan_id, ofem_rev=0, ofem_id=0;
 246         unsigned char ofem_brd_rev, ofem_brd_id;
 247         KAREF_FPGA_REGS_ST *karef_ps;
 248         OFEM_FPGA_REGS_ST *ofem_ps;
 249
 250         karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
 251         ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
 252
 253         scan_id = (unsigned char)((karef_ps->revision_ul &
 254                                    SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK)
 255                                   >> SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT);
 256
 257         scan_rev = (unsigned char)((karef_ps->revision_ul & SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK)
 258                                    >> SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT);
 259
 260         brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK)
 261                                   >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT);
 262
 263         brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK)
 264                                  >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT);
 265
 266         ofem_brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
 267                                       >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
 268
 269         ofem_brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK)
 270                                        >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT);
 271
 272         if (0xF != ofem_brd_id) {
 273                 ofem_id = (unsigned char)((ofem_ps->revision_ul &
 274                                            SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK)
 275                                           >> SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT);
 276
 277                 ofem_rev = (unsigned char)((ofem_ps->revision_ul &
 278                                             SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK)
 279                                            >> SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT);
 280         }
 281
 282         get_sys_info (&sysinfo);
 283
 284         sernum = sbcommon_get_serial_number();
 285
 286         printf ("Board: Sandburst Corporation Kamino Reference Design "
 287                 "Serial Number: %d\n", sernum);
 288         printf ("%s\n", KAREF_U_BOOT_REL_STR);
 289
 290         printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
 291         if (sbcommon_get_master()) {
 292                 printf("Slot 0 - Master\nSlave board");
 293                 if (sbcommon_secondary_present())
 294                         printf(" present\n");
 295                 else
 296                         printf(" not detected\n");
 297         } else {
 298                 printf("Slot 1 - Slave\n\n");
 299         }
 300
 301         printf ("ScanFPGA ID:\t0x%02X\tRev:  0x%02X\n", scan_id, scan_rev);
 302         printf ("Board Rev:\t0x%02X\tID:   0x%02X\n", brd_rev, brd_id);
 303         if(0xF != ofem_brd_id) {
 304                 printf("OFemFPGA ID:\t0x%02X\tRev:  0x%02X\n", ofem_id, ofem_rev);
 305                 printf("OFEM Board Rev:\t0x%02X\tID:   0x%02X\n", ofem_brd_id, ofem_brd_rev);
 306         }
 307
 308         /* Fix the ack in the bme 32 */
 309         udelay(5000);
 310         out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001);
 311         asm("eieio");
 312
 313
 314         return (0);
 315 }
 316
 317 /*************************************************************************
 318  *  misc_init_f
 319  *
 320  *  Initialize I2C bus one to gain access to the fans
 321  ************************************************************************/
 322 int misc_init_f (void)
 323 {
 324         /* Turn on fans 3 & 4 */
 325         sbcommon_fans();
 326
 327         return (0);
 328 }
 329
 330 /*************************************************************************
 331  *  misc_init_r
 332  *
 333  *  Do nothing.
 334  ************************************************************************/
 335 int misc_init_r (void)
 336 {
 337         unsigned short sernum;
 338         char envstr[255];
 339         uchar enetaddr[6];
 340         KAREF_FPGA_REGS_ST *karef_ps;
 341         OFEM_FPGA_REGS_ST *ofem_ps;
 342
 343         if(NULL != getenv("secondserial")) {
 344                 puts("secondserial is set, switching to second serial port\n");
 345                 setenv("stderr", "serial1");
 346                 setenv("stdout", "serial1");
 347                 setenv("stdin", "serial1");
 348         }
 349
 350         setenv("ubrelver", KAREF_U_BOOT_REL_STR);
 351
 352         memset(envstr, 0, 255);
 353         sprintf (envstr, "Built %s %s by %s",
 354                  U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
 355         setenv("bldstr", envstr);
 356         saveenv();
 357
 358         if( getenv("autorecover")) {
 359                 setenv("autorecover", NULL);
 360                 saveenv();
 361                 sernum = sbcommon_get_serial_number();
 362
 363                 printf("\nSetting up environment for automatic filesystem recovery\n");
 364                 /*
 365                  * Setup default bootargs
 366                  */
 367                 memset(envstr, 0, 255);
 368
 369                 sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
 370                         "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
 371                         sernum, sernum);
 372                 setenv("bootargs", envstr);
 373
 374                 /*
 375                  * Setup Default boot command
 376                  */
 377                 setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
 378                        "fatload ide 0 8100000 pramdisk;"
 379                        "bootm 8000000 8100000");
 380
 381                 printf("Done.  Please type allow the system to continue to boot\n");
 382         }
 383
 384         if( getenv("fakeled")) {
 385                 karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
 386                 ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
 387                 ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK;
 388                 karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK;
 389                 setenv("bootdelay", "-1");
 390                 saveenv();
 391                 printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
 392         }
 393
 394 #ifdef CONFIG_HAS_ETH0
 395         if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
 396                 board_get_enetaddr(0, enetaddr);
 397                 eth_setenv_enetaddr("ethaddr", enetaddr);
 398         }
 399 #endif
 400
 401 #ifdef CONFIG_HAS_ETH1
 402         if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
 403                 board_get_enetaddr(1, enetaddr);
 404                 eth_setenv_enetaddr("eth1addr", enetaddr);
 405         }
 406 #endif
 407
 408 #ifdef CONFIG_HAS_ETH2
 409         if (!eth_getenv_enetaddr("eth2addr", enetaddr)) {
 410                 board_get_enetaddr(2, enetaddr);
 411                 eth_setenv_enetaddr("eth2addr", enetaddr);
 412         }
 413 #endif
 414
 415 #ifdef CONFIG_HAS_ETH3
 416         if (!eth_getenv_enetaddr("eth3addr", enetaddr)) {
 417                 board_get_enetaddr(3, enetaddr);
 418                 eth_setenv_enetaddr("eth3addr", enetaddr);
 419         }
 420 #endif
 421
 422         return (0);
 423 }
 424
 425 /*************************************************************************
 426  *  ide_set_reset
 427  ************************************************************************/
 428 #ifdef CONFIG_IDE_RESET
 429 void ide_set_reset(int on)
 430 {
 431         KAREF_FPGA_REGS_ST *karef_ps;
 432         /* TODO: ide reset */
 433         karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
 434
 435         if (on) {
 436                 karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
 437         } else {
 438                 karef_ps->reset_ul |= SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
 439         }
 440 }
 441 #endif /* CONFIG_IDE_RESET */
 442
 443 /*************************************************************************
 444  *  fpga_init
 445  ************************************************************************/
 446 void fpga_init(void)
 447 {
 448         KAREF_FPGA_REGS_ST *karef_ps;
 449         OFEM_FPGA_REGS_ST *ofem_ps;
 450         unsigned char ofem_id;
 451         unsigned long tmp;
 452
 453         /* Ensure we have power all around */
 454         udelay(500);
 455
 456         karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
 457         tmp =
 458                 SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK |
 459                 SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK |
 460                 SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK |
 461                 SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK |
 462                 SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK |
 463                 SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK |
 464                 SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK |
 465                 SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK |
 466                 SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK;
 467
 468         karef_ps->reset_ul = tmp;
 469
 470         /*
 471          * Wait a bit to allow the ofem fpga to get its brains
 472          */
 473         udelay(5000);
 474
 475         /*
 476          * Check to see if the ofem is there
 477          */
 478         ofem_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
 479                                   >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
 480         if(0xF != ofem_id) {
 481                 tmp =
 482                         SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK |
 483                         SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK |
 484                         SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK;
 485
 486                 ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
 487                 ofem_ps->reset_ul = tmp;
 488
 489                 ofem_ps->control_ul |= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT;
 490         }
 491
 492         karef_ps->control_ul |= 1 << SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT;
 493
 494         asm("eieio");
 495
 496         return;
 497 }
 498
 499 int karefSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 500 {
 501         unsigned short sernum;
 502         char envstr[255];
 503
 504         sernum = sbcommon_get_serial_number();
 505
 506         memset(envstr, 0, 255);
 507         /*
 508          * Setup our ip address
 509          */
 510         sprintf(envstr, "10.100.70.%d", sernum);
 511
 512         setenv("ipaddr", envstr);
 513         /*
 514          * Setup the host ip address
 515          */
 516         setenv("serverip", "10.100.17.10");
 517
 518         /*
 519          * Setup default bootargs
 520          */
 521         memset(envstr, 0, 255);
 522
 523         sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
 524                 "rw nfsroot=10.100.17.10:/home/metrobox/mbc70.%d "
 525                 "nfsaddrs=10.100.70.%d:10.100.17.10:10.100.1.1:"
 526                 "255.255.0.0:karef%d.sandburst.com:eth0:none idebus=33",
 527                 sernum, sernum, sernum);
 528
 529         setenv("bootargs_nfs", envstr);
 530         setenv("bootargs", envstr);
 531
 532         /*
 533          * Setup CF bootargs
 534          */
 535         memset(envstr, 0, 255);
 536
 537         sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
 538                 "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
 539                 sernum, sernum);
 540
 541         setenv("bootargs_cf", envstr);
 542
 543         /*
 544          * Setup Default boot command
 545          */
 546         setenv("bootcmd_tftp", "tftp 8000000 uImage.karef;bootm 8000000");
 547         setenv("bootcmd", "tftp 8000000 uImage.karef;bootm 8000000");
 548
 549         /*
 550          * Setup compact flash boot command
 551          */
 552         setenv("bootcmd_cf", "fatload ide 0 8000000 uimage.karef;bootm 8000000");
 553
 554         saveenv();
 555
 556         return(1);
 557 }
 558
 559 int karefRecover(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 560 {
 561         unsigned short sernum;
 562         char envstr[255];
 563
 564         sernum = sbcommon_get_serial_number();
 565
 566         printf("\nSetting up environment for filesystem recovery\n");
 567         /*
 568          * Setup default bootargs
 569          */
 570         memset(envstr, 0, 255);
 571
 572         sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
 573                 "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none",
 574                 sernum, sernum);
 575         setenv("bootargs", envstr);
 576
 577         /*
 578          * Setup Default boot command
 579          */
 580
 581         setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
 582                "fatload ide 0 8100000 pramdisk;"
 583                "bootm 8000000 8100000");
 584
 585         printf("Done.  Please type boot<cr>.\nWhen the kernel has booted"
 586                " please type fsrecover.sh<cr>\n");
 587
 588         return(1);
 589 }
 590
 591 U_BOOT_CMD(kasetup, 1, 1, karefSetupVars,
 592            "Set environment to factory defaults", "");
 593
 594 U_BOOT_CMD(karecover, 1, 1, karefRecover,
 595            "Set environment to allow for fs recovery", "");