board/sandburst/karef/karef.c

   1 /*
   2  *  Copyright (C) 2005 Sandburst Corporation
   3  *  Travis B. Sawyer
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <config.h>
  25 #include <common.h>
  26 #include <command.h>
  27 #include "karef.h"
  28 #include "karef_version.h"
  29 #include <timestamp.h>
  30 #include <asm/processor.h>
  31 #include <asm/io.h>
  32 #include <spd_sdram.h>
  33 #include <i2c.h>
  34 #include "../common/sb_common.h"
  35 #include "../common/ppc440gx_i2c.h"
  36 #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) || \
  37     defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
  38 #include <net.h>
  39 #endif
  40
  41 void fpga_init (void);
  42
  43 KAREF_BOARD_ID_ST board_id_as[] =
  44 {
  45         {"Undefined"},                       /* Not specified */
  46         {"Kamino Reference Design"},
  47         {"Reserved"},                        /* Reserved for future use */
  48         {"Reserved"},                        /* Reserved for future use */
  49 };
  50
  51 KAREF_BOARD_ID_ST ofem_board_id_as[] =
  52 {
  53         {"Undefined"},
  54         {"1x10 + 10x2"},
  55         {"Reserved"},
  56         {"Reserved"},
  57 };
  58
  59 /*************************************************************************
  60  *  board_early_init_f
  61  *
  62  *  Setup chip selects, initialize the Opto-FPGA, initialize
  63  *  interrupt polarity and triggers.
  64  ************************************************************************/
  65 int board_early_init_f (void)
  66 {
  67         ppc440_gpio_regs_t *gpio_regs;
  68
  69         /* Enable GPIO interrupts */
  70         mtsdr(SDR0_PFC0, 0x00103E00);
  71
  72         /* Setup access for LEDs, and system topology info */
  73         gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
  74         gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
  75         gpio_regs->tri_state  = SBCOMMON_GPIO_DBGLEDS;
  76
  77         /* Turn on all the leds for now */
  78         gpio_regs->out = SBCOMMON_GPIO_LEDS;
  79
  80         /*--------------------------------------------------------------------+
  81           | Initialize EBC CONFIG
  82           +-------------------------------------------------------------------*/
  83         mtebc(EBC0_CFG,
  84               EBC_CFG_LE_UNLOCK    | EBC_CFG_PTD_ENABLE |
  85               EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
  86               EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
  87               EBC_CFG_EMC_DEFAULT  | EBC_CFG_PME_DISABLE |
  88               EBC_CFG_PR_32);
  89
  90         /*--------------------------------------------------------------------+
  91           | 1/2 MB FLASH. Initialize bank 0 with default values.
  92           +-------------------------------------------------------------------*/
  93         mtebc(PB0AP,
  94               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
  95               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
  96               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
  97               EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
  98               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
  99               EBC_BXAP_PEN_DISABLED);
 100
 101         mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
 102               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
 103         /*--------------------------------------------------------------------+
 104           | 8KB NVRAM/RTC. Initialize bank 1 with default values.
 105           +-------------------------------------------------------------------*/
 106         mtebc(PB1AP,
 107               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
 108               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
 109               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
 110               EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
 111               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
 112               EBC_BXAP_PEN_DISABLED);
 113
 114         mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000) |
 115               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
 116
 117         /*--------------------------------------------------------------------+
 118           | Compact Flash, uses 2 Chip Selects (2 & 6)
 119           +-------------------------------------------------------------------*/
 120         mtebc(PB2AP,
 121               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
 122               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
 123               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
 124               EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
 125               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
 126               EBC_BXAP_PEN_DISABLED);
 127
 128         mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0xF0000000) |
 129               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
 130
 131         /*--------------------------------------------------------------------+
 132           | KaRef Scan FPGA. Initialize bank 3 with default values.
 133           +-------------------------------------------------------------------*/
 134         mtebc(PB5AP,
 135               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 136               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 137               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 138               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 139               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 140
 141         mtebc(PB5CR, EBC_BXCR_BAS_ENCODE(0x48200000) |
 142               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 143
 144         /*--------------------------------------------------------------------+
 145           | MAC A & B for Kamino.  OFEM FPGA decodes the addresses
 146           | Initialize bank 4 with default values.
 147           +-------------------------------------------------------------------*/
 148         mtebc(PB4AP,
 149               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 150               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 151               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 152               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 153               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 154
 155         mtebc(PB4CR, EBC_BXCR_BAS_ENCODE(0x48600000) |
 156               EBC_BXCR_BS_2MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 157
 158         /*--------------------------------------------------------------------+
 159           | OFEM FPGA  Initialize bank 5 with default values.
 160           +-------------------------------------------------------------------*/
 161         mtebc(PB3AP,
 162               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 163               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 164               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 165               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 166               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 167
 168
 169         mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48400000) |
 170               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 171
 172
 173         /*--------------------------------------------------------------------+
 174           | Compact Flash, uses 2 Chip Selects (2 & 6)
 175           +-------------------------------------------------------------------*/
 176         mtebc(PB6AP,
 177               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
 178               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
 179               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
 180               EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
 181               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
 182               EBC_BXAP_PEN_DISABLED);
 183
 184         mtebc(PB6CR, EBC_BXCR_BAS_ENCODE(0xF0100000) |
 185               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
 186
 187         /*--------------------------------------------------------------------+
 188           | BME-32. Initialize bank 7 with default values.
 189           +-------------------------------------------------------------------*/
 190         mtebc(PB7AP,
 191               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 192               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 193               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 194               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 195               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 196
 197         mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48500000) |
 198               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 199
 200         /*--------------------------------------------------------------------+
 201          * Setup the interrupt controller polarities, triggers, etc.
 202          +-------------------------------------------------------------------*/
 203         /*
 204          * Because of the interrupt handling rework to handle 440GX interrupts
 205          * with the common code, we needed to change names of the UIC registers.
 206          * Here the new relationship:
 207          *
 208          * U-Boot name  440GX name
 209          * -----------------------
 210          * UIC0         UICB0
 211          * UIC1         UIC0
 212          * UIC2         UIC1
 213          * UIC3         UIC2
 214          */
 215         mtdcr (UIC1SR, 0xffffffff);     /* clear all */
 216         mtdcr (UIC1ER, 0x00000000);     /* disable all */
 217         mtdcr (UIC1CR, 0x00000000);     /* all non- critical */
 218         mtdcr (UIC1PR, 0xfffffe03);     /* polarity */
 219         mtdcr (UIC1TR, 0x01c00000);     /* trigger edge vs level */
 220         mtdcr (UIC1VR, 0x00000001);     /* int31 highest, base=0x000 */
 221         mtdcr (UIC1SR, 0xffffffff);     /* clear all */
 222
 223         mtdcr (UIC2SR, 0xffffffff);     /* clear all */
 224         mtdcr (UIC2ER, 0x00000000);     /* disable all */
 225         mtdcr (UIC2CR, 0x00000000);     /* all non-critical */
 226         mtdcr (UIC2PR, 0xffffc8ff);     /* polarity */
 227         mtdcr (UIC2TR, 0x00ff0000);     /* trigger edge vs level */
 228         mtdcr (UIC2VR, 0x00000001);     /* int31 highest, base=0x000 */
 229         mtdcr (UIC2SR, 0xffffffff);     /* clear all */
 230
 231         mtdcr (UIC3SR, 0xffffffff);     /* clear all */
 232         mtdcr (UIC3ER, 0x00000000);     /* disable all */
 233         mtdcr (UIC3CR, 0x00000000);     /* all non-critical */
 234         mtdcr (UIC3PR, 0xffff83ff);     /* polarity */
 235         mtdcr (UIC3TR, 0x00ff8c0f);     /* trigger edge vs level */
 236         mtdcr (UIC3VR, 0x00000001);     /* int31 highest, base=0x000 */
 237         mtdcr (UIC3SR, 0xffffffff);     /* clear all */
 238
 239         mtdcr (UIC0SR, 0xfc000000);     /* clear all */
 240         mtdcr (UIC0ER, 0x00000000);     /* disable all */
 241         mtdcr (UIC0CR, 0x00000000);     /* all non-critical */
 242         mtdcr (UIC0PR, 0xfc000000);
 243         mtdcr (UIC0TR, 0x00000000);
 244         mtdcr (UIC0VR, 0x00000001);
 245
 246         fpga_init();
 247
 248         return 0;
 249 }
 250
 251
 252 /*************************************************************************
 253  *  checkboard
 254  *
 255  *  Dump pertinent info to the console
 256  ************************************************************************/
 257 int checkboard (void)
 258 {
 259         sys_info_t sysinfo;
 260         unsigned char brd_rev, brd_id;
 261         unsigned short sernum;
 262         unsigned char scan_rev, scan_id, ofem_rev=0, ofem_id=0;
 263         unsigned char ofem_brd_rev, ofem_brd_id;
 264         KAREF_FPGA_REGS_ST *karef_ps;
 265         OFEM_FPGA_REGS_ST *ofem_ps;
 266
 267         karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
 268         ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
 269
 270         scan_id = (unsigned char)((karef_ps->revision_ul &
 271                                    SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK)
 272                                   >> SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT);
 273
 274         scan_rev = (unsigned char)((karef_ps->revision_ul & SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK)
 275                                    >> SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT);
 276
 277         brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK)
 278                                   >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT);
 279
 280         brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK)
 281                                  >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT);
 282
 283         ofem_brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
 284                                       >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
 285
 286         ofem_brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK)
 287                                        >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT);
 288
 289         if (0xF != ofem_brd_id) {
 290                 ofem_id = (unsigned char)((ofem_ps->revision_ul &
 291                                            SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK)
 292                                           >> SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT);
 293
 294                 ofem_rev = (unsigned char)((ofem_ps->revision_ul &
 295                                             SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK)
 296                                            >> SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT);
 297         }
 298
 299         get_sys_info (&sysinfo);
 300
 301         sernum = sbcommon_get_serial_number();
 302
 303         printf ("Board: Sandburst Corporation Kamino Reference Design "
 304                 "Serial Number: %d\n", sernum);
 305         printf ("%s\n", KAREF_U_BOOT_REL_STR);
 306
 307         printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
 308         if (sbcommon_get_master()) {
 309                 printf("Slot 0 - Master\nSlave board");
 310                 if (sbcommon_secondary_present())
 311                         printf(" present\n");
 312                 else
 313                         printf(" not detected\n");
 314         } else {
 315                 printf("Slot 1 - Slave\n\n");
 316         }
 317
 318         printf ("ScanFPGA ID:\t0x%02X\tRev:  0x%02X\n", scan_id, scan_rev);
 319         printf ("Board Rev:\t0x%02X\tID:   0x%02X\n", brd_rev, brd_id);
 320         if(0xF != ofem_brd_id) {
 321                 printf("OFemFPGA ID:\t0x%02X\tRev:  0x%02X\n", ofem_id, ofem_rev);
 322                 printf("OFEM Board Rev:\t0x%02X\tID:   0x%02X\n", ofem_brd_id, ofem_brd_rev);
 323         }
 324
 325         /* Fix the ack in the bme 32 */
 326         udelay(5000);
 327         out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001);
 328         asm("eieio");
 329
 330
 331         return (0);
 332 }
 333
 334 /*************************************************************************
 335  *  misc_init_f
 336  *
 337  *  Initialize I2C bus one to gain access to the fans
 338  ************************************************************************/
 339 int misc_init_f (void)
 340 {
 341         /* Turn on i2c bus 1 */
 342         puts ("I2C1:  ");
 343         i2c1_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 344         puts ("ready\n");
 345
 346         /* Turn on fans 3 & 4 */
 347         sbcommon_fans();
 348
 349         return (0);
 350 }
 351
 352 /*************************************************************************
 353  *  misc_init_r
 354  *
 355  *  Do nothing.
 356  ************************************************************************/
 357 int misc_init_r (void)
 358 {
 359         unsigned short sernum;
 360         char envstr[255];
 361         uchar enetaddr[6];
 362         KAREF_FPGA_REGS_ST *karef_ps;
 363         OFEM_FPGA_REGS_ST *ofem_ps;
 364
 365         if(NULL != getenv("secondserial")) {
 366                 puts("secondserial is set, switching to second serial port\n");
 367                 setenv("stderr", "serial1");
 368                 setenv("stdout", "serial1");
 369                 setenv("stdin", "serial1");
 370         }
 371
 372         setenv("ubrelver", KAREF_U_BOOT_REL_STR);
 373
 374         memset(envstr, 0, 255);
 375         sprintf (envstr, "Built %s %s by %s",
 376                  U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
 377         setenv("bldstr", envstr);
 378         saveenv();
 379
 380         if( getenv("autorecover")) {
 381                 setenv("autorecover", NULL);
 382                 saveenv();
 383                 sernum = sbcommon_get_serial_number();
 384
 385                 printf("\nSetting up environment for automatic filesystem recovery\n");
 386                 /*
 387                  * Setup default bootargs
 388                  */
 389                 memset(envstr, 0, 255);
 390
 391                 sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
 392                         "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
 393                         sernum, sernum);
 394                 setenv("bootargs", envstr);
 395
 396                 /*
 397                  * Setup Default boot command
 398                  */
 399                 setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
 400                        "fatload ide 0 8100000 pramdisk;"
 401                        "bootm 8000000 8100000");
 402
 403                 printf("Done.  Please type allow the system to continue to boot\n");
 404         }
 405
 406         if( getenv("fakeled")) {
 407                 karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
 408                 ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
 409                 ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK;
 410                 karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK;
 411                 setenv("bootdelay", "-1");
 412                 saveenv();
 413                 printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
 414         }
 415
 416 #ifdef CONFIG_HAS_ETH0
 417         if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
 418                 board_get_enetaddr(0, enetaddr);
 419                 eth_setenv_enetaddr("ethaddr", enetaddr);
 420         }
 421 #endif
 422
 423 #ifdef CONFIG_HAS_ETH1
 424         if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
 425                 board_get_enetaddr(1, enetaddr);
 426                 eth_setenv_enetaddr("eth1addr", enetaddr);
 427         }
 428 #endif
 429
 430 #ifdef CONFIG_HAS_ETH2
 431         if (!eth_getenv_enetaddr("eth2addr", enetaddr)) {
 432                 board_get_enetaddr(2, enetaddr);
 433                 eth_setenv_enetaddr("eth2addr", enetaddr);
 434         }
 435 #endif
 436
 437 #ifdef CONFIG_HAS_ETH3
 438         if (!eth_getenv_enetaddr("eth3addr", enetaddr)) {
 439                 board_get_enetaddr(3, enetaddr);
 440                 eth_setenv_enetaddr("eth3addr", enetaddr);
 441         }
 442 #endif
 443
 444         return (0);
 445 }
 446
 447 /*************************************************************************
 448  *  ide_set_reset
 449  ************************************************************************/
 450 #ifdef CONFIG_IDE_RESET
 451 void ide_set_reset(int on)
 452 {
 453         KAREF_FPGA_REGS_ST *karef_ps;
 454         /* TODO: ide reset */
 455         karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
 456
 457         if (on) {
 458                 karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
 459         } else {
 460                 karef_ps->reset_ul |= SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
 461         }
 462 }
 463 #endif /* CONFIG_IDE_RESET */
 464
 465 /*************************************************************************
 466  *  fpga_init
 467  ************************************************************************/
 468 void fpga_init(void)
 469 {
 470         KAREF_FPGA_REGS_ST *karef_ps;
 471         OFEM_FPGA_REGS_ST *ofem_ps;
 472         unsigned char ofem_id;
 473         unsigned long tmp;
 474
 475         /* Ensure we have power all around */
 476         udelay(500);
 477
 478         karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
 479         tmp =
 480                 SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK |
 481                 SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK |
 482                 SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK |
 483                 SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK |
 484                 SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK |
 485                 SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK |
 486                 SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK |
 487                 SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK |
 488                 SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK;
 489
 490         karef_ps->reset_ul = tmp;
 491
 492         /*
 493          * Wait a bit to allow the ofem fpga to get its brains
 494          */
 495         udelay(5000);
 496
 497         /*
 498          * Check to see if the ofem is there
 499          */
 500         ofem_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
 501                                   >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
 502         if(0xF != ofem_id) {
 503                 tmp =
 504                         SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK |
 505                         SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK |
 506                         SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK;
 507
 508                 ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
 509                 ofem_ps->reset_ul = tmp;
 510
 511                 ofem_ps->control_ul |= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT;
 512         }
 513
 514         karef_ps->control_ul |= 1 << SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT;
 515
 516         asm("eieio");
 517
 518         return;
 519 }
 520
 521 int karefSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 522 {
 523         unsigned short sernum;
 524         char envstr[255];
 525
 526         sernum = sbcommon_get_serial_number();
 527
 528         memset(envstr, 0, 255);
 529         /*
 530          * Setup our ip address
 531          */
 532         sprintf(envstr, "10.100.70.%d", sernum);
 533
 534         setenv("ipaddr", envstr);
 535         /*
 536          * Setup the host ip address
 537          */
 538         setenv("serverip", "10.100.17.10");
 539
 540         /*
 541          * Setup default bootargs
 542          */
 543         memset(envstr, 0, 255);
 544
 545         sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
 546                 "rw nfsroot=10.100.17.10:/home/metrobox/mbc70.%d "
 547                 "nfsaddrs=10.100.70.%d:10.100.17.10:10.100.1.1:"
 548                 "255.255.0.0:karef%d.sandburst.com:eth0:none idebus=33",
 549                 sernum, sernum, sernum);
 550
 551         setenv("bootargs_nfs", envstr);
 552         setenv("bootargs", envstr);
 553
 554         /*
 555          * Setup CF bootargs
 556          */
 557         memset(envstr, 0, 255);
 558
 559         sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
 560                 "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
 561                 sernum, sernum);
 562
 563         setenv("bootargs_cf", envstr);
 564
 565         /*
 566          * Setup Default boot command
 567          */
 568         setenv("bootcmd_tftp", "tftp 8000000 uImage.karef;bootm 8000000");
 569         setenv("bootcmd", "tftp 8000000 uImage.karef;bootm 8000000");
 570
 571         /*
 572          * Setup compact flash boot command
 573          */
 574         setenv("bootcmd_cf", "fatload ide 0 8000000 uimage.karef;bootm 8000000");
 575
 576         saveenv();
 577
 578         return(1);
 579 }
 580
 581 int karefRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 582 {
 583         unsigned short sernum;
 584         char envstr[255];
 585
 586         sernum = sbcommon_get_serial_number();
 587
 588         printf("\nSetting up environment for filesystem recovery\n");
 589         /*
 590          * Setup default bootargs
 591          */
 592         memset(envstr, 0, 255);
 593
 594         sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
 595                 "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none",
 596                 sernum, sernum);
 597         setenv("bootargs", envstr);
 598
 599         /*
 600          * Setup Default boot command
 601          */
 602
 603         setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
 604                "fatload ide 0 8100000 pramdisk;"
 605                "bootm 8000000 8100000");
 606
 607         printf("Done.  Please type boot<cr>.\nWhen the kernel has booted"
 608                " please type fsrecover.sh<cr>\n");
 609
 610         return(1);
 611 }
 612
 613 U_BOOT_CMD(kasetup, 1, 1, karefSetupVars,
 614            "Set environment to factory defaults", "");
 615
 616 U_BOOT_CMD(karecover, 1, 1, karefRecover,
 617            "Set environment to allow for fs recovery", "");