board/sandburst/karef/karef.c

   1 /*
   2  *  Copyright (C) 2005 Sandburst Corporation
   3  *  Travis B. Sawyer
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <config.h>
   9 #include <common.h>
  10 #include <command.h>
  11 #include "karef.h"
  12 #include "karef_version.h"
  13 #include <timestamp.h>
  14 #include <asm/processor.h>
  15 #include <asm/io.h>
  16 #include <spd_sdram.h>
  17 #include <i2c.h>
  18 #include "../common/sb_common.h"
  19 #include "../common/ppc440gx_i2c.h"
  20 #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) || \
  21     defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
  22 #include <net.h>
  23 #endif
  24
  25 void fpga_init (void);
  26
  27 KAREF_BOARD_ID_ST board_id_as[] =
  28 {
  29         {"Undefined"},                       /* Not specified */
  30         {"Kamino Reference Design"},
  31         {"Reserved"},                        /* Reserved for future use */
  32         {"Reserved"},                        /* Reserved for future use */
  33 };
  34
  35 KAREF_BOARD_ID_ST ofem_board_id_as[] =
  36 {
  37         {"Undefined"},
  38         {"1x10 + 10x2"},
  39         {"Reserved"},
  40         {"Reserved"},
  41 };
  42
  43 /*************************************************************************
  44  *  board_early_init_f
  45  *
  46  *  Setup chip selects, initialize the Opto-FPGA, initialize
  47  *  interrupt polarity and triggers.
  48  ************************************************************************/
  49 int board_early_init_f (void)
  50 {
  51         ppc440_gpio_regs_t *gpio_regs;
  52
  53         /* Enable GPIO interrupts */
  54         mtsdr(SDR0_PFC0, 0x00103E00);
  55
  56         /* Setup access for LEDs, and system topology info */
  57         gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
  58         gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
  59         gpio_regs->tri_state  = SBCOMMON_GPIO_DBGLEDS;
  60
  61         /* Turn on all the leds for now */
  62         gpio_regs->out = SBCOMMON_GPIO_LEDS;
  63
  64         /*--------------------------------------------------------------------+
  65           | Initialize EBC CONFIG
  66           +-------------------------------------------------------------------*/
  67         mtebc(EBC0_CFG,
  68               EBC_CFG_LE_UNLOCK    | EBC_CFG_PTD_ENABLE |
  69               EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
  70               EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
  71               EBC_CFG_EMC_DEFAULT  | EBC_CFG_PME_DISABLE |
  72               EBC_CFG_PR_32);
  73
  74         /*--------------------------------------------------------------------+
  75           | 1/2 MB FLASH. Initialize bank 0 with default values.
  76           +-------------------------------------------------------------------*/
  77         mtebc(PB0AP,
  78               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
  79               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
  80               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
  81               EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
  82               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
  83               EBC_BXAP_PEN_DISABLED);
  84
  85         mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
  86               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
  87         /*--------------------------------------------------------------------+
  88           | 8KB NVRAM/RTC. Initialize bank 1 with default values.
  89           +-------------------------------------------------------------------*/
  90         mtebc(PB1AP,
  91               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
  92               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
  93               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
  94               EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
  95               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
  96               EBC_BXAP_PEN_DISABLED);
  97
  98         mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000) |
  99               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
 100
 101         /*--------------------------------------------------------------------+
 102           | Compact Flash, uses 2 Chip Selects (2 & 6)
 103           +-------------------------------------------------------------------*/
 104         mtebc(PB2AP,
 105               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
 106               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
 107               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
 108               EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
 109               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
 110               EBC_BXAP_PEN_DISABLED);
 111
 112         mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0xF0000000) |
 113               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
 114
 115         /*--------------------------------------------------------------------+
 116           | KaRef Scan FPGA. Initialize bank 3 with default values.
 117           +-------------------------------------------------------------------*/
 118         mtebc(PB5AP,
 119               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 120               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 121               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 122               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 123               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 124
 125         mtebc(PB5CR, EBC_BXCR_BAS_ENCODE(0x48200000) |
 126               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 127
 128         /*--------------------------------------------------------------------+
 129           | MAC A & B for Kamino.  OFEM FPGA decodes the addresses
 130           | Initialize bank 4 with default values.
 131           +-------------------------------------------------------------------*/
 132         mtebc(PB4AP,
 133               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 134               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 135               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 136               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 137               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 138
 139         mtebc(PB4CR, EBC_BXCR_BAS_ENCODE(0x48600000) |
 140               EBC_BXCR_BS_2MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 141
 142         /*--------------------------------------------------------------------+
 143           | OFEM FPGA  Initialize bank 5 with default values.
 144           +-------------------------------------------------------------------*/
 145         mtebc(PB3AP,
 146               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 147               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 148               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 149               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 150               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 151
 152
 153         mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48400000) |
 154               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 155
 156
 157         /*--------------------------------------------------------------------+
 158           | Compact Flash, uses 2 Chip Selects (2 & 6)
 159           +-------------------------------------------------------------------*/
 160         mtebc(PB6AP,
 161               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
 162               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
 163               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
 164               EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
 165               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
 166               EBC_BXAP_PEN_DISABLED);
 167
 168         mtebc(PB6CR, EBC_BXCR_BAS_ENCODE(0xF0100000) |
 169               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
 170
 171         /*--------------------------------------------------------------------+
 172           | BME-32. Initialize bank 7 with default values.
 173           +-------------------------------------------------------------------*/
 174         mtebc(PB7AP,
 175               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 176               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 177               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 178               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 179               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 180
 181         mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48500000) |
 182               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 183
 184         /*--------------------------------------------------------------------+
 185          * Setup the interrupt controller polarities, triggers, etc.
 186          +-------------------------------------------------------------------*/
 187         /*
 188          * Because of the interrupt handling rework to handle 440GX interrupts
 189          * with the common code, we needed to change names of the UIC registers.
 190          * Here the new relationship:
 191          *
 192          * U-Boot name  440GX name
 193          * -----------------------
 194          * UIC0         UICB0
 195          * UIC1         UIC0
 196          * UIC2         UIC1
 197          * UIC3         UIC2
 198          */
 199         mtdcr (UIC1SR, 0xffffffff);     /* clear all */
 200         mtdcr (UIC1ER, 0x00000000);     /* disable all */
 201         mtdcr (UIC1CR, 0x00000000);     /* all non- critical */
 202         mtdcr (UIC1PR, 0xfffffe03);     /* polarity */
 203         mtdcr (UIC1TR, 0x01c00000);     /* trigger edge vs level */
 204         mtdcr (UIC1VR, 0x00000001);     /* int31 highest, base=0x000 */
 205         mtdcr (UIC1SR, 0xffffffff);     /* clear all */
 206
 207         mtdcr (UIC2SR, 0xffffffff);     /* clear all */
 208         mtdcr (UIC2ER, 0x00000000);     /* disable all */
 209         mtdcr (UIC2CR, 0x00000000);     /* all non-critical */
 210         mtdcr (UIC2PR, 0xffffc8ff);     /* polarity */
 211         mtdcr (UIC2TR, 0x00ff0000);     /* trigger edge vs level */
 212         mtdcr (UIC2VR, 0x00000001);     /* int31 highest, base=0x000 */
 213         mtdcr (UIC2SR, 0xffffffff);     /* clear all */
 214
 215         mtdcr (UIC3SR, 0xffffffff);     /* clear all */
 216         mtdcr (UIC3ER, 0x00000000);     /* disable all */
 217         mtdcr (UIC3CR, 0x00000000);     /* all non-critical */
 218         mtdcr (UIC3PR, 0xffff83ff);     /* polarity */
 219         mtdcr (UIC3TR, 0x00ff8c0f);     /* trigger edge vs level */
 220         mtdcr (UIC3VR, 0x00000001);     /* int31 highest, base=0x000 */
 221         mtdcr (UIC3SR, 0xffffffff);     /* clear all */
 222
 223         mtdcr (UIC0SR, 0xfc000000);     /* clear all */
 224         mtdcr (UIC0ER, 0x00000000);     /* disable all */
 225         mtdcr (UIC0CR, 0x00000000);     /* all non-critical */
 226         mtdcr (UIC0PR, 0xfc000000);
 227         mtdcr (UIC0TR, 0x00000000);
 228         mtdcr (UIC0VR, 0x00000001);
 229
 230         fpga_init();
 231
 232         return 0;
 233 }
 234
 235
 236 /*************************************************************************
 237  *  checkboard
 238  *
 239  *  Dump pertinent info to the console
 240  ************************************************************************/
 241 int checkboard (void)
 242 {
 243         sys_info_t sysinfo;
 244         unsigned char brd_rev, brd_id;
 245         unsigned short sernum;
 246         unsigned char scan_rev, scan_id, ofem_rev=0, ofem_id=0;
 247         unsigned char ofem_brd_rev, ofem_brd_id;
 248         KAREF_FPGA_REGS_ST *karef_ps;
 249         OFEM_FPGA_REGS_ST *ofem_ps;
 250
 251         karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
 252         ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
 253
 254         scan_id = (unsigned char)((karef_ps->revision_ul &
 255                                    SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK)
 256                                   >> SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT);
 257
 258         scan_rev = (unsigned char)((karef_ps->revision_ul & SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK)
 259                                    >> SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT);
 260
 261         brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK)
 262                                   >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT);
 263
 264         brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK)
 265                                  >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT);
 266
 267         ofem_brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
 268                                       >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
 269
 270         ofem_brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK)
 271                                        >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT);
 272
 273         if (0xF != ofem_brd_id) {
 274                 ofem_id = (unsigned char)((ofem_ps->revision_ul &
 275                                            SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK)
 276                                           >> SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT);
 277
 278                 ofem_rev = (unsigned char)((ofem_ps->revision_ul &
 279                                             SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK)
 280                                            >> SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT);
 281         }
 282
 283         get_sys_info (&sysinfo);
 284
 285         sernum = sbcommon_get_serial_number();
 286
 287         printf ("Board: Sandburst Corporation Kamino Reference Design "
 288                 "Serial Number: %d\n", sernum);
 289         printf ("%s\n", KAREF_U_BOOT_REL_STR);
 290
 291         printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
 292         if (sbcommon_get_master()) {
 293                 printf("Slot 0 - Master\nSlave board");
 294                 if (sbcommon_secondary_present())
 295                         printf(" present\n");
 296                 else
 297                         printf(" not detected\n");
 298         } else {
 299                 printf("Slot 1 - Slave\n\n");
 300         }
 301
 302         printf ("ScanFPGA ID:\t0x%02X\tRev:  0x%02X\n", scan_id, scan_rev);
 303         printf ("Board Rev:\t0x%02X\tID:   0x%02X\n", brd_rev, brd_id);
 304         if(0xF != ofem_brd_id) {
 305                 printf("OFemFPGA ID:\t0x%02X\tRev:  0x%02X\n", ofem_id, ofem_rev);
 306                 printf("OFEM Board Rev:\t0x%02X\tID:   0x%02X\n", ofem_brd_id, ofem_brd_rev);
 307         }
 308
 309         /* Fix the ack in the bme 32 */
 310         udelay(5000);
 311         out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001);
 312         asm("eieio");
 313
 314
 315         return (0);
 316 }
 317
 318 /*************************************************************************
 319  *  misc_init_f
 320  *
 321  *  Initialize I2C bus one to gain access to the fans
 322  ************************************************************************/
 323 int misc_init_f (void)
 324 {
 325         /* Turn on i2c bus 1 */
 326         puts ("I2C1:  ");
 327         i2c1_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 328         puts ("ready\n");
 329
 330         /* Turn on fans 3 & 4 */
 331         sbcommon_fans();
 332
 333         return (0);
 334 }
 335
 336 /*************************************************************************
 337  *  misc_init_r
 338  *
 339  *  Do nothing.
 340  ************************************************************************/
 341 int misc_init_r (void)
 342 {
 343         unsigned short sernum;
 344         char envstr[255];
 345         uchar enetaddr[6];
 346         KAREF_FPGA_REGS_ST *karef_ps;
 347         OFEM_FPGA_REGS_ST *ofem_ps;
 348
 349         if(NULL != getenv("secondserial")) {
 350                 puts("secondserial is set, switching to second serial port\n");
 351                 setenv("stderr", "serial1");
 352                 setenv("stdout", "serial1");
 353                 setenv("stdin", "serial1");
 354         }
 355
 356         setenv("ubrelver", KAREF_U_BOOT_REL_STR);
 357
 358         memset(envstr, 0, 255);
 359         sprintf (envstr, "Built %s %s by %s",
 360                  U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
 361         setenv("bldstr", envstr);
 362         saveenv();
 363
 364         if( getenv("autorecover")) {
 365                 setenv("autorecover", NULL);
 366                 saveenv();
 367                 sernum = sbcommon_get_serial_number();
 368
 369                 printf("\nSetting up environment for automatic filesystem recovery\n");
 370                 /*
 371                  * Setup default bootargs
 372                  */
 373                 memset(envstr, 0, 255);
 374
 375                 sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
 376                         "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
 377                         sernum, sernum);
 378                 setenv("bootargs", envstr);
 379
 380                 /*
 381                  * Setup Default boot command
 382                  */
 383                 setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
 384                        "fatload ide 0 8100000 pramdisk;"
 385                        "bootm 8000000 8100000");
 386
 387                 printf("Done.  Please type allow the system to continue to boot\n");
 388         }
 389
 390         if( getenv("fakeled")) {
 391                 karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
 392                 ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
 393                 ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK;
 394                 karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK;
 395                 setenv("bootdelay", "-1");
 396                 saveenv();
 397                 printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
 398         }
 399
 400 #ifdef CONFIG_HAS_ETH0
 401         if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
 402                 board_get_enetaddr(0, enetaddr);
 403                 eth_setenv_enetaddr("ethaddr", enetaddr);
 404         }
 405 #endif
 406
 407 #ifdef CONFIG_HAS_ETH1
 408         if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
 409                 board_get_enetaddr(1, enetaddr);
 410                 eth_setenv_enetaddr("eth1addr", enetaddr);
 411         }
 412 #endif
 413
 414 #ifdef CONFIG_HAS_ETH2
 415         if (!eth_getenv_enetaddr("eth2addr", enetaddr)) {
 416                 board_get_enetaddr(2, enetaddr);
 417                 eth_setenv_enetaddr("eth2addr", enetaddr);
 418         }
 419 #endif
 420
 421 #ifdef CONFIG_HAS_ETH3
 422         if (!eth_getenv_enetaddr("eth3addr", enetaddr)) {
 423                 board_get_enetaddr(3, enetaddr);
 424                 eth_setenv_enetaddr("eth3addr", enetaddr);
 425         }
 426 #endif
 427
 428         return (0);
 429 }
 430
 431 /*************************************************************************
 432  *  ide_set_reset
 433  ************************************************************************/
 434 #ifdef CONFIG_IDE_RESET
 435 void ide_set_reset(int on)
 436 {
 437         KAREF_FPGA_REGS_ST *karef_ps;
 438         /* TODO: ide reset */
 439         karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
 440
 441         if (on) {
 442                 karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
 443         } else {
 444                 karef_ps->reset_ul |= SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
 445         }
 446 }
 447 #endif /* CONFIG_IDE_RESET */
 448
 449 /*************************************************************************
 450  *  fpga_init
 451  ************************************************************************/
 452 void fpga_init(void)
 453 {
 454         KAREF_FPGA_REGS_ST *karef_ps;
 455         OFEM_FPGA_REGS_ST *ofem_ps;
 456         unsigned char ofem_id;
 457         unsigned long tmp;
 458
 459         /* Ensure we have power all around */
 460         udelay(500);
 461
 462         karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
 463         tmp =
 464                 SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK |
 465                 SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK |
 466                 SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK |
 467                 SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK |
 468                 SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK |
 469                 SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK |
 470                 SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK |
 471                 SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK |
 472                 SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK;
 473
 474         karef_ps->reset_ul = tmp;
 475
 476         /*
 477          * Wait a bit to allow the ofem fpga to get its brains
 478          */
 479         udelay(5000);
 480
 481         /*
 482          * Check to see if the ofem is there
 483          */
 484         ofem_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
 485                                   >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
 486         if(0xF != ofem_id) {
 487                 tmp =
 488                         SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK |
 489                         SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK |
 490                         SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK;
 491
 492                 ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
 493                 ofem_ps->reset_ul = tmp;
 494
 495                 ofem_ps->control_ul |= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT;
 496         }
 497
 498         karef_ps->control_ul |= 1 << SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT;
 499
 500         asm("eieio");
 501
 502         return;
 503 }
 504
 505 int karefSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 506 {
 507         unsigned short sernum;
 508         char envstr[255];
 509
 510         sernum = sbcommon_get_serial_number();
 511
 512         memset(envstr, 0, 255);
 513         /*
 514          * Setup our ip address
 515          */
 516         sprintf(envstr, "10.100.70.%d", sernum);
 517
 518         setenv("ipaddr", envstr);
 519         /*
 520          * Setup the host ip address
 521          */
 522         setenv("serverip", "10.100.17.10");
 523
 524         /*
 525          * Setup default bootargs
 526          */
 527         memset(envstr, 0, 255);
 528
 529         sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
 530                 "rw nfsroot=10.100.17.10:/home/metrobox/mbc70.%d "
 531                 "nfsaddrs=10.100.70.%d:10.100.17.10:10.100.1.1:"
 532                 "255.255.0.0:karef%d.sandburst.com:eth0:none idebus=33",
 533                 sernum, sernum, sernum);
 534
 535         setenv("bootargs_nfs", envstr);
 536         setenv("bootargs", envstr);
 537
 538         /*
 539          * Setup CF bootargs
 540          */
 541         memset(envstr, 0, 255);
 542
 543         sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
 544                 "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
 545                 sernum, sernum);
 546
 547         setenv("bootargs_cf", envstr);
 548
 549         /*
 550          * Setup Default boot command
 551          */
 552         setenv("bootcmd_tftp", "tftp 8000000 uImage.karef;bootm 8000000");
 553         setenv("bootcmd", "tftp 8000000 uImage.karef;bootm 8000000");
 554
 555         /*
 556          * Setup compact flash boot command
 557          */
 558         setenv("bootcmd_cf", "fatload ide 0 8000000 uimage.karef;bootm 8000000");
 559
 560         saveenv();
 561
 562         return(1);
 563 }
 564
 565 int karefRecover(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 566 {
 567         unsigned short sernum;
 568         char envstr[255];
 569
 570         sernum = sbcommon_get_serial_number();
 571
 572         printf("\nSetting up environment for filesystem recovery\n");
 573         /*
 574          * Setup default bootargs
 575          */
 576         memset(envstr, 0, 255);
 577
 578         sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
 579                 "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none",
 580                 sernum, sernum);
 581         setenv("bootargs", envstr);
 582
 583         /*
 584          * Setup Default boot command
 585          */
 586
 587         setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
 588                "fatload ide 0 8100000 pramdisk;"
 589                "bootm 8000000 8100000");
 590
 591         printf("Done.  Please type boot<cr>.\nWhen the kernel has booted"
 592                " please type fsrecover.sh<cr>\n");
 593
 594         return(1);
 595 }
 596
 597 U_BOOT_CMD(kasetup, 1, 1, karefSetupVars,
 598            "Set environment to factory defaults", "");
 599
 600 U_BOOT_CMD(karecover, 1, 1, karefRecover,
 601            "Set environment to allow for fs recovery", "");