board/sandburst/metrobox/metrobox.c

   1 /*
   2  *  Copyright (c) 2005
   3  *  Travis B. Sawyer,  Sandburst Corporation, tsawyer@sandburst.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23 #include <config.h>
  24 #include <common.h>
  25 #include <command.h>
  26 #include "metrobox.h"
  27 #include "metrobox_version.h"
  28 #include <asm/processor.h>
  29 #include <asm/io.h>
  30 #include <spd_sdram.h>
  31 #include <i2c.h>
  32 #include "../common/ppc440gx_i2c.h"
  33 #include "../common/sb_common.h"
  34
  35 void fpga_init (void);
  36
  37 METROBOX_BOARD_ID_ST board_id_as[] =
  38 {       {"Undefined"},                      /* Not specified */
  39         {"2x10Gb"},                         /* 2 ports, 10 GbE */
  40         {"20x1Gb"},                         /* 20 ports, 1 GbE */
  41         {"Reserved"},                        /* Reserved for future use */
  42 };
  43
  44 /*************************************************************************
  45  *  board_early_init_f
  46  *
  47  *  Setup chip selects, initialize the Opto-FPGA, initialize
  48  *  interrupt polarity and triggers.
  49  ************************************************************************/
  50 int board_early_init_f (void)
  51 {
  52         ppc440_gpio_regs_t *gpio_regs;
  53
  54         /* Enable GPIO interrupts */
  55         mtsdr(sdr_pfc0, 0x00103E00);
  56
  57         /* Setup access for LEDs, and system topology info */
  58         gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
  59         gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
  60         gpio_regs->tri_state  = SBCOMMON_GPIO_DBGLEDS;
  61
  62         /* Turn on all the leds for now */
  63         gpio_regs->out = SBCOMMON_GPIO_LEDS;
  64
  65         /*--------------------------------------------------------------------+
  66           | Initialize EBC CONFIG
  67           +-------------------------------------------------------------------*/
  68         mtebc(xbcfg,
  69               EBC_CFG_LE_UNLOCK    | EBC_CFG_PTD_ENABLE |
  70               EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
  71               EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
  72               EBC_CFG_EMC_DEFAULT  | EBC_CFG_PME_DISABLE |
  73               EBC_CFG_PR_32);
  74
  75         /*--------------------------------------------------------------------+
  76           | 1/2 MB FLASH. Initialize bank 0 with default values.
  77           +-------------------------------------------------------------------*/
  78         mtebc(pb0ap,
  79               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
  80               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
  81               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
  82               EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
  83               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
  84               EBC_BXAP_PEN_DISABLED);
  85
  86         mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
  87               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
  88         /*--------------------------------------------------------------------+
  89           | 8KB NVRAM/RTC. Initialize bank 1 with default values.
  90           +-------------------------------------------------------------------*/
  91         mtebc(pb1ap,
  92               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
  93               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
  94               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
  95               EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
  96               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
  97               EBC_BXAP_PEN_DISABLED);
  98
  99         mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
 100               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
 101
 102         /*--------------------------------------------------------------------+
 103           | Compact Flash, uses 2 Chip Selects (2 & 6)
 104           +-------------------------------------------------------------------*/
 105         mtebc(pb2ap,
 106               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
 107               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
 108               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
 109               EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
 110               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
 111               EBC_BXAP_PEN_DISABLED);
 112
 113         mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) |
 114               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
 115
 116         /*--------------------------------------------------------------------+
 117           | OPTO & OFEM FPGA. Initialize bank 3 with default values.
 118           +-------------------------------------------------------------------*/
 119         mtebc(pb3ap,
 120               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 121               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 122               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 123               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 124               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 125
 126         mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48200000) |
 127               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 128
 129         /*--------------------------------------------------------------------+
 130           | MAC A for metrobox
 131           | MAC A & B for Kamino.  OFEM FPGA decodes the addresses
 132           | Initialize bank 4 with default values.
 133           +-------------------------------------------------------------------*/
 134         mtebc(pb4ap,
 135               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 136               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 137               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 138               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 139               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 140
 141         mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) |
 142               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 143
 144         /*--------------------------------------------------------------------+
 145           | Metrobox MAC B  Initialize bank 5 with default values.
 146           | KA REF FPGA  Initialize bank 5 with default values.
 147           +-------------------------------------------------------------------*/
 148         mtebc(pb5ap,
 149               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 150               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 151               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 152               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 153               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 154
 155         mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48700000) |
 156               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 157
 158         /*--------------------------------------------------------------------+
 159           | Compact Flash, uses 2 Chip Selects (2 & 6)
 160           +-------------------------------------------------------------------*/
 161         mtebc(pb6ap,
 162               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
 163               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
 164               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
 165               EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
 166               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
 167               EBC_BXAP_PEN_DISABLED);
 168
 169         mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) |
 170               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
 171
 172         /*--------------------------------------------------------------------+
 173           | BME-32. Initialize bank 7 with default values.
 174           +-------------------------------------------------------------------*/
 175         mtebc(pb7ap,
 176               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 177               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 178               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 179               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 180               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 181
 182         mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) |
 183               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 184
 185         /*--------------------------------------------------------------------+
 186          * Setup the interrupt controller polarities, triggers, etc.
 187          +-------------------------------------------------------------------*/
 188         /*
 189          * Because of the interrupt handling rework to handle 440GX interrupts
 190          * with the common code, we needed to change names of the UIC registers.
 191          * Here the new relationship:
 192          *
 193          * U-Boot name  440GX name
 194          * -----------------------
 195          * UIC0         UICB0
 196          * UIC1         UIC0
 197          * UIC2         UIC1
 198          * UIC3         UIC2
 199          */
 200         mtdcr (uic1sr, 0xffffffff);     /* clear all */
 201         mtdcr (uic1er, 0x00000000);     /* disable all */
 202         mtdcr (uic1cr, 0x00000000);     /* all non- critical */
 203         mtdcr (uic1pr, 0xfffffe03);     /* polarity */
 204         mtdcr (uic1tr, 0x01c00000);     /* trigger edge vs level */
 205         mtdcr (uic1vr, 0x00000001);     /* int31 highest, base=0x000 */
 206         mtdcr (uic1sr, 0xffffffff);     /* clear all */
 207
 208         mtdcr (uic2sr, 0xffffffff);     /* clear all */
 209         mtdcr (uic2er, 0x00000000);     /* disable all */
 210         mtdcr (uic2cr, 0x00000000);     /* all non-critical */
 211         mtdcr (uic2pr, 0xffffc8ff);     /* polarity */
 212         mtdcr (uic2tr, 0x00ff0000);     /* trigger edge vs level */
 213         mtdcr (uic2vr, 0x00000001);     /* int31 highest, base=0x000 */
 214         mtdcr (uic2sr, 0xffffffff);     /* clear all */
 215
 216         mtdcr (uic3sr, 0xffffffff);     /* clear all */
 217         mtdcr (uic3er, 0x00000000);     /* disable all */
 218         mtdcr (uic3cr, 0x00000000);     /* all non-critical */
 219         mtdcr (uic3pr, 0xffff83ff);     /* polarity */
 220         mtdcr (uic3tr, 0x00ff8c0f);     /* trigger edge vs level */
 221         mtdcr (uic3vr, 0x00000001);     /* int31 highest, base=0x000 */
 222         mtdcr (uic3sr, 0xffffffff);     /* clear all */
 223
 224         mtdcr (uic0sr, 0xfc000000);     /* clear all */
 225         mtdcr (uic0er, 0x00000000);     /* disable all */
 226         mtdcr (uic0cr, 0x00000000);     /* all non-critical */
 227         mtdcr (uic0pr, 0xfc000000);
 228         mtdcr (uic0tr, 0x00000000);
 229         mtdcr (uic0vr, 0x00000001);
 230
 231         fpga_init();
 232
 233         return 0;
 234 }
 235
 236 /*************************************************************************
 237  *  checkboard
 238  *
 239  *  Dump pertinent info to the console
 240  ************************************************************************/
 241 int checkboard (void)
 242 {
 243         sys_info_t sysinfo;
 244         unsigned char brd_rev, brd_id;
 245         unsigned short sernum;
 246         unsigned char opto_rev, opto_id;
 247         OPTO_FPGA_REGS_ST *opto_ps;
 248
 249         opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
 250
 251         opto_rev = (unsigned char)((opto_ps->revision_ul &
 252                                     SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
 253                                    >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
 254
 255         opto_id = (unsigned char)((opto_ps->revision_ul &
 256                                    SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK)
 257                                   >> SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT);
 258
 259         brd_rev = (unsigned char)((opto_ps->boardinfo_ul &
 260                                    SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK)
 261                                   >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT);
 262
 263         brd_id = (unsigned char)((opto_ps->boardinfo_ul &
 264                                   SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK)
 265                                  >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT);
 266
 267         get_sys_info (&sysinfo);
 268
 269         sernum = sbcommon_get_serial_number();
 270         printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum);
 271         printf ("%s\n", METROBOX_U_BOOT_REL_STR);
 272
 273         printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER);
 274         if (sbcommon_get_master()) {
 275                 printf("Slot 0 - Master\nSlave board");
 276                 if (sbcommon_secondary_present())
 277                         printf(" present\n");
 278                 else
 279                         printf(" not detected\n");
 280         } else {
 281                 printf("Slot 1 - Slave\n\n");
 282         }
 283
 284         printf ("OptoFPGA ID:\t0x%02X\tRev:  0x%02X\n", opto_id, opto_rev);
 285         printf ("Board Rev:\t0x%02X\tID:  %s\n", brd_rev, board_id_as[brd_id].name);
 286
 287         /* Fix the ack in the bme 32 */
 288         udelay(5000);
 289         out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001);
 290         asm("eieio");
 291
 292
 293         return (0);
 294 }
 295
 296 /*************************************************************************
 297  *  misc_init_f
 298  *
 299  *  Initialize I2C bus one to gain access to the fans
 300  ************************************************************************/
 301 int misc_init_f (void)
 302 {
 303         /* Turn on i2c bus 1 */
 304         puts ("I2C1:  ");
 305         i2c1_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 306         puts ("ready\n");
 307
 308         /* Turn on fans */
 309         sbcommon_fans();
 310
 311         return (0);
 312 }
 313
 314 /*************************************************************************
 315  *  misc_init_r
 316  *
 317  *  Do nothing.
 318  ************************************************************************/
 319 int misc_init_r (void)
 320 {
 321         unsigned short sernum;
 322         char envstr[255];
 323         unsigned char opto_rev;
 324         OPTO_FPGA_REGS_ST *opto_ps;
 325
 326         opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
 327
 328         if(NULL != getenv("secondserial")) {
 329             puts("secondserial is set, switching to second serial port\n");
 330             setenv("stderr", "serial1");
 331             setenv("stdout", "serial1");
 332             setenv("stdin", "serial1");
 333         }
 334
 335         setenv("ubrelver", METROBOX_U_BOOT_REL_STR);
 336
 337         memset(envstr, 0, 255);
 338         sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER);
 339         setenv("bldstr", envstr);
 340         saveenv();
 341
 342         if( getenv("autorecover")) {
 343                 setenv("autorecover", NULL);
 344                 saveenv();
 345                 sernum = sbcommon_get_serial_number();
 346
 347                 printf("\nSetting up environment for automatic filesystem recovery\n");
 348                 /*
 349                  * Setup default bootargs
 350                  */
 351                 memset(envstr, 0, 255);
 352                 sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
 353                         "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
 354                         sernum, sernum);
 355                 setenv("bootargs", envstr);
 356
 357                 /*
 358                  * Setup Default boot command
 359                  */
 360                 setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
 361                        "fatload ide 0 8100000 pramdisk;"
 362                        "bootm 8000000 8100000");
 363
 364                 printf("Done.  Please type allow the system to continue to boot\n");
 365         }
 366
 367         if( getenv("fakeled")) {
 368                 setenv("bootdelay", "-1");
 369                 saveenv();
 370                 printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
 371                 opto_rev = (unsigned char)((opto_ps->revision_ul &
 372                                             SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
 373                                            >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
 374
 375                 if(0x12 <= opto_rev) {
 376                         opto_ps->control_ul &= ~ SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK;
 377                 }
 378         }
 379
 380         return (0);
 381 }
 382
 383 /*************************************************************************
 384  *  ide_set_reset
 385  ************************************************************************/
 386 #ifdef CONFIG_IDE_RESET
 387 void ide_set_reset(int on)
 388 {
 389         OPTO_FPGA_REGS_ST *opto_ps;
 390         opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
 391
 392         if (on) {               /* assert RESET */
 393             opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
 394         } else {                /* release RESET */
 395             opto_ps->reset_ul |= SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
 396         }
 397 }
 398 #endif /* CONFIG_IDE_RESET */
 399
 400 /*************************************************************************
 401  *  fpga_init
 402  ************************************************************************/
 403 void fpga_init(void)
 404 {
 405         OPTO_FPGA_REGS_ST *opto_ps;
 406         unsigned char opto_rev;
 407         unsigned long tmp;
 408
 409         /* Ensure we have power all around */
 410         udelay(500);
 411
 412         /*
 413          * Take appropriate hw bits out of reset
 414          */
 415         opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
 416
 417         tmp =
 418             SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK |
 419             SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK |
 420             SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK |
 421             SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK |
 422             SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK |
 423             SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK |
 424             SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK |
 425             SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK |
 426             SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK |
 427             SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK |
 428             SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK |
 429             SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK |
 430             SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK |
 431             SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK |
 432             SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK |
 433             SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK |
 434             SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK |
 435             SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK;
 436         opto_ps->reset_ul = tmp;
 437         /*
 438          * Turn on the 'Slow Blink' for the System Error Led.
 439          * Ensure FPGA rev is up to at least rev 0x12
 440          */
 441         opto_rev = (unsigned char)((opto_ps->revision_ul &
 442                                     SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
 443                                    >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
 444         if(0x12 <= opto_rev) {
 445             opto_ps->control_ul |= 1 << SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT;
 446         }
 447
 448         asm("eieio");
 449
 450         return;
 451 }
 452
 453 int metroboxSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 454 {
 455         unsigned short sernum;
 456         char envstr[255];
 457
 458         sernum = sbcommon_get_serial_number();
 459
 460         memset(envstr, 0, 255);
 461         /*
 462          * Setup our ip address
 463          */
 464         sprintf(envstr, "10.100.60.%d", sernum);
 465
 466         setenv("ipaddr", envstr);
 467         /*
 468          * Setup the host ip address
 469          */
 470         setenv("serverip", "10.100.17.10");
 471
 472         /*
 473          * Setup default bootargs
 474          */
 475         memset(envstr, 0, 255);
 476
 477         sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
 478                 "rw nfsroot=10.100.17.10:/home/metrobox/mbc%d "
 479                 "nfsaddrs=10.100.60.%d:10.100.17.10:10.100.1.1"
 480                 ":255.255.0.0:metrobox%d.sandburst.com:eth0:none idebus=33",
 481                 sernum, sernum, sernum);
 482
 483         setenv("bootargs_nfs", envstr);
 484         setenv("bootargs", envstr);
 485
 486         /*
 487          * Setup CF bootargs
 488          */
 489         memset(envstr, 0, 255);
 490         sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
 491                 "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
 492                 sernum, sernum);
 493
 494         setenv("bootargs_cf", envstr);
 495
 496         /*
 497          * Setup Default boot command
 498          */
 499         setenv("bootcmd_tftp", "tftp 8000000 pImage.metrobox;bootm 8000000");
 500         setenv("bootcmd", "tftp 8000000 pImage.metrobox;bootm 8000000");
 501
 502         /*
 503          * Setup compact flash boot command
 504          */
 505         setenv("bootcmd_cf", "fatload ide 0 8000000 pimage.metrobox;bootm 8000000");
 506
 507         saveenv();
 508
 509
 510         return(1);
 511 }
 512
 513 int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 514 {
 515         unsigned short sernum;
 516         char envstr[255];
 517
 518         sernum = sbcommon_get_serial_number();
 519
 520         printf("\nSetting up environment for filesystem recovery\n");
 521         /*
 522          * Setup default bootargs
 523          */
 524         memset(envstr, 0, 255);
 525         sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
 526                 "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none",
 527                 sernum, sernum);
 528
 529         setenv("bootargs", envstr);
 530
 531         /*
 532          * Setup Default boot command
 533          */
 534         setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
 535                "fatload ide 0 8100000 pramdisk;"
 536                "bootm 8000000 8100000");
 537
 538         printf("Done.  Please type boot<cr>.\nWhen the kernel has booted"
 539                " please type fsrecover.sh<cr>\n");
 540
 541         return(1);
 542 }
 543
 544 U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars,
 545            "mbsetup - Set environment to factory defaults\n", NULL);
 546
 547 U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover,
 548            "mbrecover - Set environment to allow for fs recovery\n", NULL);