board/sheldon/simpc8313/simpc8313.c

   1 /*
   2  * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
   3  * Copyright (C) Sheldon Instruments, Inc. 2008
   4  *
   5  * Author: Ron Madrid <info@sheldoninst.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <libfdt.h>
  12 #include <pci.h>
  13 #include <mpc83xx.h>
  14 #include <ns16550.h>
  15 #include <nand.h>
  16 #include <asm/io.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 #ifndef CONFIG_NAND_SPL
  21 int checkboard(void)
  22 {
  23         puts("Board: Sheldon Instruments SIMPC8313\n");
  24         return 0;
  25 }
  26
  27 static struct pci_region pci_regions[] = {
  28         {
  29                 bus_start: CONFIG_SYS_PCI1_MEM_BASE,
  30                 phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
  31                 size: CONFIG_SYS_PCI1_MEM_SIZE,
  32                 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
  33         },
  34         {
  35                 bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
  36                 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
  37                 size: CONFIG_SYS_PCI1_MMIO_SIZE,
  38                 flags: PCI_REGION_MEM
  39         },
  40         {
  41                 bus_start: CONFIG_SYS_PCI1_IO_BASE,
  42                 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
  43                 size: CONFIG_SYS_PCI1_IO_SIZE,
  44                 flags: PCI_REGION_IO
  45         }
  46 };
  47
  48 void pci_init_board(void)
  49 {
  50         volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
  51         volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
  52         volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
  53         struct pci_region *reg[] = { pci_regions };
  54
  55         /* Enable all 3 PCI_CLK_OUTPUTs. */
  56         clk->occr |= 0xe0000000;
  57
  58         /*
  59          * Configure PCI Local Access Windows
  60          */
  61         pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
  62         pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
  63
  64         pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
  65         pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
  66
  67         mpc83xx_pci_init(1, reg);
  68 }
  69
  70 /*
  71  * Miscellaneous late-boot configurations
  72  */
  73 int misc_init_r(void)
  74 {
  75         int rc = 0;
  76         immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  77         fsl_lbc_t *lbus = &immap->im_lbc;
  78         u32 *mxmr = &lbus->mamr;        /* Pointer to mamr */
  79
  80         /* UPM Table Configuration Code */
  81         static uint UPMATable[] = {
  82                 /* Read Single-Beat (RSS) */
  83                 0x0fff0c00, 0x0fffdc00, 0x0fff0c05, 0xfffffc00,
  84                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
  85                 /* Read Burst (RBS) */
  86                 0x0fff0c00, 0x0ffcdc00, 0x0ffc0c00, 0x0ffc0f0c,
  87                 0x0ffccf0c, 0x0ffc0f0c, 0x0ffcce0c, 0x3ffc0c05,
  88                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  89                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
  90                 /* Write Single-Beat (WSS) */
  91                 0x0ffc0c00, 0x0ffcdc00, 0x0ffc0c05, 0xfffffc00,
  92                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
  93                 /* Write Burst (WBS) */
  94                 0x0ffc0c00, 0x0fffcc0c, 0x0fff0c00, 0x0fffcc00,
  95                 0x0fff1c00, 0x0fffcf0c, 0x0fff0f0c, 0x0fffcf0c,
  96                 0x0fff0c0c, 0x0fffcc0c, 0x0fff0c05, 0xfffffc00,
  97                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
  98                 /* Refresh Timer (RTS) */
  99                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 100                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 101                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
 102                 /* Exception Condition (EXS) */
 103                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
 104         };
 105
 106         upmconfig(UPMA, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
 107
 108         /* Set LUPWAIT to be active low and enabled */
 109         out_be32(mxmr, MxMR_UWPL | MxMR_GPL_x4DIS);
 110
 111         return rc;
 112 }
 113
 114 #if defined(CONFIG_OF_BOARD_SETUP)
 115 void ft_board_setup(void *blob, bd_t *bd)
 116 {
 117         ft_cpu_setup(blob, bd);
 118 #ifdef CONFIG_PCI
 119         ft_pci_setup(blob, bd);
 120 #endif
 121 }
 122 #endif
 123 #else /* CONFIG_NAND_SPL */
 124 void board_init_f(ulong bootflag)
 125 {
 126         NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
 127                                 CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
 128         puts("NAND boot... ");
 129         init_timebase();
 130         initdram(0);
 131         relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
 132                                   CONFIG_SYS_NAND_U_BOOT_RELOC);
 133 }
 134
 135 void board_init_r(gd_t *gd, ulong dest_addr)
 136 {
 137         nand_boot();
 138 }
 139
 140 void putc(char c)
 141 {
 142         if (gd->flags & GD_FLG_SILENT)
 143                 return;
 144
 145         if (c == '\n')
 146                 NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
 147
 148         NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
 149 }
 150 #endif