board/ti/am43xx/board.c

   1 /*
   2  * board.c
   3  *
   4  * Board functions for TI AM43XX based boards
   5  *
   6  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <i2c.h>
  13 #include <asm/errno.h>
  14 #include <spl.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <asm/arch/mux.h>
  18 #include <asm/arch/ddr_defs.h>
  19 #include <asm/arch/gpio.h>
  20 #include <asm/emif.h>
  21 #include "board.h"
  22 #include <power/pmic.h>
  23 #include <power/tps65218.h>
  24 #include <miiphy.h>
  25 #include <cpsw.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  30
  31 /*
  32  * Read header information from EEPROM into global structure.
  33  */
  34 static int read_eeprom(struct am43xx_board_id *header)
  35 {
  36         /* Check if baseboard eeprom is available */
  37         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  38                 printf("Could not probe the EEPROM at 0x%x\n",
  39                        CONFIG_SYS_I2C_EEPROM_ADDR);
  40                 return -ENODEV;
  41         }
  42
  43         /* read the eeprom using i2c */
  44         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
  45                      sizeof(struct am43xx_board_id))) {
  46                 printf("Could not read the EEPROM\n");
  47                 return -EIO;
  48         }
  49
  50         if (header->magic != 0xEE3355AA) {
  51                 /*
  52                  * read the eeprom using i2c again,
  53                  * but use only a 1 byte address
  54                  */
  55                 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
  56                              sizeof(struct am43xx_board_id))) {
  57                         printf("Could not read the EEPROM at 0x%x\n",
  58                                CONFIG_SYS_I2C_EEPROM_ADDR);
  59                         return -EIO;
  60                 }
  61
  62                 if (header->magic != 0xEE3355AA) {
  63                         printf("Incorrect magic number (0x%x) in EEPROM\n",
  64                                header->magic);
  65                         return -EINVAL;
  66                 }
  67         }
  68
  69         strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name));
  70         am43xx_board_name[sizeof(header->name)] = 0;
  71
  72         return 0;
  73 }
  74
  75 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  76
  77 #define NUM_OPPS        6
  78
  79 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
  80         {       /* 19.2 MHz */
  81                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP 50 */
  82                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  83                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP 100 */
  84                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP 120 */
  85                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP TB */
  86                 {-1, -1, -1, -1, -1, -1, -1}    /* OPP NT */
  87         },
  88         {       /* 24 MHz */
  89                 {300, 23, 1, -1, -1, -1, -1},   /* OPP 50 */
  90                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  91                 {600, 23, 1, -1, -1, -1, -1},   /* OPP 100 */
  92                 {720, 23, 1, -1, -1, -1, -1},   /* OPP 120 */
  93                 {800, 23, 1, -1, -1, -1, -1},   /* OPP TB */
  94                 {1000, 23, 1, -1, -1, -1, -1}   /* OPP NT */
  95         },
  96         {       /* 25 MHz */
  97                 {300, 24, 1, -1, -1, -1, -1},   /* OPP 50 */
  98                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  99                 {600, 24, 1, -1, -1, -1, -1},   /* OPP 100 */
 100                 {720, 24, 1, -1, -1, -1, -1},   /* OPP 120 */
 101                 {800, 24, 1, -1, -1, -1, -1},   /* OPP TB */
 102                 {1000, 24, 1, -1, -1, -1, -1}   /* OPP NT */
 103         },
 104         {       /* 26 MHz */
 105                 {300, 25, 1, -1, -1, -1, -1},   /* OPP 50 */
 106                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
 107                 {600, 25, 1, -1, -1, -1, -1},   /* OPP 100 */
 108                 {720, 25, 1, -1, -1, -1, -1},   /* OPP 120 */
 109                 {800, 25, 1, -1, -1, -1, -1},   /* OPP TB */
 110                 {1000, 25, 1, -1, -1, -1, -1}   /* OPP NT */
 111         },
 112 };
 113
 114 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
 115                 {-1, -1, -1, -1, -1, -1, -1},   /* 19.2 MHz */
 116                 {1000, 23, -1, -1, 10, 8, 4},   /* 24 MHz */
 117                 {1000, 24, -1, -1, 10, 8, 4},   /* 25 MHz */
 118                 {1000, 25, -1, -1, 10, 8, 4}    /* 26 MHz */
 119 };
 120
 121 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
 122                 {-1, -1, -1, -1, -1, -1, -1},   /* 19.2 MHz */
 123                 {960, 23, 5, -1, -1, -1, -1},   /* 24 MHz */
 124                 {960, 24, 5, -1, -1, -1, -1},   /* 25 MHz */
 125                 {960, 25, 5, -1, -1, -1, -1}    /* 26 MHz */
 126 };
 127
 128 const struct dpll_params epos_evm_dpll_ddr = {
 129                 266, 24, 1, -1, 1, -1, -1};
 130
 131 const struct dpll_params gp_evm_dpll_ddr = {
 132                 400, 23, 1, -1, 1, -1, -1};
 133
 134 const struct ctrl_ioregs ioregs_lpddr2 = {
 135         .cm0ioctl               = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
 136         .cm1ioctl               = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
 137         .cm2ioctl               = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
 138         .dt0ioctl               = LPDDR2_DATA0_IOCTRL_VALUE,
 139         .dt1ioctl               = LPDDR2_DATA0_IOCTRL_VALUE,
 140         .dt2ioctrl              = LPDDR2_DATA0_IOCTRL_VALUE,
 141         .dt3ioctrl              = LPDDR2_DATA0_IOCTRL_VALUE,
 142         .emif_sdram_config_ext  = 0x1,
 143 };
 144
 145 const struct emif_regs emif_regs_lpddr2 = {
 146         .sdram_config                   = 0x808012BA,
 147         .ref_ctrl                       = 0x0000040D,
 148         .sdram_tim1                     = 0xEA86B411,
 149         .sdram_tim2                     = 0x103A094A,
 150         .sdram_tim3                     = 0x0F6BA37F,
 151         .read_idle_ctrl                 = 0x00050000,
 152         .zq_config                      = 0x50074BE4,
 153         .temp_alert_config              = 0x0,
 154         .emif_rd_wr_lvl_rmp_win         = 0x0,
 155         .emif_rd_wr_lvl_rmp_ctl         = 0x0,
 156         .emif_rd_wr_lvl_ctl             = 0x0,
 157         .emif_ddr_phy_ctlr_1            = 0x0E084006,
 158         .emif_rd_wr_exec_thresh         = 0x00000405,
 159         .emif_ddr_ext_phy_ctrl_1        = 0x04010040,
 160         .emif_ddr_ext_phy_ctrl_2        = 0x00500050,
 161         .emif_ddr_ext_phy_ctrl_3        = 0x00500050,
 162         .emif_ddr_ext_phy_ctrl_4        = 0x00500050,
 163         .emif_ddr_ext_phy_ctrl_5        = 0x00500050
 164 };
 165
 166 const u32 ext_phy_ctrl_const_base_lpddr2[] = {
 167         0x00500050,
 168         0x00350035,
 169         0x00350035,
 170         0x00350035,
 171         0x00350035,
 172         0x00350035,
 173         0x00000000,
 174         0x00000000,
 175         0x00000000,
 176         0x00000000,
 177         0x00000000,
 178         0x00000000,
 179         0x00000000,
 180         0x00000000,
 181         0x00000000,
 182         0x00000000,
 183         0x00000000,
 184         0x00000000,
 185         0x40001000,
 186         0x08102040
 187 };
 188
 189 const struct ctrl_ioregs ioregs_ddr3 = {
 190         .cm0ioctl               = DDR3_ADDRCTRL_IOCTRL_VALUE,
 191         .cm1ioctl               = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
 192         .cm2ioctl               = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
 193         .dt0ioctl               = DDR3_DATA0_IOCTRL_VALUE,
 194         .dt1ioctl               = DDR3_DATA0_IOCTRL_VALUE,
 195         .dt2ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
 196         .dt3ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
 197         .emif_sdram_config_ext  = 0x0143,
 198 };
 199
 200 const struct emif_regs ddr3_emif_regs_400Mhz = {
 201         .sdram_config                   = 0x638413B2,
 202         .ref_ctrl                       = 0x00000C30,
 203         .sdram_tim1                     = 0xEAAAD4DB,
 204         .sdram_tim2                     = 0x266B7FDA,
 205         .sdram_tim3                     = 0x107F8678,
 206         .read_idle_ctrl                 = 0x00050000,
 207         .zq_config                      = 0x50074BE4,
 208         .temp_alert_config              = 0x0,
 209         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 210         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 211         .emif_ddr_ext_phy_ctrl_2        = 0x00400040,
 212         .emif_ddr_ext_phy_ctrl_3        = 0x00400040,
 213         .emif_ddr_ext_phy_ctrl_4        = 0x00400040,
 214         .emif_ddr_ext_phy_ctrl_5        = 0x00400040,
 215         .emif_rd_wr_lvl_rmp_win         = 0x0,
 216         .emif_rd_wr_lvl_rmp_ctl         = 0x0,
 217         .emif_rd_wr_lvl_ctl             = 0x0,
 218         .emif_rd_wr_exec_thresh         = 0x00000405
 219 };
 220
 221 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
 222         .sdram_config                   = 0x638413b2,
 223         .sdram_config2                  = 0x00000000,
 224         .ref_ctrl                       = 0x00000c30,
 225         .sdram_tim1                     = 0xeaaad4db,
 226         .sdram_tim2                     = 0x266b7fda,
 227         .sdram_tim3                     = 0x107f8678,
 228         .read_idle_ctrl                 = 0x00050000,
 229         .zq_config                      = 0x50074be4,
 230         .temp_alert_config              = 0x0,
 231         .emif_ddr_phy_ctlr_1            = 0x0e084008,
 232         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 233         .emif_ddr_ext_phy_ctrl_2        = 0x89,
 234         .emif_ddr_ext_phy_ctrl_3        = 0x90,
 235         .emif_ddr_ext_phy_ctrl_4        = 0x8e,
 236         .emif_ddr_ext_phy_ctrl_5        = 0x8d,
 237         .emif_rd_wr_lvl_rmp_win         = 0x0,
 238         .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
 239         .emif_rd_wr_lvl_ctl             = 0x00000000,
 240         .emif_rd_wr_exec_thresh         = 0x00000000,
 241 };
 242
 243 const u32 ext_phy_ctrl_const_base_ddr3[] = {
 244         0x00400040,
 245         0x00350035,
 246         0x00350035,
 247         0x00350035,
 248         0x00350035,
 249         0x00350035,
 250         0x00000000,
 251         0x00000000,
 252         0x00000000,
 253         0x00000000,
 254         0x00000000,
 255         0x00340034,
 256         0x00340034,
 257         0x00340034,
 258         0x00340034,
 259         0x00340034,
 260         0x0,
 261         0x0,
 262         0x40000000,
 263         0x08102040
 264 };
 265
 266 static const u32 ext_phy_ctrl_const_base_ddr3_sk[] = {
 267         /* first 5 are taken care by emif_regs */
 268         0x00700070,
 269
 270         0x00350035,
 271         0x00350035,
 272         0x00350035,
 273         0x00350035,
 274         0x00350035,
 275
 276         0x00000000,
 277         0x00000000,
 278         0x00000000,
 279         0x00000000,
 280         0x00000000,
 281
 282         0x00150015,
 283         0x00150015,
 284         0x00150015,
 285         0x00150015,
 286         0x00150015,
 287
 288         0x00800080,
 289         0x00800080,
 290
 291         0x40000000,
 292
 293         0x08102040,
 294
 295         0x00000000,
 296         0x00000000,
 297         0x00000000,
 298         0x00000000,
 299         0x00000000,
 300         0x00000000,
 301         0x00000000,
 302         0x00000000,
 303         0x00000000,
 304         0x00000000,
 305         0x00000000,
 306 };
 307
 308 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
 309 {
 310         if (board_is_eposevm()) {
 311                 *regs = ext_phy_ctrl_const_base_lpddr2;
 312                 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
 313         } else if (board_is_gpevm()) {
 314                 *regs = ext_phy_ctrl_const_base_ddr3;
 315                 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
 316         } else if (board_is_sk()) {
 317                 *regs = ext_phy_ctrl_const_base_ddr3_sk;
 318                 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_sk);
 319         }
 320
 321         return;
 322 }
 323
 324 const struct dpll_params *get_dpll_ddr_params(void)
 325 {
 326         if (board_is_eposevm())
 327                 return &epos_evm_dpll_ddr;
 328         else if (board_is_gpevm() || board_is_sk())
 329                 return &gp_evm_dpll_ddr;
 330
 331         printf(" Board '%s' not supported\n", am43xx_board_name);
 332         return NULL;
 333 }
 334
 335 /*
 336  * get_sys_clk_index : returns the index of the sys_clk read from
 337  *                      ctrl status register. This value is either
 338  *                      read from efuse or sysboot pins.
 339  */
 340 static u32 get_sys_clk_index(void)
 341 {
 342         struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
 343         u32 ind = readl(&ctrl->statusreg), src;
 344
 345         src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
 346         if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
 347                 return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
 348                         CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
 349         else /* Value read from SYS BOOT pins */
 350                 return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
 351                         CTRL_SYSBOOT_15_14_SHIFT);
 352 }
 353
 354 /*
 355  * get_opp_offset:
 356  * Returns the index for safest OPP of the device to boot.
 357  * max_off:     Index of the MAX OPP in DEV ATTRIBUTE register.
 358  * min_off:     Index of the MIN OPP in DEV ATTRIBUTE register.
 359  * This data is read from dev_attribute register which is e-fused.
 360  * A'1' in bit indicates OPP disabled and not available, a '0' indicates
 361  * OPP available. Lowest OPP starts with min_off. So returning the
 362  * bit with rightmost '0'.
 363  */
 364 static int get_opp_offset(int max_off, int min_off)
 365 {
 366         struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
 367         int opp, offset, i;
 368
 369         /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
 370         opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
 371
 372         for (i = max_off; i >= min_off; i--) {
 373                 offset = opp & (1 << i);
 374                 if (!offset)
 375                         return i;
 376         }
 377
 378         return min_off;
 379 }
 380
 381 const struct dpll_params *get_dpll_mpu_params(void)
 382 {
 383         int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
 384         u32 ind = get_sys_clk_index();
 385
 386         return &dpll_mpu[ind][opp];
 387 }
 388
 389 const struct dpll_params *get_dpll_core_params(void)
 390 {
 391         int ind = get_sys_clk_index();
 392
 393         return &dpll_core[ind];
 394 }
 395
 396 const struct dpll_params *get_dpll_per_params(void)
 397 {
 398         int ind = get_sys_clk_index();
 399
 400         return &dpll_per[ind];
 401 }
 402
 403 void scale_vcores(void)
 404 {
 405         const struct dpll_params *mpu_params;
 406         int mpu_vdd;
 407         struct am43xx_board_id header;
 408
 409         enable_i2c0_pin_mux();
 410         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 411         if (read_eeprom(&header) < 0)
 412                 puts("Could not get board ID.\n");
 413
 414         /* Get the frequency */
 415         mpu_params = get_dpll_mpu_params();
 416
 417         if (i2c_probe(TPS65218_CHIP_PM))
 418                 return;
 419
 420         if (mpu_params->m == 1000) {
 421                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
 422         } else if (mpu_params->m == 600) {
 423                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
 424         } else {
 425                 puts("Unknown MPU clock, not scaling\n");
 426                 return;
 427         }
 428
 429         /* Set DCDC1 (CORE) voltage to 1.1V */
 430         if (tps65218_voltage_update(TPS65218_DCDC1,
 431                                     TPS65218_DCDC_VOLT_SEL_1100MV)) {
 432                 puts("tps65218_voltage_update failure\n");
 433                 return;
 434         }
 435
 436         /* Set DCDC2 (MPU) voltage */
 437         if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
 438                 puts("tps65218_voltage_update failure\n");
 439                 return;
 440         }
 441 }
 442
 443 void set_uart_mux_conf(void)
 444 {
 445         enable_uart0_pin_mux();
 446 }
 447
 448 void set_mux_conf_regs(void)
 449 {
 450         enable_board_pin_mux();
 451 }
 452
 453 static void enable_vtt_regulator(void)
 454 {
 455         u32 temp;
 456
 457         /* enable module */
 458         writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
 459
 460         /* enable output for GPIO5_7 */
 461         writel(GPIO_SETDATAOUT(7),
 462                AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
 463         temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 464         temp = temp & ~(GPIO_OE_ENABLE(7));
 465         writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 466 }
 467
 468 void sdram_init(void)
 469 {
 470         /*
 471          * EPOS EVM has 1GB LPDDR2 connected to EMIF.
 472          * GP EMV has 1GB DDR3 connected to EMIF
 473          * along with VTT regulator.
 474          */
 475         if (board_is_eposevm()) {
 476                 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
 477         } else if (board_is_gpevm()) {
 478                 enable_vtt_regulator();
 479                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 480                            &ddr3_emif_regs_400Mhz, 0);
 481         } else if (board_is_sk()) {
 482                 config_ddr(400, &ioregs_ddr3, NULL, NULL,
 483                            &ddr3_sk_emif_regs_400Mhz, 0);
 484         }
 485 }
 486 #endif
 487
 488 /* setup board specific PMIC */
 489 int power_init_board(void)
 490 {
 491         struct pmic *p;
 492
 493         power_tps65218_init(I2C_PMIC);
 494         p = pmic_get("TPS65218_PMIC");
 495         if (p && !pmic_probe(p))
 496                 puts("PMIC:  TPS65218\n");
 497
 498         return 0;
 499 }
 500
 501 int board_init(void)
 502 {
 503         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 504
 505         return 0;
 506 }
 507
 508 #ifdef CONFIG_BOARD_LATE_INIT
 509 int board_late_init(void)
 510 {
 511 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 512         char safe_string[HDR_NAME_LEN + 1];
 513         struct am43xx_board_id header;
 514
 515         if (read_eeprom(&header) < 0)
 516                 puts("Could not get board ID.\n");
 517
 518         /* Now set variables based on the header. */
 519         strncpy(safe_string, (char *)header.name, sizeof(header.name));
 520         safe_string[sizeof(header.name)] = 0;
 521         setenv("board_name", safe_string);
 522
 523         strncpy(safe_string, (char *)header.version, sizeof(header.version));
 524         safe_string[sizeof(header.version)] = 0;
 525         setenv("board_rev", safe_string);
 526 #endif
 527         return 0;
 528 }
 529 #endif
 530
 531 #ifdef CONFIG_DRIVER_TI_CPSW
 532
 533 static void cpsw_control(int enabled)
 534 {
 535         /* Additional controls can be added here */
 536         return;
 537 }
 538
 539 static struct cpsw_slave_data cpsw_slaves[] = {
 540         {
 541                 .slave_reg_ofs  = 0x208,
 542                 .sliver_reg_ofs = 0xd80,
 543                 .phy_addr       = 16,
 544         },
 545         {
 546                 .slave_reg_ofs  = 0x308,
 547                 .sliver_reg_ofs = 0xdc0,
 548                 .phy_addr       = 1,
 549         },
 550 };
 551
 552 static struct cpsw_platform_data cpsw_data = {
 553         .mdio_base              = CPSW_MDIO_BASE,
 554         .cpsw_base              = CPSW_BASE,
 555         .mdio_div               = 0xff,
 556         .channels               = 8,
 557         .cpdma_reg_ofs          = 0x800,
 558         .slaves                 = 1,
 559         .slave_data             = cpsw_slaves,
 560         .ale_reg_ofs            = 0xd00,
 561         .ale_entries            = 1024,
 562         .host_port_reg_ofs      = 0x108,
 563         .hw_stats_reg_ofs       = 0x900,
 564         .bd_ram_ofs             = 0x2000,
 565         .mac_control            = (1 << 5),
 566         .control                = cpsw_control,
 567         .host_port_num          = 0,
 568         .version                = CPSW_CTRL_VERSION_2,
 569 };
 570
 571 int board_eth_init(bd_t *bis)
 572 {
 573         int rv;
 574         uint8_t mac_addr[6];
 575         uint32_t mac_hi, mac_lo;
 576
 577         /* try reading mac address from efuse */
 578         mac_lo = readl(&cdev->macid0l);
 579         mac_hi = readl(&cdev->macid0h);
 580         mac_addr[0] = mac_hi & 0xFF;
 581         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 582         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 583         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 584         mac_addr[4] = mac_lo & 0xFF;
 585         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 586
 587         if (!getenv("ethaddr")) {
 588                 puts("<ethaddr> not set. Validating first E-fuse MAC\n");
 589                 if (is_valid_ether_addr(mac_addr))
 590                         eth_setenv_enetaddr("ethaddr", mac_addr);
 591         }
 592
 593         mac_lo = readl(&cdev->macid1l);
 594         mac_hi = readl(&cdev->macid1h);
 595         mac_addr[0] = mac_hi & 0xFF;
 596         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 597         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 598         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 599         mac_addr[4] = mac_lo & 0xFF;
 600         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 601
 602         if (!getenv("eth1addr")) {
 603                 if (is_valid_ether_addr(mac_addr))
 604                         eth_setenv_enetaddr("eth1addr", mac_addr);
 605         }
 606
 607         if (board_is_eposevm()) {
 608                 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
 609                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
 610                 cpsw_slaves[0].phy_addr = 16;
 611         } else if (board_is_sk()) {
 612                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 613                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
 614                 cpsw_slaves[0].phy_addr = 4;
 615                 cpsw_slaves[1].phy_addr = 5;
 616         } else {
 617                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 618                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
 619                 cpsw_slaves[0].phy_addr = 0;
 620         }
 621
 622         rv = cpsw_register(&cpsw_data);
 623         if (rv < 0)
 624                 printf("Error %d registering CPSW switch\n", rv);
 625
 626         return rv;
 627 }
 628 #endif