board/ti/dra7xx/evm.c

   1 /*
   2  * (C) Copyright 2013
   3  * Texas Instruments Incorporated, <www.ti.com>
   4  *
   5  * Lokesh Vutla <lokeshvutla@ti.com>
   6  *
   7  * Based on previous work by:
   8  * Aneesh V       <aneesh@ti.com>
   9  * Steve Sakoman  <steve@sakoman.com>
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13 #include <common.h>
  14 #include <palmas.h>
  15 #include <sata.h>
  16 #include <asm/gpio.h>
  17 #include <usb.h>
  18 #include <linux/usb/gadget.h>
  19 #include <asm/arch/gpio.h>
  20 #include <asm/arch/dra7xx_iodelay.h>
  21 #include <asm/arch/sys_proto.h>
  22 #include <asm/arch/mmc_host_def.h>
  23 #include <asm/arch/sata.h>
  24 #include <environment.h>
  25 #include <dwc3-uboot.h>
  26 #include <dwc3-omap-uboot.h>
  27 #include <ti-usb-phy-uboot.h>
  28
  29 #include "mux_data.h"
  30
  31 #ifdef CONFIG_DRIVER_TI_CPSW
  32 #include <cpsw.h>
  33 #endif
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 /* GPIO 7_11 */
  38 #define GPIO_DDR_VTT_EN 203
  39
  40 const struct omap_sysinfo sysinfo = {
  41         "Board: DRA7xx\n"
  42 };
  43
  44 /**
  45  * @brief board_init
  46  *
  47  * @return 0
  48  */
  49 int board_init(void)
  50 {
  51         gpmc_init();
  52         gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
  53
  54         return 0;
  55 }
  56
  57 int board_late_init(void)
  58 {
  59 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  60         u32 id[4];
  61
  62         if (omap_revision() == DRA722_ES1_0)
  63                 setenv("board_name", "dra72x");
  64         else
  65                 setenv("board_name", "dra7xx");
  66
  67         id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
  68         id[1] = readl((*ctrl)->control_std_fuse_die_id_1);
  69         usb_set_serial_num_from_die_id(id);
  70 #endif
  71         return 0;
  72 }
  73
  74 void set_muxconf_regs_essential(void)
  75 {
  76         do_set_mux32((*ctrl)->control_padconf_core_base,
  77                      early_padconf, ARRAY_SIZE(early_padconf));
  78 }
  79
  80 #ifdef CONFIG_IODELAY_RECALIBRATION
  81 void recalibrate_iodelay(void)
  82 {
  83         struct pad_conf_entry const *pads;
  84         struct iodelay_cfg_entry const *iodelay;
  85         int npads, niodelays;
  86
  87         switch (omap_revision()) {
  88         case DRA722_ES1_0:
  89                 pads = core_padconf_array_essential;
  90                 npads = ARRAY_SIZE(core_padconf_array_essential);
  91                 iodelay = iodelay_cfg_array;
  92                 niodelays = ARRAY_SIZE(iodelay_cfg_array);
  93                 break;
  94         case DRA752_ES1_0:
  95         case DRA752_ES1_1:
  96                 pads = dra74x_core_padconf_array;
  97                 npads = ARRAY_SIZE(dra74x_core_padconf_array);
  98                 iodelay = dra742_es1_1_iodelay_cfg_array;
  99                 niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
 100                 break;
 101         default:
 102         case DRA752_ES2_0:
 103                 pads = dra74x_core_padconf_array;
 104                 npads = ARRAY_SIZE(dra74x_core_padconf_array);
 105                 iodelay = dra742_es2_0_iodelay_cfg_array;
 106                 niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
 107                 break;
 108         }
 109         __recalibrate_iodelay(pads, npads, iodelay, niodelays);
 110 }
 111 #endif
 112
 113 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 114 int board_mmc_init(bd_t *bis)
 115 {
 116         omap_mmc_init(0, 0, 0, -1, -1);
 117         omap_mmc_init(1, 0, 0, -1, -1);
 118         return 0;
 119 }
 120 #endif
 121
 122 #ifdef CONFIG_USB_DWC3
 123 static struct dwc3_device usb_otg_ss1 = {
 124         .maximum_speed = USB_SPEED_SUPER,
 125         .base = DRA7_USB_OTG_SS1_BASE,
 126         .tx_fifo_resize = false,
 127         .index = 0,
 128 };
 129
 130 static struct dwc3_omap_device usb_otg_ss1_glue = {
 131         .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
 132         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 133         .vbus_id_status = OMAP_DWC3_VBUS_VALID,
 134         .index = 0,
 135 };
 136
 137 static struct ti_usb_phy_device usb_phy1_device = {
 138         .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
 139         .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
 140         .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
 141         .index = 0,
 142 };
 143
 144 static struct dwc3_device usb_otg_ss2 = {
 145         .maximum_speed = USB_SPEED_SUPER,
 146         .base = DRA7_USB_OTG_SS2_BASE,
 147         .tx_fifo_resize = false,
 148         .index = 1,
 149 };
 150
 151 static struct dwc3_omap_device usb_otg_ss2_glue = {
 152         .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
 153         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 154         .vbus_id_status = OMAP_DWC3_VBUS_VALID,
 155         .index = 1,
 156 };
 157
 158 static struct ti_usb_phy_device usb_phy2_device = {
 159         .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
 160         .index = 1,
 161 };
 162
 163 int board_usb_init(int index, enum usb_init_type init)
 164 {
 165         switch (index) {
 166         case 0:
 167                 if (init == USB_INIT_DEVICE) {
 168                         usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
 169                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 170                 } else {
 171                         usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
 172                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
 173                 }
 174
 175                 ti_usb_phy_uboot_init(&usb_phy1_device);
 176                 dwc3_omap_uboot_init(&usb_otg_ss1_glue);
 177                 dwc3_uboot_init(&usb_otg_ss1);
 178                 break;
 179         case 1:
 180                 if (init == USB_INIT_DEVICE) {
 181                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 182                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 183                 } else {
 184                         usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
 185                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
 186                 }
 187
 188                 ti_usb_phy_uboot_init(&usb_phy2_device);
 189                 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 190                 dwc3_uboot_init(&usb_otg_ss2);
 191                 break;
 192         default:
 193                 printf("Invalid Controller Index\n");
 194         }
 195
 196         return 0;
 197 }
 198
 199 int board_usb_cleanup(int index, enum usb_init_type init)
 200 {
 201         switch (index) {
 202         case 0:
 203         case 1:
 204                 ti_usb_phy_uboot_exit(index);
 205                 dwc3_uboot_exit(index);
 206                 dwc3_omap_uboot_exit(index);
 207                 break;
 208         default:
 209                 printf("Invalid Controller Index\n");
 210         }
 211         return 0;
 212 }
 213
 214 int usb_gadget_handle_interrupts(int index)
 215 {
 216         u32 status;
 217
 218         status = dwc3_omap_uboot_interrupt_status(index);
 219         if (status)
 220                 dwc3_uboot_handle_interrupt(index);
 221
 222         return 0;
 223 }
 224 #endif
 225
 226 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 227 int spl_start_uboot(void)
 228 {
 229         /* break into full u-boot on 'c' */
 230         if (serial_tstc() && serial_getc() == 'c')
 231                 return 1;
 232
 233 #ifdef CONFIG_SPL_ENV_SUPPORT
 234         env_init();
 235         env_relocate_spec();
 236         if (getenv_yesno("boot_os") != 1)
 237                 return 1;
 238 #endif
 239
 240         return 0;
 241 }
 242 #endif
 243
 244 #ifdef CONFIG_DRIVER_TI_CPSW
 245 extern u32 *const omap_si_rev;
 246
 247 static void cpsw_control(int enabled)
 248 {
 249         /* VTP can be added here */
 250
 251         return;
 252 }
 253
 254 static struct cpsw_slave_data cpsw_slaves[] = {
 255         {
 256                 .slave_reg_ofs  = 0x208,
 257                 .sliver_reg_ofs = 0xd80,
 258                 .phy_addr       = 2,
 259         },
 260         {
 261                 .slave_reg_ofs  = 0x308,
 262                 .sliver_reg_ofs = 0xdc0,
 263                 .phy_addr       = 3,
 264         },
 265 };
 266
 267 static struct cpsw_platform_data cpsw_data = {
 268         .mdio_base              = CPSW_MDIO_BASE,
 269         .cpsw_base              = CPSW_BASE,
 270         .mdio_div               = 0xff,
 271         .channels               = 8,
 272         .cpdma_reg_ofs          = 0x800,
 273         .slaves                 = 2,
 274         .slave_data             = cpsw_slaves,
 275         .ale_reg_ofs            = 0xd00,
 276         .ale_entries            = 1024,
 277         .host_port_reg_ofs      = 0x108,
 278         .hw_stats_reg_ofs       = 0x900,
 279         .bd_ram_ofs             = 0x2000,
 280         .mac_control            = (1 << 5),
 281         .control                = cpsw_control,
 282         .host_port_num          = 0,
 283         .version                = CPSW_CTRL_VERSION_2,
 284 };
 285
 286 int board_eth_init(bd_t *bis)
 287 {
 288         int ret;
 289         uint8_t mac_addr[6];
 290         uint32_t mac_hi, mac_lo;
 291         uint32_t ctrl_val;
 292
 293         /* try reading mac address from efuse */
 294         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
 295         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
 296         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 297         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 298         mac_addr[2] = mac_hi & 0xFF;
 299         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 300         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 301         mac_addr[5] = mac_lo & 0xFF;
 302
 303         if (!getenv("ethaddr")) {
 304                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 305
 306                 if (is_valid_ethaddr(mac_addr))
 307                         eth_setenv_enetaddr("ethaddr", mac_addr);
 308         }
 309
 310         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
 311         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
 312         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 313         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 314         mac_addr[2] = mac_hi & 0xFF;
 315         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 316         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 317         mac_addr[5] = mac_lo & 0xFF;
 318
 319         if (!getenv("eth1addr")) {
 320                 if (is_valid_ethaddr(mac_addr))
 321                         eth_setenv_enetaddr("eth1addr", mac_addr);
 322         }
 323
 324         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
 325         ctrl_val |= 0x22;
 326         writel(ctrl_val, (*ctrl)->control_core_control_io1);
 327
 328         if (*omap_si_rev == DRA722_ES1_0)
 329                 cpsw_data.active_slave = 1;
 330
 331         ret = cpsw_register(&cpsw_data);
 332         if (ret < 0)
 333                 printf("Error %d registering CPSW switch\n", ret);
 334
 335         return ret;
 336 }
 337 #endif
 338
 339 #ifdef CONFIG_BOARD_EARLY_INIT_F
 340 /* VTT regulator enable */
 341 static inline void vtt_regulator_enable(void)
 342 {
 343         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
 344                 return;
 345
 346         /* Do not enable VTT for DRA722 */
 347         if (omap_revision() == DRA722_ES1_0)
 348                 return;
 349
 350         /*
 351          * EVM Rev G and later use gpio7_11 for DDR3 termination.
 352          * This is safe enough to do on older revs.
 353          */
 354         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 355         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 356 }
 357
 358 int board_early_init_f(void)
 359 {
 360         vtt_regulator_enable();
 361         return 0;
 362 }
 363 #endif