2 * Keystone : Board initialization
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <fdt_support.h>
15 #include <asm/arch/ddr3.h>
16 #include <asm/arch/psc_defs.h>
17 #include <asm/ti-common/ti-aemif.h>
18 #include <asm/ti-common/keystone_net.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 static struct aemif_config aemif_configs[] = {
24 .mode = AEMIF_MODE_NAND,
32 .width = AEMIF_WIDTH_8,
40 ddr3_size = ddr3_init();
42 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
43 CONFIG_MAX_RAM_BANK_SIZE);
44 aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
45 ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
51 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
56 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
57 int get_eth_env_param(char *env_name)
62 env = getenv(env_name);
64 res = simple_strtol(env, NULL, 0);
69 int board_eth_init(bd_t *bis)
74 char link_type_name[32];
76 /* By default, select PA PLL clock as PA clock source */
77 if (psc_enable_module(KS2_LPSC_PA))
79 if (psc_enable_module(KS2_LPSC_CPGMAC))
81 if (psc_enable_module(KS2_LPSC_CRYPTO))
84 port_num = get_num_eth_ports();
86 for (j = 0; j < port_num; j++) {
87 sprintf(link_type_name, "sgmii%d_link_type", j);
88 res = get_eth_env_param(link_type_name);
90 eth_priv_cfg[j].sgmii_link_type = res;
92 keystone2_emac_initialize(ð_priv_cfg[j]);
99 #ifdef CONFIG_SPL_BUILD
100 void spl_board_init(void)
102 spl_init_keystone_plls();
103 preloader_console_init();
106 u32 spl_boot_device(void)
108 #if defined(CONFIG_SPL_SPI_LOAD)
109 return BOOT_DEVICE_SPI;
111 puts("Unknown boot device\n");
117 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
118 int ft_board_setup(void *blob, bd_t *bd)
128 int unitrd_fixup = 0;
130 env = getenv("mem_lpae");
131 lpae = env && simple_strtol(env, NULL, 0);
132 env = getenv("uinitrd_fixup");
133 unitrd_fixup = env && simple_strtol(env, NULL, 0);
137 env = getenv("ddr3a_size");
139 ddr3a_size = simple_strtol(env, NULL, 10);
140 if ((ddr3a_size != 8) && (ddr3a_size != 4))
145 start[0] = bd->bi_dram[0].start;
146 size[0] = bd->bi_dram[0].size;
148 /* adjust memory start address for LPAE */
150 start[0] -= CONFIG_SYS_SDRAM_BASE;
151 start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
154 if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
155 size[1] = ((u64)ddr3a_size - 2) << 30;
156 start[1] = 0x880000000;
160 /* reserve memory at start of bank */
161 env = getenv("mem_reserve_head");
163 start[0] += ustrtoul(env, &endp, 0);
164 size[0] -= ustrtoul(env, &endp, 0);
167 env = getenv("mem_reserve");
169 size[0] -= ustrtoul(env, &endp, 0);
171 fdt_fixup_memory_banks(blob, start, size, nbanks);
173 /* Fix up the initrd */
174 if (lpae && unitrd_fixup) {
177 u64 initrd_start, initrd_end;
179 nodeoffset = fdt_path_offset(blob, "/chosen");
180 if (nodeoffset >= 0) {
181 prop1 = (u32 *)fdt_getprop(blob, nodeoffset,
182 "linux,initrd-start", NULL);
183 prop2 = (u32 *)fdt_getprop(blob, nodeoffset,
184 "linux,initrd-end", NULL);
185 if (prop1 && prop2) {
186 initrd_start = __be32_to_cpu(*prop1);
187 initrd_start -= CONFIG_SYS_SDRAM_BASE;
188 initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
189 initrd_start = __cpu_to_be64(initrd_start);
190 initrd_end = __be32_to_cpu(*prop2);
191 initrd_end -= CONFIG_SYS_SDRAM_BASE;
192 initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
193 initrd_end = __cpu_to_be64(initrd_end);
195 err = fdt_delprop(blob, nodeoffset,
196 "linux,initrd-start");
198 puts("error deleting initrd-start\n");
200 err = fdt_delprop(blob, nodeoffset,
203 puts("error deleting initrd-end\n");
205 err = fdt_setprop(blob, nodeoffset,
206 "linux,initrd-start",
208 sizeof(initrd_start));
210 puts("error adding initrd-start\n");
212 err = fdt_setprop(blob, nodeoffset,
217 puts("error adding linux,initrd-end\n");
225 void ft_board_setup_ex(void *blob, bd_t *bd)
232 env = getenv("mem_lpae");
233 lpae = env && simple_strtol(env, NULL, 0);
237 * the initrd and other reserved memory areas are
238 * embedded in in the DTB itslef. fix up these addresses
241 reserve_start = (u64 *)((char *)blob +
242 fdt_off_mem_rsvmap(blob));
244 *reserve_start = __cpu_to_be64(*reserve_start);
245 size = __cpu_to_be64(*(reserve_start + 1));
247 *reserve_start -= CONFIG_SYS_SDRAM_BASE;
249 CONFIG_SYS_LPAE_SDRAM_BASE;
251 __cpu_to_be64(*reserve_start);
259 ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);