board/ti/ks2_evm/board_k2e.c

   1 /*
   2  * K2E EVM : Board initialization
   3  *
   4  * (C) Copyright 2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/arch/ddr3.h>
  12 #include <asm/arch/hardware.h>
  13 #include <asm/ti-common/keystone_net.h>
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 unsigned int external_clk[ext_clk_count] = {
  18         [sys_clk]       = 100000000,
  19         [alt_core_clk]  = 100000000,
  20         [pa_clk]        = 100000000,
  21         [ddr3_clk]      = 100000000,
  22         [mcm_clk]       = 312500000,
  23         [pcie_clk]      = 100000000,
  24         [sgmii_clk]     = 156250000,
  25         [xgmii_clk]     = 156250000,
  26         [usb_clk]       = 100000000,
  27 };
  28
  29 static struct pll_init_data core_pll_config[NUM_SPDS] = {
  30         [SPD800]        = CORE_PLL_800,
  31         [SPD850]        = CORE_PLL_850,
  32         [SPD1000]       = CORE_PLL_1000,
  33         [SPD1250]       = CORE_PLL_1250,
  34         [SPD1350]       = CORE_PLL_1350,
  35         [SPD1400]       = CORE_PLL_1400,
  36         [SPD1500]       = CORE_PLL_1500,
  37 };
  38
  39 /* DEV and ARM speed definitions as specified in DEVSPEED register */
  40 int speeds[DEVSPEED_NUMSPDS] = {
  41         SPD850,
  42         SPD1000,
  43         SPD1250,
  44         SPD1350,
  45         SPD1400,
  46         SPD1500,
  47         SPD1400,
  48         SPD1350,
  49         SPD1250,
  50         SPD1000,
  51         SPD850,
  52         SPD800,
  53 };
  54
  55 s16 divn_val[16] = {
  56         0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
  57 };
  58
  59 static struct pll_init_data pa_pll_config =
  60         PASS_PLL_1000;
  61
  62 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
  63 struct eth_priv_t eth_priv_cfg[] = {
  64         {
  65                 .int_name        = "K2E_EMAC0",
  66                 .rx_flow         = 0,
  67                 .phy_addr        = 0,
  68                 .slave_port      = 1,
  69                 .sgmii_link_type = SGMII_LINK_MAC_PHY,
  70         },
  71         {
  72                 .int_name        = "K2E_EMAC1",
  73                 .rx_flow         = 8,
  74                 .phy_addr        = 1,
  75                 .slave_port      = 2,
  76                 .sgmii_link_type = SGMII_LINK_MAC_PHY,
  77         },
  78         {
  79                 .int_name        = "K2E_EMAC2",
  80                 .rx_flow         = 16,
  81                 .phy_addr        = 2,
  82                 .slave_port      = 3,
  83                 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
  84         },
  85         {
  86                 .int_name        = "K2E_EMAC3",
  87                 .rx_flow         = 24,
  88                 .phy_addr        = 3,
  89                 .slave_port      = 4,
  90                 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
  91         },
  92         {
  93                 .int_name        = "K2E_EMAC4",
  94                 .rx_flow         = 32,
  95                 .phy_addr        = 4,
  96                 .slave_port      = 5,
  97                 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
  98         },
  99         {
 100                 .int_name        = "K2E_EMAC5",
 101                 .rx_flow         = 40,
 102                 .phy_addr        = 5,
 103                 .slave_port      = 6,
 104                 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
 105         },
 106         {
 107                 .int_name        = "K2E_EMAC6",
 108                 .rx_flow         = 48,
 109                 .phy_addr        = 6,
 110                 .slave_port      = 7,
 111                 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
 112         },
 113         {
 114                 .int_name        = "K2E_EMAC7",
 115                 .rx_flow         = 56,
 116                 .phy_addr        = 7,
 117                 .slave_port      = 8,
 118                 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
 119         },
 120 };
 121
 122 int get_num_eth_ports(void)
 123 {
 124         return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
 125 }
 126 #endif
 127
 128 #if defined(CONFIG_BOARD_EARLY_INIT_F)
 129 int board_early_init_f(void)
 130 {
 131         int speed;
 132
 133         speed = get_max_dev_speed();
 134         init_pll(&core_pll_config[speed]);
 135
 136         init_pll(&pa_pll_config);
 137
 138         return 0;
 139 }
 140 #endif
 141
 142 #ifdef CONFIG_SPL_BUILD
 143 static struct pll_init_data spl_pll_config[] = {
 144         CORE_PLL_800,
 145 };
 146
 147 void spl_init_keystone_plls(void)
 148 {
 149         init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
 150 }
 151 #endif