board/ti/ks2_evm/board_k2hk.c

   1 /*
   2  * K2HK EVM : Board initialization
   3  *
   4  * (C) Copyright 2012-2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/hardware.h>
  13 #include <asm/ti-common/keystone_net.h>
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 unsigned int external_clk[ext_clk_count] = {
  18         [sys_clk]       =       122880000,
  19         [alt_core_clk]  =       125000000,
  20         [pa_clk]        =       122880000,
  21         [tetris_clk]    =       125000000,
  22         [ddr3a_clk]     =       100000000,
  23         [ddr3b_clk]     =       100000000,
  24         [mcm_clk]       =       312500000,
  25         [pcie_clk]      =       100000000,
  26         [sgmii_srio_clk] =      156250000,
  27         [xgmii_clk]     =       156250000,
  28         [usb_clk]       =       100000000,
  29         [rp1_clk]       =       123456789
  30 };
  31
  32 static struct pll_init_data core_pll_config[NUM_SPDS] = {
  33         [SPD800]        = CORE_PLL_799,
  34         [SPD1000]       = CORE_PLL_999,
  35         [SPD1200]       = CORE_PLL_1200,
  36 };
  37
  38 s16 divn_val[16] = {
  39         0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
  40 };
  41
  42 static struct pll_init_data tetris_pll_config[] = {
  43         [SPD800]        = TETRIS_PLL_800,
  44         [SPD1000]       = TETRIS_PLL_1000,
  45         [SPD1200]       = TETRIS_PLL_1200,
  46         [SPD1350]       = TETRIS_PLL_1350,
  47         [SPD1400]       = TETRIS_PLL_1400,
  48 };
  49
  50 static struct pll_init_data pa_pll_config =
  51         PASS_PLL_983;
  52
  53 struct pll_init_data *get_pll_init_data(int pll)
  54 {
  55         int speed;
  56         struct pll_init_data *data;
  57
  58         switch (pll) {
  59         case MAIN_PLL:
  60                 speed = get_max_dev_speed();
  61                 data = &core_pll_config[speed];
  62                 break;
  63         case TETRIS_PLL:
  64                 speed = get_max_arm_speed();
  65                 data = &tetris_pll_config[speed];
  66                 break;
  67         case PASS_PLL:
  68                 data = &pa_pll_config;
  69                 break;
  70         default:
  71                 data = NULL;
  72         }
  73
  74         return data;
  75 }
  76
  77 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
  78 struct eth_priv_t eth_priv_cfg[] = {
  79         {
  80                 .int_name       = "K2HK_EMAC",
  81                 .rx_flow        = 22,
  82                 .phy_addr       = 0,
  83                 .slave_port     = 1,
  84                 .sgmii_link_type = SGMII_LINK_MAC_PHY,
  85         },
  86         {
  87                 .int_name       = "K2HK_EMAC1",
  88                 .rx_flow        = 23,
  89                 .phy_addr       = 1,
  90                 .slave_port     = 2,
  91                 .sgmii_link_type = SGMII_LINK_MAC_PHY,
  92         },
  93         {
  94                 .int_name       = "K2HK_EMAC2",
  95                 .rx_flow        = 24,
  96                 .phy_addr       = 2,
  97                 .slave_port     = 3,
  98                 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
  99         },
 100         {
 101                 .int_name       = "K2HK_EMAC3",
 102                 .rx_flow        = 25,
 103                 .phy_addr       = 3,
 104                 .slave_port     = 4,
 105                 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
 106         },
 107 };
 108
 109 int get_num_eth_ports(void)
 110 {
 111         return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
 112 }
 113 #endif
 114
 115 #ifdef CONFIG_BOARD_EARLY_INIT_F
 116 int board_early_init_f(void)
 117 {
 118         init_plls();
 119
 120         return 0;
 121 }
 122 #endif
 123
 124 #ifdef CONFIG_SPL_BUILD
 125 void spl_init_keystone_plls(void)
 126 {
 127         init_plls();
 128 }
 129 #endif