ARM: keystone2: Cleanup PLL init code
[karo-tx-uboot.git] / board / ti / ks2_evm / board_k2hk.c
1 /*
2  * K2HK EVM : Board initialization
3  *
4  * (C) Copyright 2012-2014
5  *     Texas Instruments Incorporated, <www.ti.com>
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9
10 #include <common.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/hardware.h>
13 #include <asm/ti-common/keystone_net.h>
14
15 DECLARE_GLOBAL_DATA_PTR;
16
17 unsigned int external_clk[ext_clk_count] = {
18         [sys_clk]       =       122880000,
19         [alt_core_clk]  =       125000000,
20         [pa_clk]        =       122880000,
21         [tetris_clk]    =       125000000,
22         [ddr3a_clk]     =       100000000,
23         [ddr3b_clk]     =       100000000,
24         [mcm_clk]       =       312500000,
25         [pcie_clk]      =       100000000,
26         [sgmii_srio_clk] =      156250000,
27         [xgmii_clk]     =       156250000,
28         [usb_clk]       =       100000000,
29         [rp1_clk]       =       123456789
30 };
31
32 static struct pll_init_data core_pll_config[] = {
33         CORE_PLL_799,
34         CORE_PLL_999,
35         CORE_PLL_1200,
36 };
37
38 s16 divn_val[16] = {
39         0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
40 };
41
42 static struct pll_init_data tetris_pll_config[] = {
43         TETRIS_PLL_800,
44         TETRIS_PLL_1000,
45         TETRIS_PLL_1200,
46         TETRIS_PLL_1350,
47         TETRIS_PLL_1400,
48 };
49
50 static struct pll_init_data pa_pll_config =
51         PASS_PLL_983;
52
53 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
54 struct eth_priv_t eth_priv_cfg[] = {
55         {
56                 .int_name       = "K2HK_EMAC",
57                 .rx_flow        = 22,
58                 .phy_addr       = 0,
59                 .slave_port     = 1,
60                 .sgmii_link_type = SGMII_LINK_MAC_PHY,
61         },
62         {
63                 .int_name       = "K2HK_EMAC1",
64                 .rx_flow        = 23,
65                 .phy_addr       = 1,
66                 .slave_port     = 2,
67                 .sgmii_link_type = SGMII_LINK_MAC_PHY,
68         },
69         {
70                 .int_name       = "K2HK_EMAC2",
71                 .rx_flow        = 24,
72                 .phy_addr       = 2,
73                 .slave_port     = 3,
74                 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
75         },
76         {
77                 .int_name       = "K2HK_EMAC3",
78                 .rx_flow        = 25,
79                 .phy_addr       = 3,
80                 .slave_port     = 4,
81                 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
82         },
83 };
84
85 int get_num_eth_ports(void)
86 {
87         return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
88 }
89 #endif
90
91 #ifdef CONFIG_BOARD_EARLY_INIT_F
92 int board_early_init_f(void)
93 {
94         int speed;
95
96         speed = get_max_dev_speed();
97         init_pll(&core_pll_config[speed]);
98
99         init_pll(&pa_pll_config);
100
101         speed = get_max_arm_speed();
102         init_pll(&tetris_pll_config[speed]);
103
104         return 0;
105 }
106 #endif
107
108 #ifdef CONFIG_SPL_BUILD
109 static struct pll_init_data spl_pll_config[] = {
110         CORE_PLL_799,
111         TETRIS_PLL_500,
112 };
113
114 void spl_init_keystone_plls(void)
115 {
116         init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
117 }
118 #endif